1; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+f64mm -asm-verbose=0 < %s 2>%t | FileCheck %s 2; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t 3 4; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it. 5; WARN-NOT: warning 6 7; 8; LD1ROB 9; 10 11define <vscale x 16 x i8> @ld1rob_i8(<vscale x 16 x i1> %pred, i8* %addr) nounwind { 12; CHECK-LABEL: ld1rob_i8: 13; CHECK-NEXT: ld1rob { z0.b }, p0/z, [x0] 14; CHECK-NEXT: ret 15 %res = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1> %pred, i8* %addr) 16 ret <vscale x 16 x i8> %res 17} 18 19; 20; LD1ROH 21; 22 23define <vscale x 8 x i16> @ld1roh_i16(<vscale x 8 x i1> %pred, i16* %addr) nounwind { 24; CHECK-LABEL: ld1roh_i16: 25; CHECK-NEXT: ld1roh { z0.h }, p0/z, [x0] 26; CHECK-NEXT: ret 27 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16(<vscale x 8 x i1> %pred, i16* %addr) 28 ret <vscale x 8 x i16> %res 29} 30 31define <vscale x 8 x half> @ld1roh_half(<vscale x 8 x i1> %pred, half* %addr) nounwind { 32; CHECK-LABEL: ld1roh_half: 33; CHECK-NEXT: ld1roh { z0.h }, p0/z, [x0] 34; CHECK-NEXT: ret 35 %res = call <vscale x 8 x half> @llvm.aarch64.sve.ld1ro.nxv8f16(<vscale x 8 x i1> %pred, half* %addr) 36 ret <vscale x 8 x half> %res 37} 38 39; 40; LD1ROW 41; 42 43define <vscale x 4 x i32> @ld1row_i32(<vscale x 4 x i1> %pred, i32* %addr) nounwind { 44; CHECK-LABEL: ld1row_i32: 45; CHECK-NEXT: ld1row { z0.s }, p0/z, [x0] 46; CHECK-NEXT: ret 47 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32(<vscale x 4 x i1> %pred, i32* %addr) 48 ret <vscale x 4 x i32> %res 49} 50 51define <vscale x 4 x float> @ld1row_float(<vscale x 4 x i1> %pred, float* %addr) nounwind { 52; CHECK-LABEL: ld1row_float: 53; CHECK-NEXT: ld1row { z0.s }, p0/z, [x0] 54; CHECK-NEXT: ret 55 %res = call <vscale x 4 x float> @llvm.aarch64.sve.ld1ro.nxv4f32(<vscale x 4 x i1> %pred, float* %addr) 56 ret <vscale x 4 x float> %res 57} 58 59; 60; LD1ROD 61; 62 63define <vscale x 2 x i64> @ld1rod_i64(<vscale x 2 x i1> %pred, i64* %addr) nounwind { 64; CHECK-LABEL: ld1rod_i64: 65; CHECK-NEXT: ld1rod { z0.d }, p0/z, [x0] 66; CHECK-NEXT: ret 67 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64(<vscale x 2 x i1> %pred, i64* %addr) 68 ret <vscale x 2 x i64> %res 69} 70 71define <vscale x 2 x double> @ld1rod_double(<vscale x 2 x i1> %pred, double* %addr) nounwind { 72; CHECK-LABEL: ld1rod_double: 73; CHECK-NEXT: ld1rod { z0.d }, p0/z, [x0] 74; CHECK-NEXT: ret 75 %res = call <vscale x 2 x double> @llvm.aarch64.sve.ld1ro.nxv2f64(<vscale x 2 x i1> %pred, double* %addr) 76 ret <vscale x 2 x double> %res 77} 78 79declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1>, i8*) 80 81declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16(<vscale x 8 x i1>, i16*) 82declare <vscale x 8 x half> @llvm.aarch64.sve.ld1ro.nxv8f16(<vscale x 8 x i1>, half*) 83 84declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32(<vscale x 4 x i1>, i32*) 85declare <vscale x 4 x float> @llvm.aarch64.sve.ld1ro.nxv4f32(<vscale x 4 x i1>, float*) 86 87declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64(<vscale x 2 x i1>, i64*) 88declare <vscale x 2 x double> @llvm.aarch64.sve.ld1ro.nxv2f64(<vscale x 2 x i1>, double*) 89