1; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
2; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
3
4; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
5; WARN-NOT: warning
6
7;
8; SEL (Vectors)
9;
10
11define <vscale x 16 x i1> @sel_i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
12; CHECK-LABEL: sel_i1:
13; CHECK: sel p0.b, p0, p1.b, p2.b
14; CHECK-NEXT: ret
15  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.sel.nxv16i1(<vscale x 16 x i1> %pg,
16                                                               <vscale x 16 x i1> %a,
17                                                               <vscale x 16 x i1> %b)
18  ret <vscale x 16 x i1> %out
19}
20
21define <vscale x 16 x i8> @sel_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
22; CHECK-LABEL: sel_i8:
23; CHECK: sel z0.b, p0, z0.b, z1.b
24; CHECK-NEXT: ret
25  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg,
26                                                               <vscale x 16 x i8> %a,
27                                                               <vscale x 16 x i8> %b)
28  ret <vscale x 16 x i8> %out
29}
30
31define <vscale x 8 x i16> @sel_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
32; CHECK-LABEL: sel_i16:
33; CHECK: sel z0.h, p0, z0.h, z1.h
34; CHECK-NEXT: ret
35  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %pg,
36                                                               <vscale x 8 x i16> %a,
37                                                               <vscale x 8 x i16> %b)
38  ret <vscale x 8 x i16> %out
39}
40
41define <vscale x 4 x i32> @sel_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
42; CHECK-LABEL: sel_i32:
43; CHECK: sel z0.s, p0, z0.s, z1.s
44; CHECK-NEXT: ret
45  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %pg,
46                                                               <vscale x 4 x i32> %a,
47                                                               <vscale x 4 x i32> %b)
48  ret <vscale x 4 x i32> %out
49}
50
51define <vscale x 2 x i64> @sel_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
52; CHECK-LABEL: sel_i64:
53; CHECK: sel z0.d, p0, z0.d, z1.d
54; CHECK-NEXT: ret
55  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %pg,
56                                                               <vscale x 2 x i64> %a,
57                                                               <vscale x 2 x i64> %b)
58  ret <vscale x 2 x i64> %out
59}
60
61define <vscale x 8 x bfloat> @sel_bf16(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) #0 {
62; CHECK-LABEL: sel_bf16:
63; CHECK: sel z0.h, p0, z0.h, z1.h
64; CHECK-NEXT: ret
65  %out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.sel.nxv8bf16(<vscale x 8 x i1> %pg,
66                                                                   <vscale x 8 x bfloat> %a,
67                                                                   <vscale x 8 x bfloat> %b)
68  ret <vscale x 8 x bfloat> %out
69}
70
71define <vscale x 8 x half> @sel_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
72; CHECK-LABEL: sel_f16:
73; CHECK: sel z0.h, p0, z0.h, z1.h
74; CHECK-NEXT: ret
75  %out = call <vscale x 8 x half> @llvm.aarch64.sve.sel.nxv8f16(<vscale x 8 x i1> %pg,
76                                                                <vscale x 8 x half> %a,
77                                                                <vscale x 8 x half> %b)
78  ret <vscale x 8 x half> %out
79}
80
81define <vscale x 4 x float> @sel_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
82; CHECK-LABEL: sel_f32:
83; CHECK: sel z0.s, p0, z0.s, z1.s
84; CHECK-NEXT: ret
85  %out = call <vscale x 4 x float> @llvm.aarch64.sve.sel.nxv4f32(<vscale x 4 x i1> %pg,
86                                                                 <vscale x 4 x float> %a,
87                                                                 <vscale x 4 x float> %b)
88  ret <vscale x 4 x float> %out
89}
90
91define <vscale x 2 x double> @sel_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
92; CHECK-LABEL: sel_f64:
93; CHECK: sel z0.d, p0, z0.d, z1.d
94; CHECK-NEXT: ret
95  %out = call <vscale x 2 x double> @llvm.aarch64.sve.sel.nxv2f64(<vscale x 2 x i1> %pg,
96                                                                  <vscale x 2 x double> %a,
97                                                                  <vscale x 2 x double> %b)
98  ret <vscale x 2 x double> %out
99}
100
101declare <vscale x 16 x i1> @llvm.aarch64.sve.sel.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
102declare <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
103declare <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
104declare <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
105declare <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
106declare <vscale x 8 x bfloat> @llvm.aarch64.sve.sel.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
107declare <vscale x 8 x half> @llvm.aarch64.sve.sel.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)
108declare <vscale x 4 x float> @llvm.aarch64.sve.sel.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
109declare <vscale x 2 x double> @llvm.aarch64.sve.sel.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
110
111; +bf16 is required for the bfloat version.
112attributes #0 = { "target-features"="+sve,+bf16" }
113