1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s 3; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t 4 5; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it. 6; WARN-NOT: warning 7 8define <vscale x 16 x i8> @sel_8_positive(<vscale x 16 x i1> %p) { 9; CHECK-LABEL: sel_8_positive: 10; CHECK: // %bb.0: 11; CHECK-NEXT: mov z0.b, p0/z, #3 // =0x3 12; CHECK-NEXT: ret 13%vec = shufflevector <vscale x 16 x i8> insertelement (<vscale x 16 x i8> undef, i8 3, i32 0), <vscale x 16 x i8> zeroinitializer, <vscale x 16 x i32> zeroinitializer 14%sel = select <vscale x 16 x i1> %p, <vscale x 16 x i8> %vec, <vscale x 16 x i8> zeroinitializer 15ret <vscale x 16 x i8> %sel 16} 17 18define <vscale x 8 x i16> @sel_16_positive(<vscale x 8 x i1> %p) { 19; CHECK-LABEL: sel_16_positive: 20; CHECK: // %bb.0: 21; CHECK-NEXT: mov z0.h, p0/z, #3 // =0x3 22; CHECK-NEXT: ret 23%vec = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 3, i32 0), <vscale x 8 x i16> zeroinitializer, <vscale x 8 x i32> zeroinitializer 24%sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> %vec, <vscale x 8 x i16> zeroinitializer 25ret <vscale x 8 x i16> %sel 26} 27 28define <vscale x 4 x i32> @sel_32_positive(<vscale x 4 x i1> %p) { 29; CHECK-LABEL: sel_32_positive: 30; CHECK: // %bb.0: 31; CHECK-NEXT: mov z0.s, p0/z, #3 // =0x3 32; CHECK-NEXT: ret 33%vec = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 3, i32 0), <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> zeroinitializer 34%sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> %vec, <vscale x 4 x i32> zeroinitializer 35ret <vscale x 4 x i32> %sel 36} 37 38define <vscale x 2 x i64> @sel_64_positive(<vscale x 2 x i1> %p) { 39; CHECK-LABEL: sel_64_positive: 40; CHECK: // %bb.0: 41; CHECK-NEXT: mov z0.d, p0/z, #3 // =0x3 42; CHECK-NEXT: ret 43%vec = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 3, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer 44%sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> %vec, <vscale x 2 x i64> zeroinitializer 45ret <vscale x 2 x i64> %sel 46} 47 48define <vscale x 16 x i8> @sel_8_negative(<vscale x 16 x i1> %p) { 49; CHECK-LABEL: sel_8_negative: 50; CHECK: // %bb.0: 51; CHECK-NEXT: mov z0.b, p0/z, #-128 // =0xffffffffffffff80 52; CHECK-NEXT: ret 53%vec = shufflevector <vscale x 16 x i8> insertelement (<vscale x 16 x i8> undef, i8 -128, i32 0), <vscale x 16 x i8> zeroinitializer, <vscale x 16 x i32> zeroinitializer 54%sel = select <vscale x 16 x i1> %p, <vscale x 16 x i8> %vec, <vscale x 16 x i8> zeroinitializer 55ret <vscale x 16 x i8> %sel 56} 57 58define <vscale x 8 x i16> @sel_16_negative(<vscale x 8 x i1> %p) { 59; CHECK-LABEL: sel_16_negative: 60; CHECK: // %bb.0: 61; CHECK-NEXT: mov z0.h, p0/z, #-128 // =0xffffffffffffff80 62; CHECK-NEXT: ret 63%vec = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 -128, i32 0), <vscale x 8 x i16> zeroinitializer, <vscale x 8 x i32> zeroinitializer 64%sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> %vec, <vscale x 8 x i16> zeroinitializer 65ret <vscale x 8 x i16> %sel 66} 67 68define <vscale x 4 x i32> @sel_32_negative(<vscale x 4 x i1> %p) { 69; CHECK-LABEL: sel_32_negative: 70; CHECK: // %bb.0: 71; CHECK-NEXT: mov z0.s, p0/z, #-128 // =0xffffffffffffff80 72; CHECK-NEXT: ret 73%vec = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 -128, i32 0), <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> zeroinitializer 74%sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> %vec, <vscale x 4 x i32> zeroinitializer 75ret <vscale x 4 x i32> %sel 76} 77 78define <vscale x 2 x i64> @sel_64_negative(<vscale x 2 x i1> %p) { 79; CHECK-LABEL: sel_64_negative: 80; CHECK: // %bb.0: 81; CHECK-NEXT: mov z0.d, p0/z, #-128 // =0xffffffffffffff80 82; CHECK-NEXT: ret 83%vec = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 -128, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer 84%sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> %vec, <vscale x 2 x i64> zeroinitializer 85ret <vscale x 2 x i64> %sel 86} 87 88define <vscale x 8 x i16> @sel_16_shifted(<vscale x 8 x i1> %p) { 89; CHECK-LABEL: sel_16_shifted: 90; CHECK: // %bb.0: 91; CHECK-NEXT: mov z0.h, p0/z, #512 // =0x200 92; CHECK-NEXT: ret 93%vec = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 512, i32 0), <vscale x 8 x i16> zeroinitializer, <vscale x 8 x i32> zeroinitializer 94%sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> %vec, <vscale x 8 x i16> zeroinitializer 95ret <vscale x 8 x i16> %sel 96} 97 98define <vscale x 4 x i32> @sel_32_shifted(<vscale x 4 x i1> %p) { 99; CHECK-LABEL: sel_32_shifted: 100; CHECK: // %bb.0: 101; CHECK-NEXT: mov z0.s, p0/z, #512 // =0x200 102; CHECK-NEXT: ret 103%vec = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 512, i32 0), <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> zeroinitializer 104%sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> %vec, <vscale x 4 x i32> zeroinitializer 105ret <vscale x 4 x i32> %sel 106} 107 108define <vscale x 2 x i64> @sel_64_shifted(<vscale x 2 x i1> %p) { 109; CHECK-LABEL: sel_64_shifted: 110; CHECK: // %bb.0: 111; CHECK-NEXT: mov z0.d, p0/z, #512 // =0x200 112; CHECK-NEXT: ret 113%vec = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 512, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer 114%sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> %vec, <vscale x 2 x i64> zeroinitializer 115ret <vscale x 2 x i64> %sel 116} 117 118; TODO: We could actually use something like "cpy z0.b, p0/z, #-128". But it's 119; a little tricky to prove correctness: we're using the predicate with the 120; wrong width, so we'd have to prove the bits which would normally be unused 121; are actually zero. 122define <vscale x 8 x i16> @sel_16_illegal_wrong_extension(<vscale x 8 x i1> %p) { 123; CHECK-LABEL: sel_16_illegal_wrong_extension: 124; CHECK: // %bb.0: 125; CHECK-NEXT: mov w8, #128 126; CHECK-NEXT: mov z0.h, w8 127; CHECK-NEXT: mov z1.h, #0 // =0x0 128; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h 129; CHECK-NEXT: ret 130%vec = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 128, i32 0), <vscale x 8 x i16> zeroinitializer, <vscale x 8 x i32> zeroinitializer 131%sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> %vec, <vscale x 8 x i16> zeroinitializer 132ret <vscale x 8 x i16> %sel 133} 134 135define <vscale x 4 x i32> @sel_32_illegal_wrong_extension(<vscale x 4 x i1> %p) { 136; CHECK-LABEL: sel_32_illegal_wrong_extension: 137; CHECK: // %bb.0: 138; CHECK-NEXT: mov w8, #128 139; CHECK-NEXT: mov z0.s, w8 140; CHECK-NEXT: mov z1.s, #0 // =0x0 141; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s 142; CHECK-NEXT: ret 143%vec = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 128, i32 0), <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> zeroinitializer 144%sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> %vec, <vscale x 4 x i32> zeroinitializer 145ret <vscale x 4 x i32> %sel 146} 147 148define <vscale x 2 x i64> @sel_64_illegal_wrong_extension(<vscale x 2 x i1> %p) { 149; CHECK-LABEL: sel_64_illegal_wrong_extension: 150; CHECK: // %bb.0: 151; CHECK-NEXT: mov w8, #128 152; CHECK-NEXT: mov z0.d, x8 153; CHECK-NEXT: mov z1.d, #0 // =0x0 154; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d 155; CHECK-NEXT: ret 156%vec = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 128, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer 157%sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> %vec, <vscale x 2 x i64> zeroinitializer 158ret <vscale x 2 x i64> %sel 159} 160 161define <vscale x 8 x i16> @sel_16_illegal_shifted(<vscale x 8 x i1> %p) { 162; CHECK-LABEL: sel_16_illegal_shifted: 163; CHECK: // %bb.0: 164; CHECK-NEXT: mov w8, #513 165; CHECK-NEXT: mov z0.h, w8 166; CHECK-NEXT: mov z1.h, #0 // =0x0 167; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h 168; CHECK-NEXT: ret 169%vec = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 513, i32 0), <vscale x 8 x i16> zeroinitializer, <vscale x 8 x i32> zeroinitializer 170%sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> %vec, <vscale x 8 x i16> zeroinitializer 171ret <vscale x 8 x i16> %sel 172} 173 174define <vscale x 4 x i32> @sel_32_illegal_shifted(<vscale x 4 x i1> %p) { 175; CHECK-LABEL: sel_32_illegal_shifted: 176; CHECK: // %bb.0: 177; CHECK-NEXT: mov w8, #513 178; CHECK-NEXT: mov z0.s, w8 179; CHECK-NEXT: mov z1.s, #0 // =0x0 180; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s 181; CHECK-NEXT: ret 182%vec = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 513, i32 0), <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> zeroinitializer 183%sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> %vec, <vscale x 4 x i32> zeroinitializer 184ret <vscale x 4 x i32> %sel 185} 186 187define <vscale x 2 x i64> @sel_64_illegal_shifted(<vscale x 2 x i1> %p) { 188; CHECK-LABEL: sel_64_illegal_shifted: 189; CHECK: // %bb.0: 190; CHECK-NEXT: mov w8, #513 191; CHECK-NEXT: mov z0.d, x8 192; CHECK-NEXT: mov z1.d, #0 // =0x0 193; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d 194; CHECK-NEXT: ret 195%vec = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 513, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer 196%sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> %vec, <vscale x 2 x i64> zeroinitializer 197ret <vscale x 2 x i64> %sel 198} 199 200define <vscale x 16 x i8> @sel_merge_8_positive(<vscale x 16 x i1> %p, <vscale x 16 x i8> %in) { 201; CHECK-LABEL: sel_merge_8_positive: 202; CHECK: // %bb.0: 203; CHECK-NEXT: mov z0.b, p0/m, #3 // =0x3 204; CHECK-NEXT: ret 205%vec = shufflevector <vscale x 16 x i8> insertelement (<vscale x 16 x i8> undef, i8 3, i32 0), <vscale x 16 x i8> zeroinitializer, <vscale x 16 x i32> zeroinitializer 206%sel = select <vscale x 16 x i1> %p, <vscale x 16 x i8> %vec, <vscale x 16 x i8> %in 207ret <vscale x 16 x i8> %sel 208} 209 210define <vscale x 8 x i16> @sel_merge_16_positive(<vscale x 8 x i1> %p, <vscale x 8 x i16> %in) { 211; CHECK-LABEL: sel_merge_16_positive: 212; CHECK: // %bb.0: 213; CHECK-NEXT: mov z0.h, p0/m, #3 // =0x3 214; CHECK-NEXT: ret 215%vec = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 3, i32 0), <vscale x 8 x i16> zeroinitializer, <vscale x 8 x i32> zeroinitializer 216%sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> %vec, <vscale x 8 x i16> %in 217ret <vscale x 8 x i16> %sel 218} 219 220define <vscale x 4 x i32> @sel_merge_32_positive(<vscale x 4 x i1> %p, <vscale x 4 x i32> %in) { 221; CHECK-LABEL: sel_merge_32_positive: 222; CHECK: // %bb.0: 223; CHECK-NEXT: mov z0.s, p0/m, #3 // =0x3 224; CHECK-NEXT: ret 225%vec = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 3, i32 0), <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> zeroinitializer 226%sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> %vec, <vscale x 4 x i32> %in 227ret <vscale x 4 x i32> %sel 228} 229 230define <vscale x 2 x i64> @sel_merge_64_positive(<vscale x 2 x i1> %p, <vscale x 2 x i64> %in) { 231; CHECK-LABEL: sel_merge_64_positive: 232; CHECK: // %bb.0: 233; CHECK-NEXT: mov z0.d, p0/m, #3 // =0x3 234; CHECK-NEXT: ret 235%vec = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 3, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer 236%sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> %vec, <vscale x 2 x i64> %in 237ret <vscale x 2 x i64> %sel 238} 239 240define <vscale x 16 x i8> @sel_merge_8_negative(<vscale x 16 x i1> %p, <vscale x 16 x i8> %in) { 241; CHECK-LABEL: sel_merge_8_negative: 242; CHECK: // %bb.0: 243; CHECK-NEXT: mov z0.b, p0/m, #-128 // =0xffffffffffffff80 244; CHECK-NEXT: ret 245%vec = shufflevector <vscale x 16 x i8> insertelement (<vscale x 16 x i8> undef, i8 -128, i32 0), <vscale x 16 x i8> zeroinitializer, <vscale x 16 x i32> zeroinitializer 246%sel = select <vscale x 16 x i1> %p, <vscale x 16 x i8> %vec, <vscale x 16 x i8> %in 247ret <vscale x 16 x i8> %sel 248} 249 250define <vscale x 8 x i16> @sel_merge_16_negative(<vscale x 8 x i1> %p, <vscale x 8 x i16> %in) { 251; CHECK-LABEL: sel_merge_16_negative: 252; CHECK: // %bb.0: 253; CHECK-NEXT: mov z0.h, p0/m, #-128 // =0xffffffffffffff80 254; CHECK-NEXT: ret 255%vec = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 -128, i32 0), <vscale x 8 x i16> zeroinitializer, <vscale x 8 x i32> zeroinitializer 256%sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> %vec, <vscale x 8 x i16> %in 257ret <vscale x 8 x i16> %sel 258} 259 260define <vscale x 4 x i32> @sel_merge_32_negative(<vscale x 4 x i1> %p, <vscale x 4 x i32> %in) { 261; CHECK-LABEL: sel_merge_32_negative: 262; CHECK: // %bb.0: 263; CHECK-NEXT: mov z0.s, p0/m, #-128 // =0xffffffffffffff80 264; CHECK-NEXT: ret 265%vec = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 -128, i32 0), <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> zeroinitializer 266%sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> %vec, <vscale x 4 x i32> %in 267ret <vscale x 4 x i32> %sel 268} 269 270define <vscale x 2 x i64> @sel_merge_64_negative(<vscale x 2 x i1> %p, <vscale x 2 x i64> %in) { 271; CHECK-LABEL: sel_merge_64_negative: 272; CHECK: // %bb.0: 273; CHECK-NEXT: mov z0.d, p0/m, #-128 // =0xffffffffffffff80 274; CHECK-NEXT: ret 275%vec = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 -128, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer 276%sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> %vec, <vscale x 2 x i64> %in 277ret <vscale x 2 x i64> %sel 278} 279 280define <vscale x 16 x i8> @sel_merge_8_zero(<vscale x 16 x i1> %p, <vscale x 16 x i8> %in) { 281; CHECK-LABEL: sel_merge_8_zero: 282; CHECK: // %bb.0: 283; CHECK-NEXT: mov z0.b, p0/m, #0 // =0x0 284; CHECK-NEXT: ret 285%sel = select <vscale x 16 x i1> %p, <vscale x 16 x i8> zeroinitializer, <vscale x 16 x i8> %in 286ret <vscale x 16 x i8> %sel 287} 288 289define <vscale x 8 x i16> @sel_merge_16_zero(<vscale x 8 x i1> %p, <vscale x 8 x i16> %in) { 290; CHECK-LABEL: sel_merge_16_zero: 291; CHECK: // %bb.0: 292; CHECK-NEXT: mov z0.h, p0/m, #0 // =0x0 293; CHECK-NEXT: ret 294%sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> zeroinitializer, <vscale x 8 x i16> %in 295ret <vscale x 8 x i16> %sel 296} 297 298define <vscale x 4 x i32> @sel_merge_32_zero(<vscale x 4 x i1> %p, <vscale x 4 x i32> %in) { 299; CHECK-LABEL: sel_merge_32_zero: 300; CHECK: // %bb.0: 301; CHECK-NEXT: mov z0.s, p0/m, #0 // =0x0 302; CHECK-NEXT: ret 303%sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> %in 304ret <vscale x 4 x i32> %sel 305} 306 307define <vscale x 2 x i64> @sel_merge_64_zero(<vscale x 2 x i1> %p, <vscale x 2 x i64> %in) { 308; CHECK-LABEL: sel_merge_64_zero: 309; CHECK: // %bb.0: 310; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0 311; CHECK-NEXT: ret 312%sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i64> %in 313ret <vscale x 2 x i64> %sel 314} 315 316define <vscale x 8 x i16> @sel_merge_16_shifted(<vscale x 8 x i1> %p, <vscale x 8 x i16> %in) { 317; CHECK-LABEL: sel_merge_16_shifted: 318; CHECK: // %bb.0: 319; CHECK-NEXT: mov z0.h, p0/m, #512 // =0x200 320; CHECK-NEXT: ret 321%vec = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 512, i32 0), <vscale x 8 x i16> zeroinitializer, <vscale x 8 x i32> zeroinitializer 322%sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> %vec, <vscale x 8 x i16> %in 323ret <vscale x 8 x i16> %sel 324} 325 326define <vscale x 4 x i32> @sel_merge_32_shifted(<vscale x 4 x i1> %p, <vscale x 4 x i32> %in) { 327; CHECK-LABEL: sel_merge_32_shifted: 328; CHECK: // %bb.0: 329; CHECK-NEXT: mov z0.s, p0/m, #512 // =0x200 330; CHECK-NEXT: ret 331%vec = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 512, i32 0), <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> zeroinitializer 332%sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> %vec, <vscale x 4 x i32> %in 333ret <vscale x 4 x i32> %sel 334} 335 336define <vscale x 2 x i64> @sel_merge_64_shifted(<vscale x 2 x i1> %p, <vscale x 2 x i64> %in) { 337; CHECK-LABEL: sel_merge_64_shifted: 338; CHECK: // %bb.0: 339; CHECK-NEXT: mov z0.d, p0/m, #512 // =0x200 340; CHECK-NEXT: ret 341%vec = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 512, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer 342%sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> %vec, <vscale x 2 x i64> %in 343ret <vscale x 2 x i64> %sel 344} 345 346; TODO: We could actually use something like "cpy z0.b, p0/m, #-128". But it's 347; a little tricky to prove correctness: we're using the predicate with the 348; wrong width, so we'd have to prove the bits which would normally be unused 349; are actually zero. 350define <vscale x 8 x i16> @sel_merge_16_illegal_wrong_extension(<vscale x 8 x i1> %p, <vscale x 8 x i16> %in) { 351; CHECK-LABEL: sel_merge_16_illegal_wrong_extension: 352; CHECK: // %bb.0: 353; CHECK-NEXT: mov w8, #128 354; CHECK-NEXT: mov z1.h, w8 355; CHECK-NEXT: mov z0.h, p0/m, z1.h 356; CHECK-NEXT: ret 357%vec = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 128, i32 0), <vscale x 8 x i16> zeroinitializer, <vscale x 8 x i32> zeroinitializer 358%sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> %vec, <vscale x 8 x i16> %in 359ret <vscale x 8 x i16> %sel 360} 361 362define <vscale x 4 x i32> @sel_merge_32_illegal_wrong_extension(<vscale x 4 x i1> %p, <vscale x 4 x i32> %in) { 363; CHECK-LABEL: sel_merge_32_illegal_wrong_extension: 364; CHECK: // %bb.0: 365; CHECK-NEXT: mov w8, #128 366; CHECK-NEXT: mov z1.s, w8 367; CHECK-NEXT: mov z0.s, p0/m, z1.s 368; CHECK-NEXT: ret 369%vec = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 128, i32 0), <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> zeroinitializer 370%sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> %vec, <vscale x 4 x i32> %in 371ret <vscale x 4 x i32> %sel 372} 373 374define <vscale x 2 x i64> @sel_merge_64_illegal_wrong_extension(<vscale x 2 x i1> %p, <vscale x 2 x i64> %in) { 375; CHECK-LABEL: sel_merge_64_illegal_wrong_extension: 376; CHECK: // %bb.0: 377; CHECK-NEXT: mov w8, #128 378; CHECK-NEXT: mov z1.d, x8 379; CHECK-NEXT: mov z0.d, p0/m, z1.d 380; CHECK-NEXT: ret 381%vec = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 128, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer 382%sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> %vec, <vscale x 2 x i64> %in 383ret <vscale x 2 x i64> %sel 384} 385 386define <vscale x 8 x i16> @sel_merge_16_illegal_shifted(<vscale x 8 x i1> %p, <vscale x 8 x i16> %in) { 387; CHECK-LABEL: sel_merge_16_illegal_shifted: 388; CHECK: // %bb.0: 389; CHECK-NEXT: mov w8, #513 390; CHECK-NEXT: mov z1.h, w8 391; CHECK-NEXT: mov z0.h, p0/m, z1.h 392; CHECK-NEXT: ret 393%vec = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 513, i32 0), <vscale x 8 x i16> zeroinitializer, <vscale x 8 x i32> zeroinitializer 394%sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> %vec, <vscale x 8 x i16> %in 395ret <vscale x 8 x i16> %sel 396} 397 398define <vscale x 4 x i32> @sel_merge_32_illegal_shifted(<vscale x 4 x i1> %p, <vscale x 4 x i32> %in) { 399; CHECK-LABEL: sel_merge_32_illegal_shifted: 400; CHECK: // %bb.0: 401; CHECK-NEXT: mov w8, #513 402; CHECK-NEXT: mov z1.s, w8 403; CHECK-NEXT: mov z0.s, p0/m, z1.s 404; CHECK-NEXT: ret 405%vec = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 513, i32 0), <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> zeroinitializer 406%sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> %vec, <vscale x 4 x i32> %in 407ret <vscale x 4 x i32> %sel 408} 409 410define <vscale x 2 x i64> @sel_merge_64_illegal_shifted(<vscale x 2 x i1> %p, <vscale x 2 x i64> %in) { 411; CHECK-LABEL: sel_merge_64_illegal_shifted: 412; CHECK: // %bb.0: 413; CHECK-NEXT: mov w8, #513 414; CHECK-NEXT: mov z1.d, x8 415; CHECK-NEXT: mov z0.d, p0/m, z1.d 416; CHECK-NEXT: ret 417%vec = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 513, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer 418%sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> %vec, <vscale x 2 x i64> %in 419ret <vscale x 2 x i64> %sel 420} 421