1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
3
4; Odd+Even divisors
5define <4 x i32> @test_urem_odd_even(<4 x i32> %X) nounwind {
6; CHECK-LABEL: test_urem_odd_even:
7; CHECK:       // %bb.0:
8; CHECK-NEXT:    adrp x8, .LCPI0_0
9; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI0_0]
10; CHECK-NEXT:    adrp x8, .LCPI0_1
11; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI0_1]
12; CHECK-NEXT:    adrp x8, .LCPI0_2
13; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI0_2]
14; CHECK-NEXT:    neg v1.4s, v1.4s
15; CHECK-NEXT:    adrp x8, .LCPI0_3
16; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
17; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
18; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
19; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI0_3]
20; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
21; CHECK-NEXT:    neg v3.4s, v3.4s
22; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
23; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
24; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
25; CHECK-NEXT:    movi v1.4s, #1
26; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
27; CHECK-NEXT:    ret
28  %urem = urem <4 x i32> %X, <i32 5, i32 14, i32 25, i32 100>
29  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
30  %ret = zext <4 x i1> %cmp to <4 x i32>
31  ret <4 x i32> %ret
32}
33
34;==============================================================================;
35
36; One all-ones divisor in odd divisor
37define <4 x i32> @test_urem_odd_allones_eq(<4 x i32> %X) nounwind {
38; CHECK-LABEL: test_urem_odd_allones_eq:
39; CHECK:       // %bb.0:
40; CHECK-NEXT:    adrp x8, .LCPI1_0
41; CHECK-NEXT:    adrp x9, .LCPI1_1
42; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI1_0]
43; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI1_1]
44; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
45; CHECK-NEXT:    cmhs v0.4s, v2.4s, v0.4s
46; CHECK-NEXT:    movi v1.4s, #1
47; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
48; CHECK-NEXT:    ret
49  %urem = urem <4 x i32> %X, <i32 5, i32 5, i32 4294967295, i32 5>
50  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
51  %ret = zext <4 x i1> %cmp to <4 x i32>
52  ret <4 x i32> %ret
53}
54define <4 x i32> @test_urem_odd_allones_ne(<4 x i32> %X) nounwind {
55; CHECK-LABEL: test_urem_odd_allones_ne:
56; CHECK:       // %bb.0:
57; CHECK-NEXT:    adrp x8, .LCPI2_0
58; CHECK-NEXT:    adrp x9, .LCPI2_1
59; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI2_0]
60; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI2_1]
61; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
62; CHECK-NEXT:    cmhi v0.4s, v0.4s, v2.4s
63; CHECK-NEXT:    movi v1.4s, #1
64; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
65; CHECK-NEXT:    ret
66  %urem = urem <4 x i32> %X, <i32 5, i32 5, i32 4294967295, i32 5>
67  %cmp = icmp ne <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
68  %ret = zext <4 x i1> %cmp to <4 x i32>
69  ret <4 x i32> %ret
70}
71
72; One all-ones divisor in even divisor
73define <4 x i32> @test_urem_even_allones_eq(<4 x i32> %X) nounwind {
74; CHECK-LABEL: test_urem_even_allones_eq:
75; CHECK:       // %bb.0:
76; CHECK-NEXT:    adrp x8, .LCPI3_0
77; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI3_0]
78; CHECK-NEXT:    adrp x8, .LCPI3_1
79; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI3_1]
80; CHECK-NEXT:    adrp x8, .LCPI3_2
81; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI3_2]
82; CHECK-NEXT:    neg v1.4s, v1.4s
83; CHECK-NEXT:    adrp x8, .LCPI3_3
84; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
85; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
86; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
87; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI3_3]
88; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
89; CHECK-NEXT:    neg v3.4s, v3.4s
90; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
91; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
92; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
93; CHECK-NEXT:    movi v1.4s, #1
94; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
95; CHECK-NEXT:    ret
96  %urem = urem <4 x i32> %X, <i32 14, i32 14, i32 4294967295, i32 14>
97  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
98  %ret = zext <4 x i1> %cmp to <4 x i32>
99  ret <4 x i32> %ret
100}
101define <4 x i32> @test_urem_even_allones_ne(<4 x i32> %X) nounwind {
102; CHECK-LABEL: test_urem_even_allones_ne:
103; CHECK:       // %bb.0:
104; CHECK-NEXT:    adrp x8, .LCPI4_0
105; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI4_0]
106; CHECK-NEXT:    adrp x8, .LCPI4_1
107; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI4_1]
108; CHECK-NEXT:    adrp x8, .LCPI4_2
109; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI4_2]
110; CHECK-NEXT:    neg v1.4s, v1.4s
111; CHECK-NEXT:    adrp x8, .LCPI4_3
112; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
113; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
114; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
115; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI4_3]
116; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
117; CHECK-NEXT:    neg v3.4s, v3.4s
118; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
119; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
120; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
121; CHECK-NEXT:    mvn v0.16b, v0.16b
122; CHECK-NEXT:    movi v1.4s, #1
123; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
124; CHECK-NEXT:    ret
125  %urem = urem <4 x i32> %X, <i32 14, i32 14, i32 4294967295, i32 14>
126  %cmp = icmp ne <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
127  %ret = zext <4 x i1> %cmp to <4 x i32>
128  ret <4 x i32> %ret
129}
130
131; One all-ones divisor in odd+even divisor
132define <4 x i32> @test_urem_odd_even_allones_eq(<4 x i32> %X) nounwind {
133; CHECK-LABEL: test_urem_odd_even_allones_eq:
134; CHECK:       // %bb.0:
135; CHECK-NEXT:    adrp x8, .LCPI5_0
136; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI5_0]
137; CHECK-NEXT:    adrp x8, .LCPI5_1
138; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI5_1]
139; CHECK-NEXT:    adrp x8, .LCPI5_2
140; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI5_2]
141; CHECK-NEXT:    neg v1.4s, v1.4s
142; CHECK-NEXT:    adrp x8, .LCPI5_3
143; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
144; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
145; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
146; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI5_3]
147; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
148; CHECK-NEXT:    neg v3.4s, v3.4s
149; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
150; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
151; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
152; CHECK-NEXT:    movi v1.4s, #1
153; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
154; CHECK-NEXT:    ret
155  %urem = urem <4 x i32> %X, <i32 5, i32 14, i32 4294967295, i32 100>
156  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
157  %ret = zext <4 x i1> %cmp to <4 x i32>
158  ret <4 x i32> %ret
159}
160define <4 x i32> @test_urem_odd_even_allones_ne(<4 x i32> %X) nounwind {
161; CHECK-LABEL: test_urem_odd_even_allones_ne:
162; CHECK:       // %bb.0:
163; CHECK-NEXT:    adrp x8, .LCPI6_0
164; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI6_0]
165; CHECK-NEXT:    adrp x8, .LCPI6_1
166; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI6_1]
167; CHECK-NEXT:    adrp x8, .LCPI6_2
168; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI6_2]
169; CHECK-NEXT:    neg v1.4s, v1.4s
170; CHECK-NEXT:    adrp x8, .LCPI6_3
171; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
172; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
173; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
174; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI6_3]
175; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
176; CHECK-NEXT:    neg v3.4s, v3.4s
177; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
178; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
179; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
180; CHECK-NEXT:    mvn v0.16b, v0.16b
181; CHECK-NEXT:    movi v1.4s, #1
182; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
183; CHECK-NEXT:    ret
184  %urem = urem <4 x i32> %X, <i32 5, i32 14, i32 4294967295, i32 100>
185  %cmp = icmp ne <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
186  %ret = zext <4 x i1> %cmp to <4 x i32>
187  ret <4 x i32> %ret
188}
189
190;------------------------------------------------------------------------------;
191
192; One power-of-two divisor in odd divisor
193define <4 x i32> @test_urem_odd_poweroftwo(<4 x i32> %X) nounwind {
194; CHECK-LABEL: test_urem_odd_poweroftwo:
195; CHECK:       // %bb.0:
196; CHECK-NEXT:    adrp x8, .LCPI7_0
197; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI7_0]
198; CHECK-NEXT:    adrp x8, .LCPI7_1
199; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI7_1]
200; CHECK-NEXT:    adrp x8, .LCPI7_2
201; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI7_2]
202; CHECK-NEXT:    umull2 v4.2d, v0.4s, v1.4s
203; CHECK-NEXT:    umull v1.2d, v0.2s, v1.2s
204; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
205; CHECK-NEXT:    neg v2.4s, v2.4s
206; CHECK-NEXT:    ushl v1.4s, v1.4s, v2.4s
207; CHECK-NEXT:    mls v0.4s, v1.4s, v3.4s
208; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
209; CHECK-NEXT:    movi v1.4s, #1
210; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
211; CHECK-NEXT:    ret
212  %urem = urem <4 x i32> %X, <i32 5, i32 5, i32 16, i32 5>
213  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
214  %ret = zext <4 x i1> %cmp to <4 x i32>
215  ret <4 x i32> %ret
216}
217
218; One power-of-two divisor in even divisor
219define <4 x i32> @test_urem_even_poweroftwo(<4 x i32> %X) nounwind {
220; CHECK-LABEL: test_urem_even_poweroftwo:
221; CHECK:       // %bb.0:
222; CHECK-NEXT:    adrp x8, .LCPI8_0
223; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI8_0]
224; CHECK-NEXT:    adrp x8, .LCPI8_1
225; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI8_1]
226; CHECK-NEXT:    adrp x8, .LCPI8_2
227; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI8_2]
228; CHECK-NEXT:    neg v1.4s, v1.4s
229; CHECK-NEXT:    adrp x8, .LCPI8_3
230; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
231; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
232; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
233; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI8_3]
234; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
235; CHECK-NEXT:    neg v3.4s, v3.4s
236; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
237; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
238; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
239; CHECK-NEXT:    movi v1.4s, #1
240; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
241; CHECK-NEXT:    ret
242  %urem = urem <4 x i32> %X, <i32 14, i32 14, i32 16, i32 14>
243  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
244  %ret = zext <4 x i1> %cmp to <4 x i32>
245  ret <4 x i32> %ret
246}
247
248; One power-of-two divisor in odd+even divisor
249define <4 x i32> @test_urem_odd_even_poweroftwo(<4 x i32> %X) nounwind {
250; CHECK-LABEL: test_urem_odd_even_poweroftwo:
251; CHECK:       // %bb.0:
252; CHECK-NEXT:    adrp x8, .LCPI9_0
253; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI9_0]
254; CHECK-NEXT:    adrp x8, .LCPI9_1
255; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI9_1]
256; CHECK-NEXT:    adrp x8, .LCPI9_2
257; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI9_2]
258; CHECK-NEXT:    neg v1.4s, v1.4s
259; CHECK-NEXT:    adrp x8, .LCPI9_3
260; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
261; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
262; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
263; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI9_3]
264; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
265; CHECK-NEXT:    neg v3.4s, v3.4s
266; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
267; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
268; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
269; CHECK-NEXT:    movi v1.4s, #1
270; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
271; CHECK-NEXT:    ret
272  %urem = urem <4 x i32> %X, <i32 5, i32 14, i32 16, i32 100>
273  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
274  %ret = zext <4 x i1> %cmp to <4 x i32>
275  ret <4 x i32> %ret
276}
277
278;------------------------------------------------------------------------------;
279
280; One one divisor in odd divisor
281define <4 x i32> @test_urem_odd_one(<4 x i32> %X) nounwind {
282; CHECK-LABEL: test_urem_odd_one:
283; CHECK:       // %bb.0:
284; CHECK-NEXT:    adrp x8, .LCPI10_0
285; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI10_0]
286; CHECK-NEXT:    mov w8, #52429
287; CHECK-NEXT:    movk w8, #52428, lsl #16
288; CHECK-NEXT:    dup v2.4s, w8
289; CHECK-NEXT:    mul v0.4s, v0.4s, v2.4s
290; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
291; CHECK-NEXT:    movi v1.4s, #1
292; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
293; CHECK-NEXT:    ret
294  %urem = urem <4 x i32> %X, <i32 5, i32 5, i32 1, i32 5>
295  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
296  %ret = zext <4 x i1> %cmp to <4 x i32>
297  ret <4 x i32> %ret
298}
299
300; One one divisor in even divisor
301define <4 x i32> @test_urem_even_one(<4 x i32> %X) nounwind {
302; CHECK-LABEL: test_urem_even_one:
303; CHECK:       // %bb.0:
304; CHECK-NEXT:    adrp x8, .LCPI11_0
305; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI11_0]
306; CHECK-NEXT:    adrp x8, .LCPI11_1
307; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI11_1]
308; CHECK-NEXT:    adrp x8, .LCPI11_2
309; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI11_2]
310; CHECK-NEXT:    neg v1.4s, v1.4s
311; CHECK-NEXT:    adrp x8, .LCPI11_3
312; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
313; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
314; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
315; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI11_3]
316; CHECK-NEXT:    adrp x8, .LCPI11_4
317; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
318; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI11_4]
319; CHECK-NEXT:    neg v3.4s, v3.4s
320; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
321; CHECK-NEXT:    bit v1.16b, v0.16b, v2.16b
322; CHECK-NEXT:    mls v0.4s, v1.4s, v4.4s
323; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
324; CHECK-NEXT:    movi v1.4s, #1
325; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
326; CHECK-NEXT:    ret
327  %urem = urem <4 x i32> %X, <i32 14, i32 14, i32 1, i32 14>
328  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
329  %ret = zext <4 x i1> %cmp to <4 x i32>
330  ret <4 x i32> %ret
331}
332
333; One one divisor in odd+even divisor
334define <4 x i32> @test_urem_odd_even_one(<4 x i32> %X) nounwind {
335; CHECK-LABEL: test_urem_odd_even_one:
336; CHECK:       // %bb.0:
337; CHECK-NEXT:    adrp x8, .LCPI12_0
338; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI12_0]
339; CHECK-NEXT:    adrp x8, .LCPI12_1
340; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI12_1]
341; CHECK-NEXT:    adrp x8, .LCPI12_2
342; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI12_2]
343; CHECK-NEXT:    neg v1.4s, v1.4s
344; CHECK-NEXT:    adrp x8, .LCPI12_3
345; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
346; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
347; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
348; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI12_3]
349; CHECK-NEXT:    adrp x8, .LCPI12_4
350; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
351; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI12_4]
352; CHECK-NEXT:    neg v3.4s, v3.4s
353; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
354; CHECK-NEXT:    bit v1.16b, v0.16b, v2.16b
355; CHECK-NEXT:    mls v0.4s, v1.4s, v4.4s
356; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
357; CHECK-NEXT:    movi v1.4s, #1
358; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
359; CHECK-NEXT:    ret
360  %urem = urem <4 x i32> %X, <i32 5, i32 14, i32 1, i32 100>
361  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
362  %ret = zext <4 x i1> %cmp to <4 x i32>
363  ret <4 x i32> %ret
364}
365
366;------------------------------------------------------------------------------;
367
368; One INT_MIN divisor in odd divisor
369define <4 x i32> @test_urem_odd_INT_MIN(<4 x i32> %X) nounwind {
370; CHECK-LABEL: test_urem_odd_INT_MIN:
371; CHECK:       // %bb.0:
372; CHECK-NEXT:    adrp x8, .LCPI13_0
373; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI13_0]
374; CHECK-NEXT:    adrp x8, .LCPI13_1
375; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI13_1]
376; CHECK-NEXT:    adrp x8, .LCPI13_2
377; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI13_2]
378; CHECK-NEXT:    umull2 v4.2d, v0.4s, v1.4s
379; CHECK-NEXT:    umull v1.2d, v0.2s, v1.2s
380; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
381; CHECK-NEXT:    neg v2.4s, v2.4s
382; CHECK-NEXT:    ushl v1.4s, v1.4s, v2.4s
383; CHECK-NEXT:    mls v0.4s, v1.4s, v3.4s
384; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
385; CHECK-NEXT:    movi v1.4s, #1
386; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
387; CHECK-NEXT:    ret
388  %urem = urem <4 x i32> %X, <i32 5, i32 5, i32 2147483648, i32 5>
389  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
390  %ret = zext <4 x i1> %cmp to <4 x i32>
391  ret <4 x i32> %ret
392}
393
394; One INT_MIN divisor in even divisor
395define <4 x i32> @test_urem_even_INT_MIN(<4 x i32> %X) nounwind {
396; CHECK-LABEL: test_urem_even_INT_MIN:
397; CHECK:       // %bb.0:
398; CHECK-NEXT:    adrp x8, .LCPI14_0
399; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI14_0]
400; CHECK-NEXT:    adrp x8, .LCPI14_1
401; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI14_1]
402; CHECK-NEXT:    adrp x8, .LCPI14_2
403; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI14_2]
404; CHECK-NEXT:    neg v1.4s, v1.4s
405; CHECK-NEXT:    adrp x8, .LCPI14_3
406; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
407; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
408; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
409; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI14_3]
410; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
411; CHECK-NEXT:    neg v3.4s, v3.4s
412; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
413; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
414; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
415; CHECK-NEXT:    movi v1.4s, #1
416; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
417; CHECK-NEXT:    ret
418  %urem = urem <4 x i32> %X, <i32 14, i32 14, i32 2147483648, i32 14>
419  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
420  %ret = zext <4 x i1> %cmp to <4 x i32>
421  ret <4 x i32> %ret
422}
423
424; One INT_MIN divisor in odd+even divisor
425define <4 x i32> @test_urem_odd_even_INT_MIN(<4 x i32> %X) nounwind {
426; CHECK-LABEL: test_urem_odd_even_INT_MIN:
427; CHECK:       // %bb.0:
428; CHECK-NEXT:    adrp x8, .LCPI15_0
429; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI15_0]
430; CHECK-NEXT:    adrp x8, .LCPI15_1
431; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI15_1]
432; CHECK-NEXT:    adrp x8, .LCPI15_2
433; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI15_2]
434; CHECK-NEXT:    neg v1.4s, v1.4s
435; CHECK-NEXT:    adrp x8, .LCPI15_3
436; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
437; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
438; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
439; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI15_3]
440; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
441; CHECK-NEXT:    neg v3.4s, v3.4s
442; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
443; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
444; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
445; CHECK-NEXT:    movi v1.4s, #1
446; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
447; CHECK-NEXT:    ret
448  %urem = urem <4 x i32> %X, <i32 5, i32 14, i32 2147483648, i32 100>
449  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
450  %ret = zext <4 x i1> %cmp to <4 x i32>
451  ret <4 x i32> %ret
452}
453
454;==============================================================================;
455
456; One all-ones divisor and power-of-two divisor divisor in odd divisor
457define <4 x i32> @test_urem_odd_allones_and_poweroftwo(<4 x i32> %X) nounwind {
458; CHECK-LABEL: test_urem_odd_allones_and_poweroftwo:
459; CHECK:       // %bb.0:
460; CHECK-NEXT:    adrp x8, .LCPI16_0
461; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI16_0]
462; CHECK-NEXT:    adrp x8, .LCPI16_1
463; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI16_1]
464; CHECK-NEXT:    adrp x8, .LCPI16_2
465; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI16_2]
466; CHECK-NEXT:    umull2 v4.2d, v0.4s, v1.4s
467; CHECK-NEXT:    umull v1.2d, v0.2s, v1.2s
468; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
469; CHECK-NEXT:    neg v2.4s, v2.4s
470; CHECK-NEXT:    ushl v1.4s, v1.4s, v2.4s
471; CHECK-NEXT:    mls v0.4s, v1.4s, v3.4s
472; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
473; CHECK-NEXT:    movi v1.4s, #1
474; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
475; CHECK-NEXT:    ret
476  %urem = urem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 5>
477  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
478  %ret = zext <4 x i1> %cmp to <4 x i32>
479  ret <4 x i32> %ret
480}
481
482; One all-ones divisor and power-of-two divisor divisor in even divisor
483define <4 x i32> @test_urem_even_allones_and_poweroftwo(<4 x i32> %X) nounwind {
484; CHECK-LABEL: test_urem_even_allones_and_poweroftwo:
485; CHECK:       // %bb.0:
486; CHECK-NEXT:    adrp x8, .LCPI17_0
487; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI17_0]
488; CHECK-NEXT:    adrp x8, .LCPI17_1
489; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI17_1]
490; CHECK-NEXT:    adrp x8, .LCPI17_2
491; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI17_2]
492; CHECK-NEXT:    neg v1.4s, v1.4s
493; CHECK-NEXT:    adrp x8, .LCPI17_3
494; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
495; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
496; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
497; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI17_3]
498; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
499; CHECK-NEXT:    neg v3.4s, v3.4s
500; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
501; CHECK-NEXT:    mls v0.4s, v1.4s, v2.4s
502; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
503; CHECK-NEXT:    movi v1.4s, #1
504; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
505; CHECK-NEXT:    ret
506  %urem = urem <4 x i32> %X, <i32 14, i32 4294967295, i32 16, i32 14>
507  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
508  %ret = zext <4 x i1> %cmp to <4 x i32>
509  ret <4 x i32> %ret
510}
511
512; One all-ones divisor and power-of-two divisor divisor in odd+even divisor
513define <4 x i32> @test_urem_odd_even_allones_and_poweroftwo(<4 x i32> %X) nounwind {
514; CHECK-LABEL: test_urem_odd_even_allones_and_poweroftwo:
515; CHECK:       // %bb.0:
516; CHECK-NEXT:    adrp x8, .LCPI18_0
517; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI18_0]
518; CHECK-NEXT:    adrp x8, .LCPI18_1
519; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI18_1]
520; CHECK-NEXT:    adrp x8, .LCPI18_2
521; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI18_2]
522; CHECK-NEXT:    umull2 v4.2d, v0.4s, v1.4s
523; CHECK-NEXT:    umull v1.2d, v0.2s, v1.2s
524; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
525; CHECK-NEXT:    neg v2.4s, v2.4s
526; CHECK-NEXT:    ushl v1.4s, v1.4s, v2.4s
527; CHECK-NEXT:    mls v0.4s, v1.4s, v3.4s
528; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
529; CHECK-NEXT:    movi v1.4s, #1
530; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
531; CHECK-NEXT:    ret
532  %urem = urem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 100>
533  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
534  %ret = zext <4 x i1> %cmp to <4 x i32>
535  ret <4 x i32> %ret
536}
537
538;------------------------------------------------------------------------------;
539
540; One all-ones divisor and one one divisor in odd divisor
541define <4 x i32> @test_urem_odd_allones_and_one(<4 x i32> %X) nounwind {
542; CHECK-LABEL: test_urem_odd_allones_and_one:
543; CHECK:       // %bb.0:
544; CHECK-NEXT:    adrp x8, .LCPI19_0
545; CHECK-NEXT:    adrp x9, .LCPI19_1
546; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI19_0]
547; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI19_1]
548; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
549; CHECK-NEXT:    cmhs v0.4s, v2.4s, v0.4s
550; CHECK-NEXT:    movi v1.4s, #1
551; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
552; CHECK-NEXT:    ret
553  %urem = urem <4 x i32> %X, <i32 5, i32 4294967295, i32 1, i32 5>
554  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
555  %ret = zext <4 x i1> %cmp to <4 x i32>
556  ret <4 x i32> %ret
557}
558
559; One all-ones divisor and one one divisor in even divisor
560define <4 x i32> @test_urem_even_allones_and_one(<4 x i32> %X) nounwind {
561; CHECK-LABEL: test_urem_even_allones_and_one:
562; CHECK:       // %bb.0:
563; CHECK-NEXT:    adrp x8, .LCPI20_0
564; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI20_0]
565; CHECK-NEXT:    adrp x8, .LCPI20_1
566; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI20_1]
567; CHECK-NEXT:    adrp x8, .LCPI20_2
568; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI20_2]
569; CHECK-NEXT:    neg v1.4s, v1.4s
570; CHECK-NEXT:    adrp x8, .LCPI20_3
571; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
572; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
573; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
574; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI20_3]
575; CHECK-NEXT:    adrp x8, .LCPI20_4
576; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
577; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI20_4]
578; CHECK-NEXT:    neg v3.4s, v3.4s
579; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
580; CHECK-NEXT:    bit v1.16b, v0.16b, v2.16b
581; CHECK-NEXT:    mls v0.4s, v1.4s, v4.4s
582; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
583; CHECK-NEXT:    movi v1.4s, #1
584; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
585; CHECK-NEXT:    ret
586  %urem = urem <4 x i32> %X, <i32 14, i32 4294967295, i32 1, i32 14>
587  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
588  %ret = zext <4 x i1> %cmp to <4 x i32>
589  ret <4 x i32> %ret
590}
591
592; One all-ones divisor and one one divisor in odd+even divisor
593define <4 x i32> @test_urem_odd_even_allones_and_one(<4 x i32> %X) nounwind {
594; CHECK-LABEL: test_urem_odd_even_allones_and_one:
595; CHECK:       // %bb.0:
596; CHECK-NEXT:    adrp x8, .LCPI21_0
597; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI21_0]
598; CHECK-NEXT:    adrp x8, .LCPI21_1
599; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI21_1]
600; CHECK-NEXT:    adrp x8, .LCPI21_2
601; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI21_2]
602; CHECK-NEXT:    adrp x8, .LCPI21_3
603; CHECK-NEXT:    umull2 v4.2d, v0.4s, v1.4s
604; CHECK-NEXT:    umull v1.2d, v0.2s, v1.2s
605; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
606; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI21_3]
607; CHECK-NEXT:    neg v2.4s, v2.4s
608; CHECK-NEXT:    ushl v1.4s, v1.4s, v2.4s
609; CHECK-NEXT:    bit v1.16b, v0.16b, v3.16b
610; CHECK-NEXT:    mls v0.4s, v1.4s, v4.4s
611; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
612; CHECK-NEXT:    movi v1.4s, #1
613; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
614; CHECK-NEXT:    ret
615  %urem = urem <4 x i32> %X, <i32 5, i32 4294967295, i32 1, i32 100>
616  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
617  %ret = zext <4 x i1> %cmp to <4 x i32>
618  ret <4 x i32> %ret
619}
620
621;------------------------------------------------------------------------------;
622
623; One power-of-two divisor divisor and one divisor in odd divisor
624define <4 x i32> @test_urem_odd_poweroftwo_and_one(<4 x i32> %X) nounwind {
625; CHECK-LABEL: test_urem_odd_poweroftwo_and_one:
626; CHECK:       // %bb.0:
627; CHECK-NEXT:    adrp x8, .LCPI22_0
628; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI22_0]
629; CHECK-NEXT:    adrp x8, .LCPI22_1
630; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI22_1]
631; CHECK-NEXT:    adrp x8, .LCPI22_2
632; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI22_2]
633; CHECK-NEXT:    adrp x8, .LCPI22_3
634; CHECK-NEXT:    umull2 v4.2d, v0.4s, v1.4s
635; CHECK-NEXT:    umull v1.2d, v0.2s, v1.2s
636; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
637; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI22_3]
638; CHECK-NEXT:    neg v2.4s, v2.4s
639; CHECK-NEXT:    ushl v1.4s, v1.4s, v2.4s
640; CHECK-NEXT:    bit v1.16b, v0.16b, v3.16b
641; CHECK-NEXT:    mls v0.4s, v1.4s, v4.4s
642; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
643; CHECK-NEXT:    movi v1.4s, #1
644; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
645; CHECK-NEXT:    ret
646  %urem = urem <4 x i32> %X, <i32 5, i32 16, i32 1, i32 5>
647  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
648  %ret = zext <4 x i1> %cmp to <4 x i32>
649  ret <4 x i32> %ret
650}
651
652; One power-of-two divisor divisor and one divisor in even divisor
653define <4 x i32> @test_urem_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
654; CHECK-LABEL: test_urem_even_poweroftwo_and_one:
655; CHECK:       // %bb.0:
656; CHECK-NEXT:    adrp x8, .LCPI23_0
657; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI23_0]
658; CHECK-NEXT:    adrp x8, .LCPI23_1
659; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI23_1]
660; CHECK-NEXT:    adrp x8, .LCPI23_2
661; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI23_2]
662; CHECK-NEXT:    neg v1.4s, v1.4s
663; CHECK-NEXT:    adrp x8, .LCPI23_3
664; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
665; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
666; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
667; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI23_3]
668; CHECK-NEXT:    adrp x8, .LCPI23_4
669; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
670; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI23_4]
671; CHECK-NEXT:    neg v3.4s, v3.4s
672; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
673; CHECK-NEXT:    bit v1.16b, v0.16b, v2.16b
674; CHECK-NEXT:    mls v0.4s, v1.4s, v4.4s
675; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
676; CHECK-NEXT:    movi v1.4s, #1
677; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
678; CHECK-NEXT:    ret
679  %urem = urem <4 x i32> %X, <i32 14, i32 16, i32 1, i32 14>
680  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
681  %ret = zext <4 x i1> %cmp to <4 x i32>
682  ret <4 x i32> %ret
683}
684
685; One power-of-two divisor divisor and one divisor in odd+even divisor
686define <4 x i32> @test_urem_odd_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
687; CHECK-LABEL: test_urem_odd_even_poweroftwo_and_one:
688; CHECK:       // %bb.0:
689; CHECK-NEXT:    adrp x8, .LCPI24_0
690; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI24_0]
691; CHECK-NEXT:    adrp x8, .LCPI24_1
692; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI24_1]
693; CHECK-NEXT:    adrp x8, .LCPI24_2
694; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI24_2]
695; CHECK-NEXT:    adrp x8, .LCPI24_3
696; CHECK-NEXT:    umull2 v4.2d, v0.4s, v1.4s
697; CHECK-NEXT:    umull v1.2d, v0.2s, v1.2s
698; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
699; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI24_3]
700; CHECK-NEXT:    neg v2.4s, v2.4s
701; CHECK-NEXT:    ushl v1.4s, v1.4s, v2.4s
702; CHECK-NEXT:    bit v1.16b, v0.16b, v3.16b
703; CHECK-NEXT:    mls v0.4s, v1.4s, v4.4s
704; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
705; CHECK-NEXT:    movi v1.4s, #1
706; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
707; CHECK-NEXT:    ret
708  %urem = urem <4 x i32> %X, <i32 5, i32 16, i32 1, i32 100>
709  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
710  %ret = zext <4 x i1> %cmp to <4 x i32>
711  ret <4 x i32> %ret
712}
713
714;------------------------------------------------------------------------------;
715
716define <4 x i32> @test_urem_odd_allones_and_poweroftwo_and_one(<4 x i32> %X) nounwind {
717; CHECK-LABEL: test_urem_odd_allones_and_poweroftwo_and_one:
718; CHECK:       // %bb.0:
719; CHECK-NEXT:    adrp x8, .LCPI25_0
720; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI25_0]
721; CHECK-NEXT:    adrp x8, .LCPI25_1
722; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI25_1]
723; CHECK-NEXT:    adrp x8, .LCPI25_2
724; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI25_2]
725; CHECK-NEXT:    adrp x8, .LCPI25_3
726; CHECK-NEXT:    umull2 v4.2d, v0.4s, v1.4s
727; CHECK-NEXT:    umull v1.2d, v0.2s, v1.2s
728; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
729; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI25_3]
730; CHECK-NEXT:    neg v2.4s, v2.4s
731; CHECK-NEXT:    ushl v1.4s, v1.4s, v2.4s
732; CHECK-NEXT:    bit v1.16b, v0.16b, v3.16b
733; CHECK-NEXT:    mls v0.4s, v1.4s, v4.4s
734; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
735; CHECK-NEXT:    movi v1.4s, #1
736; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
737; CHECK-NEXT:    ret
738  %urem = urem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 1>
739  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
740  %ret = zext <4 x i1> %cmp to <4 x i32>
741  ret <4 x i32> %ret
742}
743
744define <4 x i32> @test_urem_even_allones_and_poweroftwo_and_one(<4 x i32> %X) nounwind {
745; CHECK-LABEL: test_urem_even_allones_and_poweroftwo_and_one:
746; CHECK:       // %bb.0:
747; CHECK-NEXT:    adrp x8, .LCPI26_0
748; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI26_0]
749; CHECK-NEXT:    adrp x8, .LCPI26_1
750; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI26_1]
751; CHECK-NEXT:    adrp x8, .LCPI26_2
752; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI26_2]
753; CHECK-NEXT:    neg v1.4s, v1.4s
754; CHECK-NEXT:    adrp x8, .LCPI26_3
755; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
756; CHECK-NEXT:    umull2 v4.2d, v1.4s, v2.4s
757; CHECK-NEXT:    umull v1.2d, v1.2s, v2.2s
758; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI26_3]
759; CHECK-NEXT:    adrp x8, .LCPI26_4
760; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v4.4s
761; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI26_4]
762; CHECK-NEXT:    neg v3.4s, v3.4s
763; CHECK-NEXT:    ushl v1.4s, v1.4s, v3.4s
764; CHECK-NEXT:    bit v1.16b, v0.16b, v2.16b
765; CHECK-NEXT:    mls v0.4s, v1.4s, v4.4s
766; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
767; CHECK-NEXT:    movi v1.4s, #1
768; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
769; CHECK-NEXT:    ret
770  %urem = urem <4 x i32> %X, <i32 14, i32 4294967295, i32 16, i32 1>
771  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
772  %ret = zext <4 x i1> %cmp to <4 x i32>
773  ret <4 x i32> %ret
774}
775