1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK 3 4declare {<1 x i32>, <1 x i1>} @llvm.umul.with.overflow.v1i32(<1 x i32>, <1 x i32>) 5declare {<2 x i32>, <2 x i1>} @llvm.umul.with.overflow.v2i32(<2 x i32>, <2 x i32>) 6declare {<3 x i32>, <3 x i1>} @llvm.umul.with.overflow.v3i32(<3 x i32>, <3 x i32>) 7declare {<4 x i32>, <4 x i1>} @llvm.umul.with.overflow.v4i32(<4 x i32>, <4 x i32>) 8declare {<6 x i32>, <6 x i1>} @llvm.umul.with.overflow.v6i32(<6 x i32>, <6 x i32>) 9declare {<8 x i32>, <8 x i1>} @llvm.umul.with.overflow.v8i32(<8 x i32>, <8 x i32>) 10 11declare {<16 x i8>, <16 x i1>} @llvm.umul.with.overflow.v16i8(<16 x i8>, <16 x i8>) 12declare {<8 x i16>, <8 x i1>} @llvm.umul.with.overflow.v8i16(<8 x i16>, <8 x i16>) 13declare {<2 x i64>, <2 x i1>} @llvm.umul.with.overflow.v2i64(<2 x i64>, <2 x i64>) 14 15declare {<4 x i24>, <4 x i1>} @llvm.umul.with.overflow.v4i24(<4 x i24>, <4 x i24>) 16declare {<4 x i1>, <4 x i1>} @llvm.umul.with.overflow.v4i1(<4 x i1>, <4 x i1>) 17declare {<2 x i128>, <2 x i1>} @llvm.umul.with.overflow.v2i128(<2 x i128>, <2 x i128>) 18 19define <1 x i32> @umulo_v1i32(<1 x i32> %a0, <1 x i32> %a1, <1 x i32>* %p2) nounwind { 20; CHECK-LABEL: umulo_v1i32: 21; CHECK: // %bb.0: 22; CHECK-NEXT: umull v1.2d, v0.2s, v1.2s 23; CHECK-NEXT: shrn v0.2s, v1.2d, #32 24; CHECK-NEXT: cmeq v0.2s, v0.2s, #0 25; CHECK-NEXT: mvn v0.8b, v0.8b 26; CHECK-NEXT: xtn v1.2s, v1.2d 27; CHECK-NEXT: str s1, [x0] 28; CHECK-NEXT: ret 29 %t = call {<1 x i32>, <1 x i1>} @llvm.umul.with.overflow.v1i32(<1 x i32> %a0, <1 x i32> %a1) 30 %val = extractvalue {<1 x i32>, <1 x i1>} %t, 0 31 %obit = extractvalue {<1 x i32>, <1 x i1>} %t, 1 32 %res = sext <1 x i1> %obit to <1 x i32> 33 store <1 x i32> %val, <1 x i32>* %p2 34 ret <1 x i32> %res 35} 36 37define <2 x i32> @umulo_v2i32(<2 x i32> %a0, <2 x i32> %a1, <2 x i32>* %p2) nounwind { 38; CHECK-LABEL: umulo_v2i32: 39; CHECK: // %bb.0: 40; CHECK-NEXT: umull v1.2d, v0.2s, v1.2s 41; CHECK-NEXT: shrn v0.2s, v1.2d, #32 42; CHECK-NEXT: cmeq v0.2s, v0.2s, #0 43; CHECK-NEXT: mvn v0.8b, v0.8b 44; CHECK-NEXT: xtn v1.2s, v1.2d 45; CHECK-NEXT: str d1, [x0] 46; CHECK-NEXT: ret 47 %t = call {<2 x i32>, <2 x i1>} @llvm.umul.with.overflow.v2i32(<2 x i32> %a0, <2 x i32> %a1) 48 %val = extractvalue {<2 x i32>, <2 x i1>} %t, 0 49 %obit = extractvalue {<2 x i32>, <2 x i1>} %t, 1 50 %res = sext <2 x i1> %obit to <2 x i32> 51 store <2 x i32> %val, <2 x i32>* %p2 52 ret <2 x i32> %res 53} 54 55define <3 x i32> @umulo_v3i32(<3 x i32> %a0, <3 x i32> %a1, <3 x i32>* %p2) nounwind { 56; CHECK-LABEL: umulo_v3i32: 57; CHECK: // %bb.0: 58; CHECK-NEXT: umull2 v2.2d, v0.4s, v1.4s 59; CHECK-NEXT: umull v3.2d, v0.2s, v1.2s 60; CHECK-NEXT: mul v1.4s, v0.4s, v1.4s 61; CHECK-NEXT: uzp2 v0.4s, v3.4s, v2.4s 62; CHECK-NEXT: cmeq v0.4s, v0.4s, #0 63; CHECK-NEXT: add x8, x0, #8 // =8 64; CHECK-NEXT: mvn v0.16b, v0.16b 65; CHECK-NEXT: st1 { v1.s }[2], [x8] 66; CHECK-NEXT: str d1, [x0] 67; CHECK-NEXT: ret 68 %t = call {<3 x i32>, <3 x i1>} @llvm.umul.with.overflow.v3i32(<3 x i32> %a0, <3 x i32> %a1) 69 %val = extractvalue {<3 x i32>, <3 x i1>} %t, 0 70 %obit = extractvalue {<3 x i32>, <3 x i1>} %t, 1 71 %res = sext <3 x i1> %obit to <3 x i32> 72 store <3 x i32> %val, <3 x i32>* %p2 73 ret <3 x i32> %res 74} 75 76define <4 x i32> @umulo_v4i32(<4 x i32> %a0, <4 x i32> %a1, <4 x i32>* %p2) nounwind { 77; CHECK-LABEL: umulo_v4i32: 78; CHECK: // %bb.0: 79; CHECK-NEXT: umull2 v2.2d, v0.4s, v1.4s 80; CHECK-NEXT: umull v3.2d, v0.2s, v1.2s 81; CHECK-NEXT: uzp2 v2.4s, v3.4s, v2.4s 82; CHECK-NEXT: cmeq v2.4s, v2.4s, #0 83; CHECK-NEXT: mvn v2.16b, v2.16b 84; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s 85; CHECK-NEXT: str q0, [x0] 86; CHECK-NEXT: mov v0.16b, v2.16b 87; CHECK-NEXT: ret 88 %t = call {<4 x i32>, <4 x i1>} @llvm.umul.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> %a1) 89 %val = extractvalue {<4 x i32>, <4 x i1>} %t, 0 90 %obit = extractvalue {<4 x i32>, <4 x i1>} %t, 1 91 %res = sext <4 x i1> %obit to <4 x i32> 92 store <4 x i32> %val, <4 x i32>* %p2 93 ret <4 x i32> %res 94} 95 96define <6 x i32> @umulo_v6i32(<6 x i32> %a0, <6 x i32> %a1, <6 x i32>* %p2) nounwind { 97; CHECK-LABEL: umulo_v6i32: 98; CHECK: // %bb.0: 99; CHECK-NEXT: fmov s2, w6 100; CHECK-NEXT: ldr s0, [sp, #16] 101; CHECK-NEXT: mov x9, sp 102; CHECK-NEXT: mov v2.s[1], w7 103; CHECK-NEXT: ld1 { v2.s }[2], [x9] 104; CHECK-NEXT: add x8, sp, #24 // =24 105; CHECK-NEXT: add x10, sp, #8 // =8 106; CHECK-NEXT: ld1 { v0.s }[1], [x8] 107; CHECK-NEXT: fmov s3, w0 108; CHECK-NEXT: ldr x11, [sp, #32] 109; CHECK-NEXT: ld1 { v2.s }[3], [x10] 110; CHECK-NEXT: fmov s1, w4 111; CHECK-NEXT: mov v3.s[1], w1 112; CHECK-NEXT: mov v1.s[1], w5 113; CHECK-NEXT: mov v3.s[2], w2 114; CHECK-NEXT: mov v3.s[3], w3 115; CHECK-NEXT: umull2 v4.2d, v1.4s, v0.4s 116; CHECK-NEXT: umull v5.2d, v1.2s, v0.2s 117; CHECK-NEXT: mul v0.4s, v1.4s, v0.4s 118; CHECK-NEXT: uzp2 v1.4s, v5.4s, v4.4s 119; CHECK-NEXT: str d0, [x11, #16] 120; CHECK-NEXT: umull2 v0.2d, v3.4s, v2.4s 121; CHECK-NEXT: umull v4.2d, v3.2s, v2.2s 122; CHECK-NEXT: uzp2 v0.4s, v4.4s, v0.4s 123; CHECK-NEXT: cmeq v1.4s, v1.4s, #0 124; CHECK-NEXT: cmeq v0.4s, v0.4s, #0 125; CHECK-NEXT: mvn v1.16b, v1.16b 126; CHECK-NEXT: mvn v0.16b, v0.16b 127; CHECK-NEXT: mul v2.4s, v3.4s, v2.4s 128; CHECK-NEXT: mov w5, v1.s[1] 129; CHECK-NEXT: mov w1, v0.s[1] 130; CHECK-NEXT: mov w2, v0.s[2] 131; CHECK-NEXT: mov w3, v0.s[3] 132; CHECK-NEXT: fmov w4, s1 133; CHECK-NEXT: fmov w0, s0 134; CHECK-NEXT: str q2, [x11] 135; CHECK-NEXT: ret 136 %t = call {<6 x i32>, <6 x i1>} @llvm.umul.with.overflow.v6i32(<6 x i32> %a0, <6 x i32> %a1) 137 %val = extractvalue {<6 x i32>, <6 x i1>} %t, 0 138 %obit = extractvalue {<6 x i32>, <6 x i1>} %t, 1 139 %res = sext <6 x i1> %obit to <6 x i32> 140 store <6 x i32> %val, <6 x i32>* %p2 141 ret <6 x i32> %res 142} 143 144define <8 x i32> @umulo_v8i32(<8 x i32> %a0, <8 x i32> %a1, <8 x i32>* %p2) nounwind { 145; CHECK-LABEL: umulo_v8i32: 146; CHECK: // %bb.0: 147; CHECK-NEXT: umull2 v4.2d, v0.4s, v2.4s 148; CHECK-NEXT: umull v5.2d, v0.2s, v2.2s 149; CHECK-NEXT: umull2 v6.2d, v1.4s, v3.4s 150; CHECK-NEXT: mul v2.4s, v0.4s, v2.4s 151; CHECK-NEXT: umull v0.2d, v1.2s, v3.2s 152; CHECK-NEXT: mul v3.4s, v1.4s, v3.4s 153; CHECK-NEXT: uzp2 v1.4s, v5.4s, v4.4s 154; CHECK-NEXT: uzp2 v0.4s, v0.4s, v6.4s 155; CHECK-NEXT: cmeq v1.4s, v1.4s, #0 156; CHECK-NEXT: cmeq v4.4s, v0.4s, #0 157; CHECK-NEXT: mvn v0.16b, v1.16b 158; CHECK-NEXT: mvn v1.16b, v4.16b 159; CHECK-NEXT: stp q2, q3, [x0] 160; CHECK-NEXT: ret 161 %t = call {<8 x i32>, <8 x i1>} @llvm.umul.with.overflow.v8i32(<8 x i32> %a0, <8 x i32> %a1) 162 %val = extractvalue {<8 x i32>, <8 x i1>} %t, 0 163 %obit = extractvalue {<8 x i32>, <8 x i1>} %t, 1 164 %res = sext <8 x i1> %obit to <8 x i32> 165 store <8 x i32> %val, <8 x i32>* %p2 166 ret <8 x i32> %res 167} 168 169define <16 x i32> @umulo_v16i8(<16 x i8> %a0, <16 x i8> %a1, <16 x i8>* %p2) nounwind { 170; CHECK-LABEL: umulo_v16i8: 171; CHECK: // %bb.0: 172; CHECK-NEXT: umull2 v2.8h, v0.16b, v1.16b 173; CHECK-NEXT: umull v3.8h, v0.8b, v1.8b 174; CHECK-NEXT: mul v4.16b, v0.16b, v1.16b 175; CHECK-NEXT: uzp2 v0.16b, v3.16b, v2.16b 176; CHECK-NEXT: cmeq v0.16b, v0.16b, #0 177; CHECK-NEXT: mvn v0.16b, v0.16b 178; CHECK-NEXT: zip1 v1.8b, v0.8b, v0.8b 179; CHECK-NEXT: zip2 v2.8b, v0.8b, v0.8b 180; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 181; CHECK-NEXT: ushll v1.4s, v1.4h, #0 182; CHECK-NEXT: ushll v2.4s, v2.4h, #0 183; CHECK-NEXT: zip1 v3.8b, v0.8b, v0.8b 184; CHECK-NEXT: zip2 v0.8b, v0.8b, v0.8b 185; CHECK-NEXT: shl v1.4s, v1.4s, #31 186; CHECK-NEXT: shl v2.4s, v2.4s, #31 187; CHECK-NEXT: ushll v3.4s, v3.4h, #0 188; CHECK-NEXT: ushll v5.4s, v0.4h, #0 189; CHECK-NEXT: sshr v0.4s, v1.4s, #31 190; CHECK-NEXT: sshr v1.4s, v2.4s, #31 191; CHECK-NEXT: shl v2.4s, v3.4s, #31 192; CHECK-NEXT: shl v3.4s, v5.4s, #31 193; CHECK-NEXT: sshr v2.4s, v2.4s, #31 194; CHECK-NEXT: sshr v3.4s, v3.4s, #31 195; CHECK-NEXT: str q4, [x0] 196; CHECK-NEXT: ret 197 %t = call {<16 x i8>, <16 x i1>} @llvm.umul.with.overflow.v16i8(<16 x i8> %a0, <16 x i8> %a1) 198 %val = extractvalue {<16 x i8>, <16 x i1>} %t, 0 199 %obit = extractvalue {<16 x i8>, <16 x i1>} %t, 1 200 %res = sext <16 x i1> %obit to <16 x i32> 201 store <16 x i8> %val, <16 x i8>* %p2 202 ret <16 x i32> %res 203} 204 205define <8 x i32> @umulo_v8i16(<8 x i16> %a0, <8 x i16> %a1, <8 x i16>* %p2) nounwind { 206; CHECK-LABEL: umulo_v8i16: 207; CHECK: // %bb.0: 208; CHECK-NEXT: umull2 v2.4s, v0.8h, v1.8h 209; CHECK-NEXT: umull v3.4s, v0.4h, v1.4h 210; CHECK-NEXT: mul v4.8h, v0.8h, v1.8h 211; CHECK-NEXT: uzp2 v0.8h, v3.8h, v2.8h 212; CHECK-NEXT: cmeq v0.8h, v0.8h, #0 213; CHECK-NEXT: mvn v0.16b, v0.16b 214; CHECK-NEXT: xtn v0.8b, v0.8h 215; CHECK-NEXT: zip1 v1.8b, v0.8b, v0.8b 216; CHECK-NEXT: zip2 v0.8b, v0.8b, v0.8b 217; CHECK-NEXT: ushll v1.4s, v1.4h, #0 218; CHECK-NEXT: ushll v0.4s, v0.4h, #0 219; CHECK-NEXT: shl v1.4s, v1.4s, #31 220; CHECK-NEXT: shl v2.4s, v0.4s, #31 221; CHECK-NEXT: sshr v0.4s, v1.4s, #31 222; CHECK-NEXT: sshr v1.4s, v2.4s, #31 223; CHECK-NEXT: str q4, [x0] 224; CHECK-NEXT: ret 225 %t = call {<8 x i16>, <8 x i1>} @llvm.umul.with.overflow.v8i16(<8 x i16> %a0, <8 x i16> %a1) 226 %val = extractvalue {<8 x i16>, <8 x i1>} %t, 0 227 %obit = extractvalue {<8 x i16>, <8 x i1>} %t, 1 228 %res = sext <8 x i1> %obit to <8 x i32> 229 store <8 x i16> %val, <8 x i16>* %p2 230 ret <8 x i32> %res 231} 232 233define <2 x i32> @umulo_v2i64(<2 x i64> %a0, <2 x i64> %a1, <2 x i64>* %p2) nounwind { 234; CHECK-LABEL: umulo_v2i64: 235; CHECK: // %bb.0: 236; CHECK-NEXT: mov x8, v1.d[1] 237; CHECK-NEXT: fmov x9, d1 238; CHECK-NEXT: mov x10, v0.d[1] 239; CHECK-NEXT: fmov x11, d0 240; CHECK-NEXT: umulh x12, x11, x9 241; CHECK-NEXT: mul x9, x11, x9 242; CHECK-NEXT: umulh x11, x10, x8 243; CHECK-NEXT: cmp xzr, x11 244; CHECK-NEXT: csetm x11, ne 245; CHECK-NEXT: cmp xzr, x12 246; CHECK-NEXT: csetm x12, ne 247; CHECK-NEXT: fmov d0, x12 248; CHECK-NEXT: mul x8, x10, x8 249; CHECK-NEXT: fmov d1, x9 250; CHECK-NEXT: mov v0.d[1], x11 251; CHECK-NEXT: xtn v0.2s, v0.2d 252; CHECK-NEXT: mov v1.d[1], x8 253; CHECK-NEXT: str q1, [x0] 254; CHECK-NEXT: ret 255 %t = call {<2 x i64>, <2 x i1>} @llvm.umul.with.overflow.v2i64(<2 x i64> %a0, <2 x i64> %a1) 256 %val = extractvalue {<2 x i64>, <2 x i1>} %t, 0 257 %obit = extractvalue {<2 x i64>, <2 x i1>} %t, 1 258 %res = sext <2 x i1> %obit to <2 x i32> 259 store <2 x i64> %val, <2 x i64>* %p2 260 ret <2 x i32> %res 261} 262 263define <4 x i32> @umulo_v4i24(<4 x i24> %a0, <4 x i24> %a1, <4 x i24>* %p2) nounwind { 264; CHECK-LABEL: umulo_v4i24: 265; CHECK: // %bb.0: 266; CHECK-NEXT: bic v1.4s, #255, lsl #24 267; CHECK-NEXT: bic v0.4s, #255, lsl #24 268; CHECK-NEXT: umull2 v2.2d, v0.4s, v1.4s 269; CHECK-NEXT: umull v3.2d, v0.2s, v1.2s 270; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s 271; CHECK-NEXT: uzp2 v1.4s, v3.4s, v2.4s 272; CHECK-NEXT: ushr v2.4s, v0.4s, #24 273; CHECK-NEXT: mov w8, v0.s[3] 274; CHECK-NEXT: mov w9, v0.s[2] 275; CHECK-NEXT: mov w10, v0.s[1] 276; CHECK-NEXT: fmov w11, s0 277; CHECK-NEXT: cmeq v0.4s, v1.4s, #0 278; CHECK-NEXT: cmeq v1.4s, v2.4s, #0 279; CHECK-NEXT: sturh w8, [x0, #9] 280; CHECK-NEXT: lsr w8, w8, #16 281; CHECK-NEXT: mvn v0.16b, v0.16b 282; CHECK-NEXT: mvn v1.16b, v1.16b 283; CHECK-NEXT: strh w9, [x0, #6] 284; CHECK-NEXT: sturh w10, [x0, #3] 285; CHECK-NEXT: lsr w9, w9, #16 286; CHECK-NEXT: lsr w10, w10, #16 287; CHECK-NEXT: strb w8, [x0, #11] 288; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b 289; CHECK-NEXT: lsr w8, w11, #16 290; CHECK-NEXT: strh w11, [x0] 291; CHECK-NEXT: strb w9, [x0, #8] 292; CHECK-NEXT: strb w10, [x0, #5] 293; CHECK-NEXT: strb w8, [x0, #2] 294; CHECK-NEXT: ret 295 %t = call {<4 x i24>, <4 x i1>} @llvm.umul.with.overflow.v4i24(<4 x i24> %a0, <4 x i24> %a1) 296 %val = extractvalue {<4 x i24>, <4 x i1>} %t, 0 297 %obit = extractvalue {<4 x i24>, <4 x i1>} %t, 1 298 %res = sext <4 x i1> %obit to <4 x i32> 299 store <4 x i24> %val, <4 x i24>* %p2 300 ret <4 x i32> %res 301} 302 303define <4 x i32> @umulo_v4i1(<4 x i1> %a0, <4 x i1> %a1, <4 x i1>* %p2) nounwind { 304; CHECK-LABEL: umulo_v4i1: 305; CHECK: // %bb.0: 306; CHECK-NEXT: movi v2.4h, #1 307; CHECK-NEXT: and v1.8b, v1.8b, v2.8b 308; CHECK-NEXT: and v0.8b, v0.8b, v2.8b 309; CHECK-NEXT: umull v0.4s, v0.4h, v1.4h 310; CHECK-NEXT: shrn v1.4h, v0.4s, #16 311; CHECK-NEXT: xtn v0.4h, v0.4s 312; CHECK-NEXT: umov w9, v0.h[1] 313; CHECK-NEXT: umov w8, v0.h[0] 314; CHECK-NEXT: and w9, w9, #0x1 315; CHECK-NEXT: bfi w8, w9, #1, #1 316; CHECK-NEXT: umov w9, v0.h[2] 317; CHECK-NEXT: cmeq v1.4h, v1.4h, #0 318; CHECK-NEXT: ushr v2.4h, v0.4h, #1 319; CHECK-NEXT: and w9, w9, #0x1 320; CHECK-NEXT: bfi w8, w9, #2, #1 321; CHECK-NEXT: umov w9, v0.h[3] 322; CHECK-NEXT: mvn v0.8b, v1.8b 323; CHECK-NEXT: cmeq v1.4h, v2.4h, #0 324; CHECK-NEXT: mvn v1.8b, v1.8b 325; CHECK-NEXT: orr v0.8b, v1.8b, v0.8b 326; CHECK-NEXT: bfi w8, w9, #3, #29 327; CHECK-NEXT: sshll v0.4s, v0.4h, #0 328; CHECK-NEXT: and w8, w8, #0xf 329; CHECK-NEXT: strb w8, [x0] 330; CHECK-NEXT: ret 331 %t = call {<4 x i1>, <4 x i1>} @llvm.umul.with.overflow.v4i1(<4 x i1> %a0, <4 x i1> %a1) 332 %val = extractvalue {<4 x i1>, <4 x i1>} %t, 0 333 %obit = extractvalue {<4 x i1>, <4 x i1>} %t, 1 334 %res = sext <4 x i1> %obit to <4 x i32> 335 store <4 x i1> %val, <4 x i1>* %p2 336 ret <4 x i32> %res 337} 338 339define <2 x i32> @umulo_v2i128(<2 x i128> %a0, <2 x i128> %a1, <2 x i128>* %p2) nounwind { 340; CHECK-LABEL: umulo_v2i128: 341; CHECK: // %bb.0: 342; CHECK-NEXT: mul x9, x7, x2 343; CHECK-NEXT: umulh x10, x2, x6 344; CHECK-NEXT: madd x9, x3, x6, x9 345; CHECK-NEXT: add x15, x10, x9 346; CHECK-NEXT: cmp x15, x10 347; CHECK-NEXT: cset w10, lo 348; CHECK-NEXT: cmp x9, #0 // =0 349; CHECK-NEXT: csel w10, wzr, w10, eq 350; CHECK-NEXT: cmp x7, #0 // =0 351; CHECK-NEXT: umulh x11, x3, x6 352; CHECK-NEXT: mul x13, x5, x0 353; CHECK-NEXT: cset w17, ne 354; CHECK-NEXT: cmp x3, #0 // =0 355; CHECK-NEXT: umulh x12, x7, x2 356; CHECK-NEXT: umulh x9, x0, x4 357; CHECK-NEXT: madd x13, x1, x4, x13 358; CHECK-NEXT: cset w18, ne 359; CHECK-NEXT: cmp xzr, x11 360; CHECK-NEXT: ldr x8, [sp] 361; CHECK-NEXT: add x11, x9, x13 362; CHECK-NEXT: and w17, w18, w17 363; CHECK-NEXT: cset w18, ne 364; CHECK-NEXT: cmp xzr, x12 365; CHECK-NEXT: orr w12, w17, w18 366; CHECK-NEXT: cset w17, ne 367; CHECK-NEXT: cmp x11, x9 368; CHECK-NEXT: orr w9, w12, w17 369; CHECK-NEXT: cset w12, lo 370; CHECK-NEXT: cmp x13, #0 // =0 371; CHECK-NEXT: mul x14, x2, x6 372; CHECK-NEXT: csel w12, wzr, w12, eq 373; CHECK-NEXT: cmp x5, #0 // =0 374; CHECK-NEXT: stp x14, x15, [x8, #16] 375; CHECK-NEXT: umulh x14, x1, x4 376; CHECK-NEXT: cset w13, ne 377; CHECK-NEXT: cmp x1, #0 // =0 378; CHECK-NEXT: umulh x16, x5, x0 379; CHECK-NEXT: cset w17, ne 380; CHECK-NEXT: cmp xzr, x14 381; CHECK-NEXT: and w13, w17, w13 382; CHECK-NEXT: cset w14, ne 383; CHECK-NEXT: cmp xzr, x16 384; CHECK-NEXT: orr w13, w13, w14 385; CHECK-NEXT: cset w14, ne 386; CHECK-NEXT: orr w13, w13, w14 387; CHECK-NEXT: orr w12, w13, w12 388; CHECK-NEXT: orr w9, w9, w10 389; CHECK-NEXT: fmov s0, w12 390; CHECK-NEXT: mov v0.s[1], w9 391; CHECK-NEXT: shl v0.2s, v0.2s, #31 392; CHECK-NEXT: mul x15, x0, x4 393; CHECK-NEXT: sshr v0.2s, v0.2s, #31 394; CHECK-NEXT: stp x15, x11, [x8] 395; CHECK-NEXT: ret 396 %t = call {<2 x i128>, <2 x i1>} @llvm.umul.with.overflow.v2i128(<2 x i128> %a0, <2 x i128> %a1) 397 %val = extractvalue {<2 x i128>, <2 x i1>} %t, 0 398 %obit = extractvalue {<2 x i128>, <2 x i1>} %t, 1 399 %res = sext <2 x i1> %obit to <2 x i32> 400 store <2 x i128> %val, <2 x i128>* %p2 401 ret <2 x i32> %res 402} 403