1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
3
4; Same as vecreduce-fadd-legalization.ll, but without fmf.
5
6declare half @llvm.experimental.vector.reduce.v2.fadd.f16.v1f16(half, <1 x half>)
7declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v1f32(float, <1 x float>)
8declare double @llvm.experimental.vector.reduce.v2.fadd.f64.v1f64(double, <1 x double>)
9declare fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v1f128(fp128, <1 x fp128>)
10
11declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v3f32(float, <3 x float>)
12declare fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v2f128(fp128, <2 x fp128>)
13declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v16f32(float, <16 x float>)
14
15define half @test_v1f16(<1 x half> %a) nounwind {
16; CHECK-LABEL: test_v1f16:
17; CHECK:       // %bb.0:
18; CHECK-NEXT:    fcvt s0, h0
19; CHECK-NEXT:    fmov s1, wzr
20; CHECK-NEXT:    fadd s0, s0, s1
21; CHECK-NEXT:    fcvt h0, s0
22; CHECK-NEXT:    ret
23  %b = call half @llvm.experimental.vector.reduce.v2.fadd.f16.v1f16(half 0.0, <1 x half> %a)
24  ret half %b
25}
26
27define float @test_v1f32(<1 x float> %a) nounwind {
28; CHECK-LABEL: test_v1f32:
29; CHECK:       // %bb.0:
30; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
31; CHECK-NEXT:    fmov s1, wzr
32; CHECK-NEXT:    fadd s0, s0, s1
33; CHECK-NEXT:    ret
34  %b = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v1f32(float 0.0, <1 x float> %a)
35  ret float %b
36}
37
38define double @test_v1f64(<1 x double> %a) nounwind {
39; CHECK-LABEL: test_v1f64:
40; CHECK:       // %bb.0:
41; CHECK-NEXT:    fmov d1, xzr
42; CHECK-NEXT:    fadd d0, d0, d1
43; CHECK-NEXT:    ret
44  %b = call double @llvm.experimental.vector.reduce.v2.fadd.f64.v1f64(double 0.0, <1 x double> %a)
45  ret double %b
46}
47
48define fp128 @test_v1f128(<1 x fp128> %a) nounwind {
49; CHECK-LABEL: test_v1f128:
50; CHECK:       // %bb.0:
51; CHECK-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
52; CHECK-NEXT:    adrp x8, .LCPI3_0
53; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI3_0]
54; CHECK-NEXT:    bl __addtf3
55; CHECK-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
56; CHECK-NEXT:    ret
57  %b = call fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v1f128(fp128 zeroinitializer, <1 x fp128> %a)
58  ret fp128 %b
59}
60
61define float @test_v3f32(<3 x float> %a) nounwind {
62; CHECK-LABEL: test_v3f32:
63; CHECK:       // %bb.0:
64; CHECK-NEXT:    fmov s1, wzr
65; CHECK-NEXT:    mov s2, v0.s[1]
66; CHECK-NEXT:    fadd s1, s0, s1
67; CHECK-NEXT:    fadd s1, s1, s2
68; CHECK-NEXT:    mov s0, v0.s[2]
69; CHECK-NEXT:    fadd s0, s1, s0
70; CHECK-NEXT:    ret
71  %b = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v3f32(float 0.0, <3 x float> %a)
72  ret float %b
73}
74
75define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
76; CHECK-LABEL: test_v2f128:
77; CHECK:       // %bb.0:
78; CHECK-NEXT:    sub sp, sp, #32 // =32
79; CHECK-NEXT:    adrp x8, .LCPI5_0
80; CHECK-NEXT:    str q1, [sp] // 16-byte Folded Spill
81; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI5_0]
82; CHECK-NEXT:    str x30, [sp, #16] // 8-byte Folded Spill
83; CHECK-NEXT:    bl __addtf3
84; CHECK-NEXT:    ldr q1, [sp] // 16-byte Folded Reload
85; CHECK-NEXT:    bl __addtf3
86; CHECK-NEXT:    ldr x30, [sp, #16] // 8-byte Folded Reload
87; CHECK-NEXT:    add sp, sp, #32 // =32
88; CHECK-NEXT:    ret
89  %b = call fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v2f128(fp128 zeroinitializer, <2 x fp128> %a)
90  ret fp128 %b
91}
92
93define float @test_v16f32(<16 x float> %a) nounwind {
94; CHECK-LABEL: test_v16f32:
95; CHECK:       // %bb.0:
96; CHECK-NEXT:    fmov s4, wzr
97; CHECK-NEXT:    mov s5, v0.s[1]
98; CHECK-NEXT:    fadd s4, s0, s4
99; CHECK-NEXT:    fadd s4, s4, s5
100; CHECK-NEXT:    mov s5, v0.s[2]
101; CHECK-NEXT:    mov s0, v0.s[3]
102; CHECK-NEXT:    fadd s4, s4, s5
103; CHECK-NEXT:    fadd s0, s4, s0
104; CHECK-NEXT:    mov s5, v1.s[1]
105; CHECK-NEXT:    fadd s0, s0, s1
106; CHECK-NEXT:    mov s4, v1.s[2]
107; CHECK-NEXT:    fadd s0, s0, s5
108; CHECK-NEXT:    mov s1, v1.s[3]
109; CHECK-NEXT:    fadd s0, s0, s4
110; CHECK-NEXT:    fadd s0, s0, s1
111; CHECK-NEXT:    mov s5, v2.s[1]
112; CHECK-NEXT:    fadd s0, s0, s2
113; CHECK-NEXT:    mov s4, v2.s[2]
114; CHECK-NEXT:    fadd s0, s0, s5
115; CHECK-NEXT:    mov s1, v2.s[3]
116; CHECK-NEXT:    fadd s0, s0, s4
117; CHECK-NEXT:    fadd s0, s0, s1
118; CHECK-NEXT:    mov s2, v3.s[1]
119; CHECK-NEXT:    fadd s0, s0, s3
120; CHECK-NEXT:    mov s5, v3.s[2]
121; CHECK-NEXT:    fadd s0, s0, s2
122; CHECK-NEXT:    fadd s0, s0, s5
123; CHECK-NEXT:    mov s1, v3.s[3]
124; CHECK-NEXT:    fadd s0, s0, s1
125; CHECK-NEXT:    ret
126  %b = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v16f32(float 0.0, <16 x float> %a)
127  ret float %b
128}
129