1; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=ppc64le-- -mcpu=pwr8 | FileCheck %s --check-prefixes=CHECK,CHECK-P8 2; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=ppc64le-- -mcpu=pwr9 | FileCheck %s --check-prefixes=CHECK,CHECK-P9 3 4define <16 x i8> @test1_v16i8(<16 x i8> %a) { 5 %tmp.1 = mul nsw <16 x i8> %a, <i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16> ; <<16 x i8>> [#uses=1] 6 ret <16 x i8> %tmp.1 7} 8; CHECK-LABEL: test1_v16i8: 9; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 4 10; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 4 11; CHECK-NOT: vmul 12; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]] 13 14define <16 x i8> @test2_v16i8(<16 x i8> %a) { 15 %tmp.1 = mul nsw <16 x i8> %a, <i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17> ; <<16 x i8>> [#uses=1] 16 ret <16 x i8> %tmp.1 17} 18; CHECK-LABEL: test2_v16i8: 19; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 4 20; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 4 21; CHECK-NOT: vmul 22; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]] 23; CHECK-NEXT: vaddubm v[[REG3:[0-9]+]], v2, v[[REG2]] 24 25define <16 x i8> @test3_v16i8(<16 x i8> %a) { 26 %tmp.1 = mul nsw <16 x i8> %a, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15> ; <<16 x i8>> [#uses=1] 27 ret <16 x i8> %tmp.1 28} 29; CHECK-LABEL: test3_v16i8: 30; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 4 31; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 4 32; CHECK-NOT: vmul 33; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]] 34; CHECK-NEXT: vsububm v[[REG3:[0-9]+]], v[[REG2]], v2 35 36; negtive constant 37 38define <16 x i8> @test4_v16i8(<16 x i8> %a) { 39 %tmp.1 = mul nsw <16 x i8> %a, <i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16> ; <<16 x i8>> [#uses=1] 40 ret <16 x i8> %tmp.1 41} 42; CHECK-LABEL: test4_v16i8: 43; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 4 44; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 4 45; CHECK-NOT: vmul 46; CHECK-NEXT: vslb v[[REG3:[0-9]+]], v2, v[[REG1]] 47; CHECK-NEXT: xxlxor v[[REG2:[0-9]+]], 48; CHECK-NEXT: vsububm v[[REG4:[0-9]+]], v[[REG2]], v[[REG3]] 49 50define <16 x i8> @test5_v16i8(<16 x i8> %a) { 51 %tmp.1 = mul nsw <16 x i8> %a, <i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17> ; <<16 x i8>> [#uses=1] 52 ret <16 x i8> %tmp.1 53} 54; CHECK-LABEL: test5_v16i8: 55; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 4 56; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 4 57; CHECK-NOT: vmul 58; CHECK-NEXT: vslb v[[REG3:[0-9]+]], v2, v[[REG1]] 59; CHECK-NEXT: vaddubm v[[REG4:[0-9]+]], v2, v[[REG3]] 60; CHECK-NEXT: xxlxor v[[REG2:[0-9]+]], 61; CHECK-NEXT: vsububm v[[REG5:[0-9]+]], v[[REG2]], v[[REG4]] 62 63define <16 x i8> @test6_v16i8(<16 x i8> %a) { 64 %tmp.1 = mul nsw <16 x i8> %a, <i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15> ; <<16 x i8>> [#uses=1] 65 ret <16 x i8> %tmp.1 66} 67; CHECK-LABEL: test6_v16i8: 68; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 4 69; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 4 70; CHECK-NOT: vmul 71; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]] 72; CHECK-NEXT: vsububm v[[REG3:[0-9]+]], v2, v[[REG2]] 73 74; boundary case 75 76define <16 x i8> @test7_v16i8(<16 x i8> %a) { 77 %tmp.1 = mul nsw <16 x i8> %a, <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128> ; <<16 x i8>> [#uses=1] 78 ret <16 x i8> %tmp.1 79} 80; CHECK-LABEL: test7_v16i8: 81; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 7 82; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 7 83; CHECK-NOT: vmul 84; CHECK-NEXT: vslb v[[REG5:[0-9]+]], v2, v[[REG1]] 85 86define <16 x i8> @test8_v16i8(<16 x i8> %a) { 87 %tmp.1 = mul nsw <16 x i8> %a, <i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127> ; <<16 x i8>> [#uses=1] 88 ret <16 x i8> %tmp.1 89} 90; CHECK-LABEL: test8_v16i8: 91; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 7 92; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 7 93; CHECK-NOT: vmul 94; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]] 95; CHECK-NEXT: vsububm v[[REG3:[0-9]+]], v[[REG2]], v2 96 97define <8 x i16> @test1_v8i16(<8 x i16> %a) { 98 %tmp.1 = mul nsw <8 x i16> %a, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16> ; <<8 x i16>> [#uses=1] 99 ret <8 x i16> %tmp.1 100} 101; CHECK-LABEL: test1_v8i16: 102; CHECK: vspltish v[[REG1:[0-9]+]], 4 103; CHECK-NOT: vmul 104; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]] 105 106define <8 x i16> @test2_v8i16(<8 x i16> %a) { 107 %tmp.1 = mul nsw <8 x i16> %a, <i16 17, i16 17, i16 17, i16 17, i16 17, i16 17, i16 17, i16 17> ; <<8 x i16>> [#uses=1] 108 ret <8 x i16> %tmp.1 109} 110; CHECK-LABEL: test2_v8i16: 111; CHECK: vspltish v[[REG1:[0-9]+]], 4 112; CHECK-NOT: vmul 113; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]] 114; CHECK-NEXT: vadduhm v[[REG3:[0-9]+]], v2, v[[REG2]] 115 116define <8 x i16> @test3_v8i16(<8 x i16> %a) { 117 %tmp.1 = mul nsw <8 x i16> %a, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> ; <<8 x i16>> [#uses=1] 118 ret <8 x i16> %tmp.1 119} 120; CHECK-LABEL: test3_v8i16: 121; CHECK: vspltish v[[REG1:[0-9]+]], 4 122; CHECK-NOT: vmul 123; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]] 124; CHECK-NEXT: vsubuhm v[[REG3:[0-9]+]], v[[REG2]], v2 125 126; negtive constant 127 128define <8 x i16> @test4_v8i16(<8 x i16> %a) { 129 %tmp.1 = mul nsw <8 x i16> %a, <i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16> ; <<8 x i16>> [#uses=1] 130 ret <8 x i16> %tmp.1 131} 132; CHECK-LABEL: test4_v8i16: 133; CHECK: vspltish v[[REG1:[0-9]+]], 4 134; CHECK-NOT: vmul 135; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]] 136; CHECK-NEXT: xxlxor v[[REG2:[0-9]+]], 137; CHECK-NEXT: vsubuhm v[[REG4:[0-9]+]], v[[REG2]], v[[REG3]] 138 139define <8 x i16> @test5_v8i16(<8 x i16> %a) { 140 %tmp.1 = mul nsw <8 x i16> %a, <i16 -17, i16 -17, i16 -17, i16 -17, i16 -17, i16 -17, i16 -17, i16 -17> ; <<8 x i16>> [#uses=1] 141 ret <8 x i16> %tmp.1 142} 143; CHECK-LABEL: test5_v8i16: 144; CHECK: vspltish v[[REG1:[0-9]+]], 4 145; CHECK-NOT: vmul 146; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]] 147; CHECK-NEXT: vadduhm v[[REG4:[0-9]+]], v2, v[[REG3]] 148; CHECK-NEXT: xxlxor v[[REG2:[0-9]+]], 149; CHECK-NEXT: vsubuhm v[[REG5:[0-9]+]], v[[REG2]], v[[REG4]] 150 151define <8 x i16> @test6_v8i16(<8 x i16> %a) { 152 %tmp.1 = mul nsw <8 x i16> %a, <i16 -15, i16 -15, i16 -15, i16 -15, i16 -15, i16 -15, i16 -15, i16 -15> ; <<8 x i16>> [#uses=1] 153 ret <8 x i16> %tmp.1 154} 155; CHECK-LABEL: test6_v8i16: 156; CHECK: vspltish v[[REG1:[0-9]+]], 4 157; CHECK-NOT: vmul 158; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]] 159; CHECK-NEXT: vsubuhm v[[REG3:[0-9]+]], v2, v[[REG2]] 160 161; boundary case 162 163define <8 x i16> @test7_v8i16(<8 x i16> %a) { 164 %tmp.1 = mul nsw <8 x i16> %a, <i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768> ; <<8 x i16>> [#uses=1] 165 ret <8 x i16> %tmp.1 166} 167; CHECK-LABEL: test7_v8i16: 168; CHECK: vspltish v[[REG1:[0-9]+]], 15 169; CHECK-NOT: vmul 170; CHECK-NEXT: vslh v[[REG5:[0-9]+]], v2, v[[REG1]] 171 172define <8 x i16> @test8_v8i16(<8 x i16> %a) { 173 %tmp.1 = mul nsw <8 x i16> %a, <i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767> ; <<8 x i16>> [#uses=1] 174 ret <8 x i16> %tmp.1 175} 176; CHECK-LABEL: test8_v8i16: 177; CHECK: vspltish v[[REG1:[0-9]+]], 15 178; CHECK-NOT: vmul 179; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]] 180; CHECK-NEXT: vsubuhm v[[REG3:[0-9]+]], v[[REG2]], v2 181 182define <4 x i32> @test1_v4i32(<4 x i32> %a) { 183 %tmp.1 = mul nsw <4 x i32> %a, <i32 16, i32 16, i32 16, i32 16> ; <<4 x i32>> [#uses=1] 184 ret <4 x i32> %tmp.1 185} 186; CHECK-LABEL: test1_v4i32: 187; CHECK: vspltisw v[[REG1:[0-9]+]], 4 188; CHECK-NOT: vmul 189; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 190 191define <4 x i32> @test2_v4i32(<4 x i32> %a) { 192 %tmp.1 = mul nsw <4 x i32> %a, <i32 17, i32 17, i32 17, i32 17> ; <<4 x i32>> [#uses=1] 193 ret <4 x i32> %tmp.1 194} 195; CHECK-LABEL: test2_v4i32: 196; CHECK: vspltisw v[[REG1:[0-9]+]], 4 197; CHECK-NOT: vmul 198; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 199; CHECK-NEXT: vadduwm v[[REG3:[0-9]+]], v2, v[[REG2]] 200 201define <4 x i32> @test3_v4i32(<4 x i32> %a) { 202 %tmp.1 = mul nsw <4 x i32> %a, <i32 15, i32 15, i32 15, i32 15> ; <<4 x i32>> [#uses=1] 203 ret <4 x i32> %tmp.1 204} 205; CHECK-LABEL: test3_v4i32: 206; CHECK: vspltisw v[[REG1:[0-9]+]], 4 207; CHECK-NOT: vmul 208; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 209; CHECK-NEXT: vsubuwm v[[REG3:[0-9]+]], v[[REG2]], v2 210 211; negtive constant 212 213define <4 x i32> @test4_v4i32(<4 x i32> %a) { 214 %tmp.1 = mul nsw <4 x i32> %a, <i32 -16, i32 -16, i32 -16, i32 -16> ; <<4 x i32>> [#uses=1] 215 ret <4 x i32> %tmp.1 216} 217; CHECK-LABEL: test4_v4i32: 218; CHECK: vspltisw v[[REG1:[0-9]+]], 4 219; CHECK-NOT: vmul 220; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 221; CHECK-P8-NEXT: xxlxor v[[REG3:[0-9]+]], 222; CHECK-P8-NEXT: vsubuwm v{{[0-9]+}}, v[[REG3]], v[[REG2]] 223; CHECK-P9-NEXT: vnegw v{{[0-9]+}}, v[[REG2]] 224 225define <4 x i32> @test5_v4i32(<4 x i32> %a) { 226 %tmp.1 = mul nsw <4 x i32> %a, <i32 -17, i32 -17, i32 -17, i32 -17> ; <<4 x i32>> [#uses=1] 227 ret <4 x i32> %tmp.1 228} 229; CHECK-LABEL: test5_v4i32: 230; CHECK: vspltisw v[[REG1:[0-9]+]], 4 231; CHECK-NOT: vmul 232; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 233; CHECK-NEXT: vadduwm v[[REG3:[0-9]+]], v2, v[[REG2]] 234; CHECK-P8-NEXT: xxlxor v[[REG4:[0-9]+]], 235; CHECK-P8-NEXT: vsubuwm v{{[0-9]+}}, v[[REG4]], v[[REG3]] 236; CHECK-P9-NEXT: vnegw v{{[0-9]+}}, v[[REG3]] 237 238define <4 x i32> @test6_v4i32(<4 x i32> %a) { 239 %tmp.1 = mul nsw <4 x i32> %a, <i32 -15, i32 -15, i32 -15, i32 -15> ; <<4 x i32>> [#uses=1] 240 ret <4 x i32> %tmp.1 241} 242; CHECK-LABEL: test6_v4i32: 243; CHECK: vspltisw v[[REG1:[0-9]+]], 4 244; CHECK-NOT: vmul 245; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 246; CHECK-NEXT: vsubuwm v[[REG3:[0-9]+]], v2, v[[REG2]] 247 248; boundary case 249 250define <4 x i32> @test7_v4i32(<4 x i32> %a) { 251 %tmp.1 = mul nsw <4 x i32> %a, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> ; <<4 x i32>> [#uses=1] 252 ret <4 x i32> %tmp.1 253} 254; CHECK-LABEL: test7_v4i32: 255; CHECK-DAG: vspltisw v[[REG2:[0-9]+]], -16 256; CHECK-DAG: vspltisw v[[REG3:[0-9]+]], 15 257; CHECK-NEXT: vsubuwm v[[REG4:[0-9]+]], v[[REG3]], v[[REG2]] 258; CHECK-NOT: vmul 259; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]] 260 261define <4 x i32> @test8_v4i32(<4 x i32> %a) { 262 %tmp.1 = mul nsw <4 x i32> %a, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647> ; <<4 x i32>> [#uses=1] 263 ret <4 x i32> %tmp.1 264} 265; CHECK-LABEL: test8_v4i32: 266; CHECK-DAG: vspltisw v[[REG2:[0-9]+]], -16 267; CHECK-DAG: vspltisw v[[REG3:[0-9]+]], 15 268; CHECK-NEXT: vsubuwm v[[REG4:[0-9]+]], v[[REG3]], v[[REG2]] 269; CHECK-NOT: vmul 270; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]] 271; CHECK-NEXT: vsubuwm v[[REG6:[0-9]+]], v[[REG5]], v2 272 273define <2 x i64> @test1_v2i64(<2 x i64> %a) { 274 %tmp.1 = mul nsw <2 x i64> %a, <i64 16, i64 16> ; <<2 x i64>> [#uses=1] 275 ret <2 x i64> %tmp.1 276} 277; CHECK-LABEL: test1_v2i64: 278; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} 279; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] 280; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} 281; CHECK-NOT: vmul 282; CHECK-NEXT: vsld v{{[0-9]+}}, v2, v[[REG2]] 283 284define <2 x i64> @test2_v2i64(<2 x i64> %a) { 285 %tmp.1 = mul nsw <2 x i64> %a, <i64 17, i64 17> ; <<2 x i64>> [#uses=1] 286 ret <2 x i64> %tmp.1 287} 288 289; CHECK-LABEL: test2_v2i64: 290; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} 291; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] 292; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} 293; CHECK-NOT: vmul 294; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]] 295; CHECK-NEXT: vaddudm v{{[0-9]+}}, v2, v[[REG3]] 296 297define <2 x i64> @test3_v2i64(<2 x i64> %a) { 298 %tmp.1 = mul nsw <2 x i64> %a, <i64 15, i64 15> ; <<2 x i64>> [#uses=1] 299 ret <2 x i64> %tmp.1 300} 301 302; CHECK-LABEL: test3_v2i64: 303; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} 304; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] 305; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} 306; CHECK-NOT: vmul 307; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]] 308; CHECK-NEXT: vsubudm v{{[0-9]+}}, v[[REG3]], v2 309 310; negtive constant 311 312define <2 x i64> @test4_v2i64(<2 x i64> %a) { 313 %tmp.1 = mul nsw <2 x i64> %a, <i64 -16, i64 -16> ; <<2 x i64>> [#uses=1] 314 ret <2 x i64> %tmp.1 315} 316 317; CHECK-LABEL: test4_v2i64: 318; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} 319; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] 320; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} 321; CHECK-NOT: vmul 322; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]] 323; CHECK-P8-NEXT: xxlxor v[[REG4:[0-9]+]], 324; CHECK-P8-NEXT: vsubudm v{{[0-9]+}}, v[[REG4]], v[[REG3]] 325; CHECK-P9-NEXT: vnegd v[[REG4:[0-9]+]], v[[REG3]] 326 327define <2 x i64> @test5_v2i64(<2 x i64> %a) { 328 %tmp.1 = mul nsw <2 x i64> %a, <i64 -17, i64 -17> ; <<2 x i64>> [#uses=1] 329 ret <2 x i64> %tmp.1 330} 331 332; CHECK-LABEL: test5_v2i64: 333; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} 334; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] 335; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} 336; CHECK-NOT: vmul 337; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]] 338; CHECK-NEXT: vaddudm v[[REG4:[0-9]+]], v2, v[[REG3]] 339; CHECK-P8-NEXT: xxlxor v[[REG5:[0-9]+]], 340; CHECK-P8-NEXT: vsubudm v[[REG6:[0-9]+]], v[[REG5]], v[[REG4]] 341; CHECK-P9-NEXT: vnegd v{{[0-9]+}}, v[[REG4]] 342 343define <2 x i64> @test6_v2i64(<2 x i64> %a) { 344 %tmp.1 = mul nsw <2 x i64> %a, <i64 -15, i64 -15> ; <<2 x i64>> [#uses=1] 345 ret <2 x i64> %tmp.1 346} 347 348; CHECK-LABEL: test6_v2i64: 349; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} 350; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] 351; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} 352; CHECK-NOT: vmul 353; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]] 354; CHECK-NEXT: vsubudm v{{[0-9]+}}, v2, v[[REG3]] 355 356 357; boundary case 358 359define <2 x i64> @test7_v2i64(<2 x i64> %a) { 360 %tmp.1 = mul nsw <2 x i64> %a, <i64 -9223372036854775808, i64 -9223372036854775808> ; <<2 x i64>> [#uses=1] 361 ret <2 x i64> %tmp.1 362} 363 364; CHECK-LABEL: test7_v2i64: 365; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} 366; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] 367; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} 368; CHECK-NOT: vmul 369; CHECK-NEXT: vsld v[[REG4:[0-9]+]], v2, v[[REG2]] 370 371define <2 x i64> @test8_v2i64(<2 x i64> %a) { 372 %tmp.1 = mul nsw <2 x i64> %a, <i64 9223372036854775807, i64 9223372036854775807> ; <<2 x i64>> [#uses=1] 373 ret <2 x i64> %tmp.1 374} 375 376; CHECK-LABEL: test8_v2i64: 377; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} 378; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] 379; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} 380; CHECK-NOT: vmul 381; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]] 382; CHECK-NEXT: vsubudm v{{[0-9]+}}, v[[REG3]], v2 383