1# RUN: llvm-mc -filetype=obj -triple x86_64 --x86-align-branch-boundary=32 --x86-align-branch=jmp %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s 2 3 # Exercise cases where we're enabling interrupts with one instruction delay 4 # and thus can't add a nop in between without changing behavior. 5 6 .text 7 8 # CHECK: 1e: sti 9 # CHECK: 1f: jmp 10 .p2align 5 11 .rept 30 12 int3 13 .endr 14 sti 15 jmp baz 16 17 # CHECK: 5c: movq %rax, %ss 18 # CHECK: 5f: jmp 19 .p2align 5 20 .rept 28 21 int3 22 .endr 23 movq %rax, %ss 24 jmp baz 25 26 # CHECK: 9d: movl %esi, %ss 27 # CHECK: 9f: jmp 28 .p2align 5 29 .rept 29 30 int3 31 .endr 32 movl %esi, %ss 33 jmp baz 34 35 # movw and movl are interchangeable since we're only using the low 16 bits. 36 # Both are generated as "MOV Sreg,r/m16**" (8E /r), but disassembled as movl 37 # CHECK: dd: movl %esi, %ss 38 # CHECK: df: jmp 39 .p2align 5 40 .rept 29 41 int3 42 .endr 43 movw %si, %ss 44 jmp baz 45 46 # CHECK: 11b: movw (%esi), %ss 47 # CHECK: 11e: jmp 48 .p2align 5 49 .rept 27 50 int3 51 .endr 52 movw (%esi), %ss 53 jmp baz 54 55 # CHECK: 15b: movw (%rsi), %ss 56 # CHECK: 15d: jmp 57 .p2align 5 58 .rept 27 59 int3 60 .endr 61 movw (%rsi), %ss 62 jmp baz 63 64 65 int3 66 .section ".text.other" 67bar: 68 retq 69