1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11
12 #include "AArch64TargetMachine.h"
13 #include "AArch64.h"
14 #include "AArch64MachineFunctionInfo.h"
15 #include "AArch64MacroFusion.h"
16 #include "AArch64Subtarget.h"
17 #include "AArch64TargetObjectFile.h"
18 #include "AArch64TargetTransformInfo.h"
19 #include "MCTargetDesc/AArch64MCTargetDesc.h"
20 #include "TargetInfo/AArch64TargetInfo.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/Analysis/TargetTransformInfo.h"
24 #include "llvm/CodeGen/CSEConfigBase.h"
25 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
26 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
27 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
28 #include "llvm/CodeGen/GlobalISel/Localizer.h"
29 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
30 #include "llvm/CodeGen/MIRParser/MIParser.h"
31 #include "llvm/CodeGen/MachineScheduler.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/CodeGen/TargetPassConfig.h"
34 #include "llvm/IR/Attributes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/InitializePasses.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCTargetOptions.h"
39 #include "llvm/Pass.h"
40 #include "llvm/Support/CodeGen.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/TargetRegistry.h"
43 #include "llvm/Target/TargetLoweringObjectFile.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Transforms/CFGuard.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include <memory>
48 #include <string>
49
50 using namespace llvm;
51
52 static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
53 cl::desc("Enable the CCMP formation pass"),
54 cl::init(true), cl::Hidden);
55
56 static cl::opt<bool>
57 EnableCondBrTuning("aarch64-enable-cond-br-tune",
58 cl::desc("Enable the conditional branch tuning pass"),
59 cl::init(true), cl::Hidden);
60
61 static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
62 cl::desc("Enable the machine combiner pass"),
63 cl::init(true), cl::Hidden);
64
65 static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
66 cl::desc("Suppress STP for AArch64"),
67 cl::init(true), cl::Hidden);
68
69 static cl::opt<bool> EnableAdvSIMDScalar(
70 "aarch64-enable-simd-scalar",
71 cl::desc("Enable use of AdvSIMD scalar integer instructions"),
72 cl::init(false), cl::Hidden);
73
74 static cl::opt<bool>
75 EnablePromoteConstant("aarch64-enable-promote-const",
76 cl::desc("Enable the promote constant pass"),
77 cl::init(true), cl::Hidden);
78
79 static cl::opt<bool> EnableCollectLOH(
80 "aarch64-enable-collect-loh",
81 cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
82 cl::init(true), cl::Hidden);
83
84 static cl::opt<bool>
85 EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
86 cl::desc("Enable the pass that removes dead"
87 " definitons and replaces stores to"
88 " them with stores to the zero"
89 " register"),
90 cl::init(true));
91
92 static cl::opt<bool> EnableRedundantCopyElimination(
93 "aarch64-enable-copyelim",
94 cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
95 cl::Hidden);
96
97 static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
98 cl::desc("Enable the load/store pair"
99 " optimization pass"),
100 cl::init(true), cl::Hidden);
101
102 static cl::opt<bool> EnableAtomicTidy(
103 "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
104 cl::desc("Run SimplifyCFG after expanding atomic operations"
105 " to make use of cmpxchg flow-based information"),
106 cl::init(true));
107
108 static cl::opt<bool>
109 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
110 cl::desc("Run early if-conversion"),
111 cl::init(true));
112
113 static cl::opt<bool>
114 EnableCondOpt("aarch64-enable-condopt",
115 cl::desc("Enable the condition optimizer pass"),
116 cl::init(true), cl::Hidden);
117
118 static cl::opt<bool>
119 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
120 cl::desc("Work around Cortex-A53 erratum 835769"),
121 cl::init(false));
122
123 static cl::opt<bool>
124 EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
125 cl::desc("Enable optimizations on complex GEPs"),
126 cl::init(false));
127
128 static cl::opt<bool>
129 BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
130 cl::desc("Relax out of range conditional branches"));
131
132 static cl::opt<bool> EnableCompressJumpTables(
133 "aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true),
134 cl::desc("Use smallest entry possible for jump tables"));
135
136 // FIXME: Unify control over GlobalMerge.
137 static cl::opt<cl::boolOrDefault>
138 EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
139 cl::desc("Enable the global merge pass"));
140
141 static cl::opt<bool>
142 EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
143 cl::desc("Enable the loop data prefetch pass"),
144 cl::init(true));
145
146 static cl::opt<int> EnableGlobalISelAtO(
147 "aarch64-enable-global-isel-at-O", cl::Hidden,
148 cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
149 cl::init(0));
150
151 static cl::opt<bool>
152 EnableSVEIntrinsicOpts("aarch64-enable-sve-intrinsic-opts", cl::Hidden,
153 cl::desc("Enable SVE intrinsic opts"),
154 cl::init(true));
155
156 static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
157 cl::init(true), cl::Hidden);
158
159 static cl::opt<bool>
160 EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden,
161 cl::desc("Enable the AAcrh64 branch target pass"),
162 cl::init(true));
163
LLVMInitializeAArch64Target()164 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target() {
165 // Register the target.
166 RegisterTargetMachine<AArch64leTargetMachine> X(getTheAArch64leTarget());
167 RegisterTargetMachine<AArch64beTargetMachine> Y(getTheAArch64beTarget());
168 RegisterTargetMachine<AArch64leTargetMachine> Z(getTheARM64Target());
169 RegisterTargetMachine<AArch64leTargetMachine> W(getTheARM64_32Target());
170 RegisterTargetMachine<AArch64leTargetMachine> V(getTheAArch64_32Target());
171 auto PR = PassRegistry::getPassRegistry();
172 initializeGlobalISel(*PR);
173 initializeAArch64A53Fix835769Pass(*PR);
174 initializeAArch64A57FPLoadBalancingPass(*PR);
175 initializeAArch64AdvSIMDScalarPass(*PR);
176 initializeAArch64BranchTargetsPass(*PR);
177 initializeAArch64CollectLOHPass(*PR);
178 initializeAArch64CompressJumpTablesPass(*PR);
179 initializeAArch64ConditionalComparesPass(*PR);
180 initializeAArch64ConditionOptimizerPass(*PR);
181 initializeAArch64DeadRegisterDefinitionsPass(*PR);
182 initializeAArch64ExpandPseudoPass(*PR);
183 initializeAArch64LoadStoreOptPass(*PR);
184 initializeAArch64SIMDInstrOptPass(*PR);
185 initializeAArch64PreLegalizerCombinerPass(*PR);
186 initializeAArch64PostLegalizerCombinerPass(*PR);
187 initializeAArch64PostLegalizerLoweringPass(*PR);
188 initializeAArch64PostSelectOptimizePass(*PR);
189 initializeAArch64PromoteConstantPass(*PR);
190 initializeAArch64RedundantCopyEliminationPass(*PR);
191 initializeAArch64StorePairSuppressPass(*PR);
192 initializeFalkorHWPFFixPass(*PR);
193 initializeFalkorMarkStridedAccessesLegacyPass(*PR);
194 initializeLDTLSCleanupPass(*PR);
195 initializeSVEIntrinsicOptsPass(*PR);
196 initializeAArch64SpeculationHardeningPass(*PR);
197 initializeAArch64SLSHardeningPass(*PR);
198 initializeAArch64StackTaggingPass(*PR);
199 initializeAArch64StackTaggingPreRAPass(*PR);
200 }
201
202 //===----------------------------------------------------------------------===//
203 // AArch64 Lowering public interface.
204 //===----------------------------------------------------------------------===//
createTLOF(const Triple & TT)205 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
206 if (TT.isOSBinFormatMachO())
207 return std::make_unique<AArch64_MachoTargetObjectFile>();
208 if (TT.isOSBinFormatCOFF())
209 return std::make_unique<AArch64_COFFTargetObjectFile>();
210
211 return std::make_unique<AArch64_ELFTargetObjectFile>();
212 }
213
214 // Helper function to build a DataLayout string
computeDataLayout(const Triple & TT,const MCTargetOptions & Options,bool LittleEndian)215 static std::string computeDataLayout(const Triple &TT,
216 const MCTargetOptions &Options,
217 bool LittleEndian) {
218 if (TT.isOSBinFormatMachO()) {
219 if (TT.getArch() == Triple::aarch64_32)
220 return "e-m:o-p:32:32-i64:64-i128:128-n32:64-S128";
221 return "e-m:o-i64:64-i128:128-n32:64-S128";
222 }
223 if (TT.isOSBinFormatCOFF())
224 return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
225 std::string Endian = LittleEndian ? "e" : "E";
226 std::string Ptr32 = TT.getEnvironment() == Triple::GNUILP32 ? "-p:32:32" : "";
227 return Endian + "-m:e" + Ptr32 +
228 "-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
229 }
230
computeDefaultCPU(const Triple & TT,StringRef CPU)231 static StringRef computeDefaultCPU(const Triple &TT, StringRef CPU) {
232 if (CPU.empty() && TT.isArm64e())
233 return "apple-a12";
234 return CPU;
235 }
236
getEffectiveRelocModel(const Triple & TT,Optional<Reloc::Model> RM)237 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
238 Optional<Reloc::Model> RM) {
239 // AArch64 Darwin and Windows are always PIC.
240 if (TT.isOSDarwin() || TT.isOSWindows())
241 return Reloc::PIC_;
242 // On ELF platforms the default static relocation model has a smart enough
243 // linker to cope with referencing external symbols defined in a shared
244 // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
245 if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
246 return Reloc::Static;
247 return *RM;
248 }
249
250 static CodeModel::Model
getEffectiveAArch64CodeModel(const Triple & TT,Optional<CodeModel::Model> CM,bool JIT)251 getEffectiveAArch64CodeModel(const Triple &TT, Optional<CodeModel::Model> CM,
252 bool JIT) {
253 if (CM) {
254 if (*CM != CodeModel::Small && *CM != CodeModel::Tiny &&
255 *CM != CodeModel::Large) {
256 report_fatal_error(
257 "Only small, tiny and large code models are allowed on AArch64");
258 } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF())
259 report_fatal_error("tiny code model is only supported on ELF");
260 return *CM;
261 }
262 // The default MCJIT memory managers make no guarantees about where they can
263 // find an executable page; JITed code needs to be able to refer to globals
264 // no matter how far away they are.
265 // We should set the CodeModel::Small for Windows ARM64 in JIT mode,
266 // since with large code model LLVM generating 4 MOV instructions, and
267 // Windows doesn't support relocating these long branch (4 MOVs).
268 if (JIT && !TT.isOSWindows())
269 return CodeModel::Large;
270 return CodeModel::Small;
271 }
272
273 /// Create an AArch64 architecture model.
274 ///
AArch64TargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Optional<Reloc::Model> RM,Optional<CodeModel::Model> CM,CodeGenOpt::Level OL,bool JIT,bool LittleEndian)275 AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
276 StringRef CPU, StringRef FS,
277 const TargetOptions &Options,
278 Optional<Reloc::Model> RM,
279 Optional<CodeModel::Model> CM,
280 CodeGenOpt::Level OL, bool JIT,
281 bool LittleEndian)
282 : LLVMTargetMachine(T,
283 computeDataLayout(TT, Options.MCOptions, LittleEndian),
284 TT, computeDefaultCPU(TT, CPU), FS, Options,
285 getEffectiveRelocModel(TT, RM),
286 getEffectiveAArch64CodeModel(TT, CM, JIT), OL),
287 TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
288 initAsmInfo();
289
290 if (TT.isOSBinFormatMachO()) {
291 this->Options.TrapUnreachable = true;
292 this->Options.NoTrapAfterNoreturn = true;
293 }
294
295 if (getMCAsmInfo()->usesWindowsCFI()) {
296 // Unwinding can get confused if the last instruction in an
297 // exception-handling region (function, funclet, try block, etc.)
298 // is a call.
299 //
300 // FIXME: We could elide the trap if the next instruction would be in
301 // the same region anyway.
302 this->Options.TrapUnreachable = true;
303 }
304
305 if (this->Options.TLSSize == 0) // default
306 this->Options.TLSSize = 24;
307 if ((getCodeModel() == CodeModel::Small ||
308 getCodeModel() == CodeModel::Kernel) &&
309 this->Options.TLSSize > 32)
310 // for the small (and kernel) code model, the maximum TLS size is 4GiB
311 this->Options.TLSSize = 32;
312 else if (getCodeModel() == CodeModel::Tiny && this->Options.TLSSize > 24)
313 // for the tiny code model, the maximum TLS size is 1MiB (< 16MiB)
314 this->Options.TLSSize = 24;
315
316 // Enable GlobalISel at or below EnableGlobalISelAt0, unless this is
317 // MachO/CodeModel::Large, which GlobalISel does not support.
318 if (getOptLevel() <= EnableGlobalISelAtO &&
319 TT.getArch() != Triple::aarch64_32 &&
320 TT.getEnvironment() != Triple::GNUILP32 &&
321 !(getCodeModel() == CodeModel::Large && TT.isOSBinFormatMachO())) {
322 setGlobalISel(true);
323 setGlobalISelAbort(GlobalISelAbortMode::Disable);
324 }
325
326 // AArch64 supports the MachineOutliner.
327 setMachineOutliner(true);
328
329 // AArch64 supports default outlining behaviour.
330 setSupportsDefaultOutlining(true);
331
332 // AArch64 supports the debug entry values.
333 setSupportsDebugEntryValues(true);
334 }
335
336 AArch64TargetMachine::~AArch64TargetMachine() = default;
337
338 const AArch64Subtarget *
getSubtargetImpl(const Function & F) const339 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
340 Attribute CPUAttr = F.getFnAttribute("target-cpu");
341 Attribute FSAttr = F.getFnAttribute("target-features");
342
343 std::string CPU =
344 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
345 std::string FS =
346 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
347
348 auto &I = SubtargetMap[CPU + FS];
349 if (!I) {
350 // This needs to be done before we create a new subtarget since any
351 // creation will depend on the TM and the code generation flags on the
352 // function that reside in TargetOptions.
353 resetTargetOptions(F);
354 I = std::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
355 isLittle);
356 }
357 return I.get();
358 }
359
anchor()360 void AArch64leTargetMachine::anchor() { }
361
AArch64leTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Optional<Reloc::Model> RM,Optional<CodeModel::Model> CM,CodeGenOpt::Level OL,bool JIT)362 AArch64leTargetMachine::AArch64leTargetMachine(
363 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
364 const TargetOptions &Options, Optional<Reloc::Model> RM,
365 Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
366 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
367
anchor()368 void AArch64beTargetMachine::anchor() { }
369
AArch64beTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Optional<Reloc::Model> RM,Optional<CodeModel::Model> CM,CodeGenOpt::Level OL,bool JIT)370 AArch64beTargetMachine::AArch64beTargetMachine(
371 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
372 const TargetOptions &Options, Optional<Reloc::Model> RM,
373 Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
374 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
375
376 namespace {
377
378 /// AArch64 Code Generator Pass Configuration Options.
379 class AArch64PassConfig : public TargetPassConfig {
380 public:
AArch64PassConfig(AArch64TargetMachine & TM,PassManagerBase & PM)381 AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
382 : TargetPassConfig(TM, PM) {
383 if (TM.getOptLevel() != CodeGenOpt::None)
384 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
385 }
386
getAArch64TargetMachine() const387 AArch64TargetMachine &getAArch64TargetMachine() const {
388 return getTM<AArch64TargetMachine>();
389 }
390
391 ScheduleDAGInstrs *
createMachineScheduler(MachineSchedContext * C) const392 createMachineScheduler(MachineSchedContext *C) const override {
393 const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
394 ScheduleDAGMILive *DAG = createGenericSchedLive(C);
395 DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
396 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
397 if (ST.hasFusion())
398 DAG->addMutation(createAArch64MacroFusionDAGMutation());
399 return DAG;
400 }
401
402 ScheduleDAGInstrs *
createPostMachineScheduler(MachineSchedContext * C) const403 createPostMachineScheduler(MachineSchedContext *C) const override {
404 const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
405 if (ST.hasFusion()) {
406 // Run the Macro Fusion after RA again since literals are expanded from
407 // pseudos then (v. addPreSched2()).
408 ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
409 DAG->addMutation(createAArch64MacroFusionDAGMutation());
410 return DAG;
411 }
412
413 return nullptr;
414 }
415
416 void addIRPasses() override;
417 bool addPreISel() override;
418 bool addInstSelector() override;
419 bool addIRTranslator() override;
420 void addPreLegalizeMachineIR() override;
421 bool addLegalizeMachineIR() override;
422 void addPreRegBankSelect() override;
423 bool addRegBankSelect() override;
424 void addPreGlobalInstructionSelect() override;
425 bool addGlobalInstructionSelect() override;
426 bool addILPOpts() override;
427 void addPreRegAlloc() override;
428 void addPostRegAlloc() override;
429 void addPreSched2() override;
430 void addPreEmitPass() override;
431
432 std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
433 };
434
435 } // end anonymous namespace
436
437 TargetTransformInfo
getTargetTransformInfo(const Function & F)438 AArch64TargetMachine::getTargetTransformInfo(const Function &F) {
439 return TargetTransformInfo(AArch64TTIImpl(this, F));
440 }
441
createPassConfig(PassManagerBase & PM)442 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
443 return new AArch64PassConfig(*this, PM);
444 }
445
getCSEConfig() const446 std::unique_ptr<CSEConfigBase> AArch64PassConfig::getCSEConfig() const {
447 return getStandardCSEConfigForOpt(TM->getOptLevel());
448 }
449
addIRPasses()450 void AArch64PassConfig::addIRPasses() {
451 // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
452 // ourselves.
453 addPass(createAtomicExpandPass());
454
455 // Expand any SVE vector library calls that we can't code generate directly.
456 if (EnableSVEIntrinsicOpts && TM->getOptLevel() == CodeGenOpt::Aggressive)
457 addPass(createSVEIntrinsicOptsPass());
458
459 // Cmpxchg instructions are often used with a subsequent comparison to
460 // determine whether it succeeded. We can exploit existing control-flow in
461 // ldrex/strex loops to simplify this, but it needs tidying up.
462 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
463 addPass(createCFGSimplificationPass(SimplifyCFGOptions()
464 .forwardSwitchCondToPhi(true)
465 .convertSwitchToLookupTable(true)
466 .needCanonicalLoops(false)
467 .hoistCommonInsts(true)
468 .sinkCommonInsts(true)));
469
470 // Run LoopDataPrefetch
471 //
472 // Run this before LSR to remove the multiplies involved in computing the
473 // pointer values N iterations ahead.
474 if (TM->getOptLevel() != CodeGenOpt::None) {
475 if (EnableLoopDataPrefetch)
476 addPass(createLoopDataPrefetchPass());
477 if (EnableFalkorHWPFFix)
478 addPass(createFalkorMarkStridedAccessesPass());
479 }
480
481 TargetPassConfig::addIRPasses();
482
483 addPass(createAArch64StackTaggingPass(
484 /*IsOptNone=*/TM->getOptLevel() == CodeGenOpt::None));
485
486 // Match interleaved memory accesses to ldN/stN intrinsics.
487 if (TM->getOptLevel() != CodeGenOpt::None) {
488 addPass(createInterleavedLoadCombinePass());
489 addPass(createInterleavedAccessPass());
490 }
491
492 if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
493 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
494 // and lower a GEP with multiple indices to either arithmetic operations or
495 // multiple GEPs with single index.
496 addPass(createSeparateConstOffsetFromGEPPass(true));
497 // Call EarlyCSE pass to find and remove subexpressions in the lowered
498 // result.
499 addPass(createEarlyCSEPass());
500 // Do loop invariant code motion in case part of the lowered result is
501 // invariant.
502 addPass(createLICMPass());
503 }
504
505 // Add Control Flow Guard checks.
506 if (TM->getTargetTriple().isOSWindows())
507 addPass(createCFGuardCheckPass());
508 }
509
510 // Pass Pipeline Configuration
addPreISel()511 bool AArch64PassConfig::addPreISel() {
512 // Run promote constant before global merge, so that the promoted constants
513 // get a chance to be merged
514 if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
515 addPass(createAArch64PromoteConstantPass());
516 // FIXME: On AArch64, this depends on the type.
517 // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
518 // and the offset has to be a multiple of the related size in bytes.
519 if ((TM->getOptLevel() != CodeGenOpt::None &&
520 EnableGlobalMerge == cl::BOU_UNSET) ||
521 EnableGlobalMerge == cl::BOU_TRUE) {
522 bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
523 (EnableGlobalMerge == cl::BOU_UNSET);
524
525 // Merging of extern globals is enabled by default on non-Mach-O as we
526 // expect it to be generally either beneficial or harmless. On Mach-O it
527 // is disabled as we emit the .subsections_via_symbols directive which
528 // means that merging extern globals is not safe.
529 bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
530
531 // FIXME: extern global merging is only enabled when we optimise for size
532 // because there are some regressions with it also enabled for performance.
533 if (!OnlyOptimizeForSize)
534 MergeExternalByDefault = false;
535
536 addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize,
537 MergeExternalByDefault));
538 }
539
540 return false;
541 }
542
addInstSelector()543 bool AArch64PassConfig::addInstSelector() {
544 addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
545
546 // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
547 // references to _TLS_MODULE_BASE_ as possible.
548 if (TM->getTargetTriple().isOSBinFormatELF() &&
549 getOptLevel() != CodeGenOpt::None)
550 addPass(createAArch64CleanupLocalDynamicTLSPass());
551
552 return false;
553 }
554
addIRTranslator()555 bool AArch64PassConfig::addIRTranslator() {
556 addPass(new IRTranslator(getOptLevel()));
557 return false;
558 }
559
addPreLegalizeMachineIR()560 void AArch64PassConfig::addPreLegalizeMachineIR() {
561 bool IsOptNone = getOptLevel() == CodeGenOpt::None;
562 addPass(createAArch64PreLegalizerCombiner(IsOptNone));
563 }
564
addLegalizeMachineIR()565 bool AArch64PassConfig::addLegalizeMachineIR() {
566 addPass(new Legalizer());
567 return false;
568 }
569
addPreRegBankSelect()570 void AArch64PassConfig::addPreRegBankSelect() {
571 bool IsOptNone = getOptLevel() == CodeGenOpt::None;
572 if (!IsOptNone)
573 addPass(createAArch64PostLegalizerCombiner(IsOptNone));
574 addPass(createAArch64PostLegalizerLowering());
575 }
576
addRegBankSelect()577 bool AArch64PassConfig::addRegBankSelect() {
578 addPass(new RegBankSelect());
579 return false;
580 }
581
addPreGlobalInstructionSelect()582 void AArch64PassConfig::addPreGlobalInstructionSelect() {
583 addPass(new Localizer());
584 }
585
addGlobalInstructionSelect()586 bool AArch64PassConfig::addGlobalInstructionSelect() {
587 addPass(new InstructionSelect());
588 if (getOptLevel() != CodeGenOpt::None)
589 addPass(createAArch64PostSelectOptimize());
590 return false;
591 }
592
addILPOpts()593 bool AArch64PassConfig::addILPOpts() {
594 if (EnableCondOpt)
595 addPass(createAArch64ConditionOptimizerPass());
596 if (EnableCCMP)
597 addPass(createAArch64ConditionalCompares());
598 if (EnableMCR)
599 addPass(&MachineCombinerID);
600 if (EnableCondBrTuning)
601 addPass(createAArch64CondBrTuning());
602 if (EnableEarlyIfConversion)
603 addPass(&EarlyIfConverterID);
604 if (EnableStPairSuppress)
605 addPass(createAArch64StorePairSuppressPass());
606 addPass(createAArch64SIMDInstrOptPass());
607 if (TM->getOptLevel() != CodeGenOpt::None)
608 addPass(createAArch64StackTaggingPreRAPass());
609 return true;
610 }
611
addPreRegAlloc()612 void AArch64PassConfig::addPreRegAlloc() {
613 // Change dead register definitions to refer to the zero register.
614 if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
615 addPass(createAArch64DeadRegisterDefinitions());
616
617 // Use AdvSIMD scalar instructions whenever profitable.
618 if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
619 addPass(createAArch64AdvSIMDScalar());
620 // The AdvSIMD pass may produce copies that can be rewritten to
621 // be register coalescer friendly.
622 addPass(&PeepholeOptimizerID);
623 }
624 }
625
addPostRegAlloc()626 void AArch64PassConfig::addPostRegAlloc() {
627 // Remove redundant copy instructions.
628 if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
629 addPass(createAArch64RedundantCopyEliminationPass());
630
631 if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
632 // Improve performance for some FP/SIMD code for A57.
633 addPass(createAArch64A57FPLoadBalancing());
634 }
635
addPreSched2()636 void AArch64PassConfig::addPreSched2() {
637 // Expand some pseudo instructions to allow proper scheduling.
638 addPass(createAArch64ExpandPseudoPass());
639 // Use load/store pair instructions when possible.
640 if (TM->getOptLevel() != CodeGenOpt::None) {
641 if (EnableLoadStoreOpt)
642 addPass(createAArch64LoadStoreOptimizationPass());
643 }
644
645 // The AArch64SpeculationHardeningPass destroys dominator tree and natural
646 // loop info, which is needed for the FalkorHWPFFixPass and also later on.
647 // Therefore, run the AArch64SpeculationHardeningPass before the
648 // FalkorHWPFFixPass to avoid recomputing dominator tree and natural loop
649 // info.
650 addPass(createAArch64SpeculationHardeningPass());
651
652 addPass(createAArch64IndirectThunks());
653 addPass(createAArch64SLSHardeningPass());
654
655 if (TM->getOptLevel() != CodeGenOpt::None) {
656 if (EnableFalkorHWPFFix)
657 addPass(createFalkorHWPFFixPass());
658 }
659 }
660
addPreEmitPass()661 void AArch64PassConfig::addPreEmitPass() {
662 // Machine Block Placement might have created new opportunities when run
663 // at O3, where the Tail Duplication Threshold is set to 4 instructions.
664 // Run the load/store optimizer once more.
665 if (TM->getOptLevel() >= CodeGenOpt::Aggressive && EnableLoadStoreOpt)
666 addPass(createAArch64LoadStoreOptimizationPass());
667
668 if (EnableA53Fix835769)
669 addPass(createAArch64A53Fix835769());
670
671 if (EnableBranchTargets)
672 addPass(createAArch64BranchTargetsPass());
673
674 // Relax conditional branch instructions if they're otherwise out of
675 // range of their destination.
676 if (BranchRelaxation)
677 addPass(&BranchRelaxationPassID);
678
679 // Identify valid longjmp targets for Windows Control Flow Guard.
680 if (TM->getTargetTriple().isOSWindows())
681 addPass(createCFGuardLongjmpPass());
682
683 if (TM->getOptLevel() != CodeGenOpt::None && EnableCompressJumpTables)
684 addPass(createAArch64CompressJumpTablesPass());
685
686 if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
687 TM->getTargetTriple().isOSBinFormatMachO())
688 addPass(createAArch64CollectLOHPass());
689
690 // SVE bundles move prefixes with destructive operations.
691 addPass(createUnpackMachineBundles(nullptr));
692 }
693
694 yaml::MachineFunctionInfo *
createDefaultFuncInfoYAML() const695 AArch64TargetMachine::createDefaultFuncInfoYAML() const {
696 return new yaml::AArch64FunctionInfo();
697 }
698
699 yaml::MachineFunctionInfo *
convertFuncInfoToYAML(const MachineFunction & MF) const700 AArch64TargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
701 const auto *MFI = MF.getInfo<AArch64FunctionInfo>();
702 return new yaml::AArch64FunctionInfo(*MFI);
703 }
704
parseMachineFunctionInfo(const yaml::MachineFunctionInfo & MFI,PerFunctionMIParsingState & PFS,SMDiagnostic & Error,SMRange & SourceRange) const705 bool AArch64TargetMachine::parseMachineFunctionInfo(
706 const yaml::MachineFunctionInfo &MFI, PerFunctionMIParsingState &PFS,
707 SMDiagnostic &Error, SMRange &SourceRange) const {
708 const auto &YamlMFI =
709 reinterpret_cast<const yaml::AArch64FunctionInfo &>(MFI);
710 MachineFunction &MF = PFS.MF;
711 MF.getInfo<AArch64FunctionInfo>()->initializeBaseYamlFields(YamlMFI);
712 return false;
713 }
714