1//=-HexagonScheduleV67.td - HexagonV67 Scheduling Definitions *- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//
10// ScalarItin and HVXItin contain some old itineraries
11// still used by a handful of instructions. Hopefully, we will be able
12// to get rid of them soon.
13
14def HexagonV67ItinList : DepScalarItinV66, ScalarItin,
15                         DepHVXItinV66, HVXItin, PseudoItin {
16  list<InstrItinData> ItinList =
17    !listconcat(DepScalarItinV66_list, ScalarItin_list,
18                DepHVXItinV66_list, HVXItin_list, PseudoItin_list);
19}
20
21def HexagonItinerariesV67 :
22      ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
23                            CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
24                            CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL,
25                            CVI_ALL_NOMEM, CVI_ZW],
26                            [Hex_FWD, HVX_FWD],
27                            HexagonV67ItinList.ItinList>;
28
29def HexagonModelV67 : SchedMachineModel {
30  // Max issue per cycle == bundle width.
31  let IssueWidth = 4;
32  let Itineraries = HexagonItinerariesV67;
33  let LoadLatency = 1;
34  let CompleteModel = 0;
35}
36
37//===----------------------------------------------------------------------===//
38// Hexagon V67 Resource Definitions -
39//===----------------------------------------------------------------------===//
40