1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about Hexagon target spec.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "HexagonTargetMachine.h"
14 #include "Hexagon.h"
15 #include "HexagonISelLowering.h"
16 #include "HexagonLoopIdiomRecognition.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "HexagonVectorLoopCarriedReuse.h"
21 #include "TargetInfo/HexagonTargetInfo.h"
22 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/CodeGen/TargetPassConfig.h"
24 #include "llvm/IR/LegacyPassManager.h"
25 #include "llvm/IR/Module.h"
26 #include "llvm/Passes/PassBuilder.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/TargetRegistry.h"
29 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
30 #include "llvm/Transforms/Scalar.h"
31
32 using namespace llvm;
33
34 static cl::opt<bool> EnableCExtOpt("hexagon-cext", cl::Hidden, cl::ZeroOrMore,
35 cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"));
36
37 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
38 cl::init(true), cl::desc("Enable RDF-based optimizations"));
39
40 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
41 cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
42
43 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
44 cl::Hidden, cl::ZeroOrMore, cl::init(false),
45 cl::desc("Disable Hexagon Addressing Mode Optimization"));
46
47 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
48 cl::Hidden, cl::ZeroOrMore, cl::init(false),
49 cl::desc("Disable Hexagon CFG Optimization"));
50
51 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
52 cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
53
54 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
55 cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
56
57 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
58 cl::init(true), cl::Hidden, cl::ZeroOrMore,
59 cl::desc("Early expansion of MUX"));
60
61 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
62 cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
63
64 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
65 cl::Hidden, cl::desc("Generate \"insert\" instructions"));
66
67 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
68 cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
69
70 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
71 cl::Hidden, cl::desc("Generate \"extract\" instructions"));
72
73 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
74 cl::desc("Enable converting conditional transfers into MUX instructions"));
75
76 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
77 cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
78 "predicate instructions"));
79
80 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
81 cl::init(false), cl::Hidden, cl::ZeroOrMore,
82 cl::desc("Enable loop data prefetch on Hexagon"));
83
84 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
85 cl::desc("Disable splitting double registers"));
86
87 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
88 cl::Hidden, cl::desc("Bit simplification"));
89
90 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
91 cl::Hidden, cl::desc("Loop rescheduling"));
92
93 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
94 cl::Hidden, cl::desc("Disable backend optimizations"));
95
96 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
97 cl::Hidden, cl::ZeroOrMore, cl::init(false),
98 cl::desc("Enable Hexagon Vector print instr pass"));
99
100 static cl::opt<bool> EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden,
101 cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization"));
102
103 static cl::opt<bool> EnableVectorCombine("hexagon-vector-combine", cl::Hidden,
104 cl::ZeroOrMore, cl::init(true), cl::desc("Enable HVX vector combining"));
105
106 static cl::opt<bool> EnableInitialCFGCleanup("hexagon-initial-cfg-cleanup",
107 cl::Hidden, cl::ZeroOrMore, cl::init(true),
108 cl::desc("Simplify the CFG after atomic expansion pass"));
109
110 static cl::opt<bool> EnableInstSimplify("hexagon-instsimplify", cl::Hidden,
111 cl::ZeroOrMore, cl::init(true),
112 cl::desc("Enable instsimplify"));
113
114 /// HexagonTargetMachineModule - Note that this is used on hosts that
115 /// cannot link in a library unless there are references into the
116 /// library. In particular, it seems that it is not possible to get
117 /// things to work on Win32 without this. Though it is unused, do not
118 /// remove it.
119 extern "C" int HexagonTargetMachineModule;
120 int HexagonTargetMachineModule = 0;
121
createVLIWMachineSched(MachineSchedContext * C)122 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
123 ScheduleDAGMILive *DAG =
124 new VLIWMachineScheduler(C, std::make_unique<ConvergingVLIWScheduler>());
125 DAG->addMutation(std::make_unique<HexagonSubtarget::UsrOverflowMutation>());
126 DAG->addMutation(std::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
127 DAG->addMutation(std::make_unique<HexagonSubtarget::CallMutation>());
128 DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
129 return DAG;
130 }
131
132 static MachineSchedRegistry
133 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
134 createVLIWMachineSched);
135
136 namespace llvm {
137 extern char &HexagonExpandCondsetsID;
138 void initializeHexagonBitSimplifyPass(PassRegistry&);
139 void initializeHexagonConstExtendersPass(PassRegistry&);
140 void initializeHexagonConstPropagationPass(PassRegistry&);
141 void initializeHexagonEarlyIfConversionPass(PassRegistry&);
142 void initializeHexagonExpandCondsetsPass(PassRegistry&);
143 void initializeHexagonGenMuxPass(PassRegistry&);
144 void initializeHexagonHardwareLoopsPass(PassRegistry&);
145 void initializeHexagonLoopIdiomRecognizeLegacyPassPass(PassRegistry &);
146 void initializeHexagonNewValueJumpPass(PassRegistry&);
147 void initializeHexagonOptAddrModePass(PassRegistry&);
148 void initializeHexagonPacketizerPass(PassRegistry&);
149 void initializeHexagonRDFOptPass(PassRegistry&);
150 void initializeHexagonSplitDoubleRegsPass(PassRegistry&);
151 void initializeHexagonVectorCombineLegacyPass(PassRegistry&);
152 void initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PassRegistry &);
153 void initializeHexagonVExtractPass(PassRegistry&);
154 Pass *createHexagonLoopIdiomPass();
155 Pass *createHexagonVectorLoopCarriedReuseLegacyPass();
156
157 FunctionPass *createHexagonBitSimplify();
158 FunctionPass *createHexagonBranchRelaxation();
159 FunctionPass *createHexagonCallFrameInformation();
160 FunctionPass *createHexagonCFGOptimizer();
161 FunctionPass *createHexagonCommonGEP();
162 FunctionPass *createHexagonConstExtenders();
163 FunctionPass *createHexagonConstPropagationPass();
164 FunctionPass *createHexagonCopyToCombine();
165 FunctionPass *createHexagonEarlyIfConversion();
166 FunctionPass *createHexagonFixupHwLoops();
167 FunctionPass *createHexagonGenExtract();
168 FunctionPass *createHexagonGenInsert();
169 FunctionPass *createHexagonGenMux();
170 FunctionPass *createHexagonGenPredicate();
171 FunctionPass *createHexagonHardwareLoops();
172 FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
173 CodeGenOpt::Level OptLevel);
174 FunctionPass *createHexagonLoopRescheduling();
175 FunctionPass *createHexagonNewValueJump();
176 FunctionPass *createHexagonOptAddrMode();
177 FunctionPass *createHexagonOptimizeSZextends();
178 FunctionPass *createHexagonPacketizer(bool Minimal);
179 FunctionPass *createHexagonPeephole();
180 FunctionPass *createHexagonRDFOpt();
181 FunctionPass *createHexagonSplitConst32AndConst64();
182 FunctionPass *createHexagonSplitDoubleRegs();
183 FunctionPass *createHexagonStoreWidening();
184 FunctionPass *createHexagonVectorCombineLegacyPass();
185 FunctionPass *createHexagonVectorPrint();
186 FunctionPass *createHexagonVExtract();
187 } // end namespace llvm;
188
getEffectiveRelocModel(Optional<Reloc::Model> RM)189 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
190 return RM.getValueOr(Reloc::Static);
191 }
192
LLVMInitializeHexagonTarget()193 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget() {
194 // Register the target.
195 RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
196
197 PassRegistry &PR = *PassRegistry::getPassRegistry();
198 initializeHexagonBitSimplifyPass(PR);
199 initializeHexagonConstExtendersPass(PR);
200 initializeHexagonConstPropagationPass(PR);
201 initializeHexagonEarlyIfConversionPass(PR);
202 initializeHexagonGenMuxPass(PR);
203 initializeHexagonHardwareLoopsPass(PR);
204 initializeHexagonLoopIdiomRecognizeLegacyPassPass(PR);
205 initializeHexagonNewValueJumpPass(PR);
206 initializeHexagonOptAddrModePass(PR);
207 initializeHexagonPacketizerPass(PR);
208 initializeHexagonRDFOptPass(PR);
209 initializeHexagonSplitDoubleRegsPass(PR);
210 initializeHexagonVectorCombineLegacyPass(PR);
211 initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PR);
212 initializeHexagonVExtractPass(PR);
213 }
214
HexagonTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Optional<Reloc::Model> RM,Optional<CodeModel::Model> CM,CodeGenOpt::Level OL,bool JIT)215 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
216 StringRef CPU, StringRef FS,
217 const TargetOptions &Options,
218 Optional<Reloc::Model> RM,
219 Optional<CodeModel::Model> CM,
220 CodeGenOpt::Level OL, bool JIT)
221 // Specify the vector alignment explicitly. For v512x1, the calculated
222 // alignment would be 512*alignment(i1), which is 512 bytes, instead of
223 // the required minimum of 64 bytes.
224 : LLVMTargetMachine(
225 T,
226 "e-m:e-p:32:32:32-a:0-n16:32-"
227 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
228 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
229 TT, CPU, FS, Options, getEffectiveRelocModel(RM),
230 getEffectiveCodeModel(CM, CodeModel::Small),
231 (HexagonNoOpt ? CodeGenOpt::None : OL)),
232 TLOF(std::make_unique<HexagonTargetObjectFile>()) {
233 initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
234 initAsmInfo();
235 }
236
237 const HexagonSubtarget *
getSubtargetImpl(const Function & F) const238 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
239 AttributeList FnAttrs = F.getAttributes();
240 Attribute CPUAttr =
241 FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu");
242 Attribute FSAttr =
243 FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features");
244
245 std::string CPU =
246 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
247 std::string FS =
248 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
249 // Append the preexisting target features last, so that +mattr overrides
250 // the "unsafe-fp-math" function attribute.
251 // Creating a separate target feature is not strictly necessary, it only
252 // exists to make "unsafe-fp-math" force creating a new subtarget.
253
254 if (FnAttrs.hasFnAttribute("unsafe-fp-math") &&
255 F.getFnAttribute("unsafe-fp-math").getValueAsString() == "true")
256 FS = FS.empty() ? "+unsafe-fp" : "+unsafe-fp," + FS;
257
258 auto &I = SubtargetMap[CPU + FS];
259 if (!I) {
260 // This needs to be done before we create a new subtarget since any
261 // creation will depend on the TM and the code generation flags on the
262 // function that reside in TargetOptions.
263 resetTargetOptions(F);
264 I = std::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
265 }
266 return I.get();
267 }
268
adjustPassManager(PassManagerBuilder & PMB)269 void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
270 PMB.addExtension(
271 PassManagerBuilder::EP_LateLoopOptimizations,
272 [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
273 PM.add(createHexagonLoopIdiomPass());
274 });
275 PMB.addExtension(
276 PassManagerBuilder::EP_LoopOptimizerEnd,
277 [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
278 PM.add(createHexagonVectorLoopCarriedReuseLegacyPass());
279 });
280 }
281
registerPassBuilderCallbacks(PassBuilder & PB,bool DebugPassManager)282 void HexagonTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB,
283 bool DebugPassManager) {
284 PB.registerLateLoopOptimizationsEPCallback(
285 [=](LoopPassManager &LPM, PassBuilder::OptimizationLevel Level) {
286 LPM.addPass(HexagonLoopIdiomRecognitionPass());
287 });
288 PB.registerLoopOptimizerEndEPCallback(
289 [=](LoopPassManager &LPM, PassBuilder::OptimizationLevel Level) {
290 LPM.addPass(HexagonVectorLoopCarriedReusePass());
291 });
292 }
293
294 TargetTransformInfo
getTargetTransformInfo(const Function & F)295 HexagonTargetMachine::getTargetTransformInfo(const Function &F) {
296 return TargetTransformInfo(HexagonTTIImpl(this, F));
297 }
298
299
~HexagonTargetMachine()300 HexagonTargetMachine::~HexagonTargetMachine() {}
301
302 namespace {
303 /// Hexagon Code Generator Pass Configuration Options.
304 class HexagonPassConfig : public TargetPassConfig {
305 public:
HexagonPassConfig(HexagonTargetMachine & TM,PassManagerBase & PM)306 HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
307 : TargetPassConfig(TM, PM) {}
308
getHexagonTargetMachine() const309 HexagonTargetMachine &getHexagonTargetMachine() const {
310 return getTM<HexagonTargetMachine>();
311 }
312
313 ScheduleDAGInstrs *
createMachineScheduler(MachineSchedContext * C) const314 createMachineScheduler(MachineSchedContext *C) const override {
315 return createVLIWMachineSched(C);
316 }
317
318 void addIRPasses() override;
319 bool addInstSelector() override;
320 void addPreRegAlloc() override;
321 void addPostRegAlloc() override;
322 void addPreSched2() override;
323 void addPreEmitPass() override;
324 };
325 } // namespace
326
createPassConfig(PassManagerBase & PM)327 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
328 return new HexagonPassConfig(*this, PM);
329 }
330
addIRPasses()331 void HexagonPassConfig::addIRPasses() {
332 TargetPassConfig::addIRPasses();
333 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
334
335 if (!NoOpt) {
336 if (EnableInstSimplify)
337 addPass(createInstSimplifyLegacyPass());
338 addPass(createDeadCodeEliminationPass());
339 }
340
341 addPass(createAtomicExpandPass());
342
343 if (!NoOpt) {
344 if (EnableInitialCFGCleanup)
345 addPass(createCFGSimplificationPass(SimplifyCFGOptions()
346 .forwardSwitchCondToPhi(true)
347 .convertSwitchToLookupTable(true)
348 .needCanonicalLoops(false)
349 .hoistCommonInsts(true)
350 .sinkCommonInsts(true)));
351 if (EnableLoopPrefetch)
352 addPass(createLoopDataPrefetchPass());
353 if (EnableVectorCombine)
354 addPass(createHexagonVectorCombineLegacyPass());
355 if (EnableCommGEP)
356 addPass(createHexagonCommonGEP());
357 // Replace certain combinations of shifts and ands with extracts.
358 if (EnableGenExtract)
359 addPass(createHexagonGenExtract());
360 }
361 }
362
addInstSelector()363 bool HexagonPassConfig::addInstSelector() {
364 HexagonTargetMachine &TM = getHexagonTargetMachine();
365 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
366
367 if (!NoOpt)
368 addPass(createHexagonOptimizeSZextends());
369
370 addPass(createHexagonISelDag(TM, getOptLevel()));
371
372 if (!NoOpt) {
373 if (EnableVExtractOpt)
374 addPass(createHexagonVExtract());
375 // Create logical operations on predicate registers.
376 if (EnableGenPred)
377 addPass(createHexagonGenPredicate());
378 // Rotate loops to expose bit-simplification opportunities.
379 if (EnableLoopResched)
380 addPass(createHexagonLoopRescheduling());
381 // Split double registers.
382 if (!DisableHSDR)
383 addPass(createHexagonSplitDoubleRegs());
384 // Bit simplification.
385 if (EnableBitSimplify)
386 addPass(createHexagonBitSimplify());
387 addPass(createHexagonPeephole());
388 // Constant propagation.
389 if (!DisableHCP) {
390 addPass(createHexagonConstPropagationPass());
391 addPass(&UnreachableMachineBlockElimID);
392 }
393 if (EnableGenInsert)
394 addPass(createHexagonGenInsert());
395 if (EnableEarlyIf)
396 addPass(createHexagonEarlyIfConversion());
397 }
398
399 return false;
400 }
401
addPreRegAlloc()402 void HexagonPassConfig::addPreRegAlloc() {
403 if (getOptLevel() != CodeGenOpt::None) {
404 if (EnableCExtOpt)
405 addPass(createHexagonConstExtenders());
406 if (EnableExpandCondsets)
407 insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
408 if (!DisableStoreWidening)
409 addPass(createHexagonStoreWidening());
410 if (!DisableHardwareLoops)
411 addPass(createHexagonHardwareLoops());
412 }
413 if (TM->getOptLevel() >= CodeGenOpt::Default)
414 addPass(&MachinePipelinerID);
415 }
416
addPostRegAlloc()417 void HexagonPassConfig::addPostRegAlloc() {
418 if (getOptLevel() != CodeGenOpt::None) {
419 if (EnableRDFOpt)
420 addPass(createHexagonRDFOpt());
421 if (!DisableHexagonCFGOpt)
422 addPass(createHexagonCFGOptimizer());
423 if (!DisableAModeOpt)
424 addPass(createHexagonOptAddrMode());
425 }
426 }
427
addPreSched2()428 void HexagonPassConfig::addPreSched2() {
429 addPass(createHexagonCopyToCombine());
430 if (getOptLevel() != CodeGenOpt::None)
431 addPass(&IfConverterID);
432 addPass(createHexagonSplitConst32AndConst64());
433 }
434
addPreEmitPass()435 void HexagonPassConfig::addPreEmitPass() {
436 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
437
438 if (!NoOpt)
439 addPass(createHexagonNewValueJump());
440
441 addPass(createHexagonBranchRelaxation());
442
443 if (!NoOpt) {
444 if (!DisableHardwareLoops)
445 addPass(createHexagonFixupHwLoops());
446 // Generate MUX from pairs of conditional transfers.
447 if (EnableGenMux)
448 addPass(createHexagonGenMux());
449 }
450
451 // Packetization is mandatory: it handles gather/scatter at all opt levels.
452 addPass(createHexagonPacketizer(NoOpt), false);
453
454 if (EnableVectorPrint)
455 addPass(createHexagonVectorPrint(), false);
456
457 // Add CFI instructions if necessary.
458 addPass(createHexagonCallFrameInformation(), false);
459 }
460