1; RUN: llc -march=amdgcn -verify-machineinstrs< %s | FileCheck --check-prefix=SI --check-prefix=CHECK %s
2; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs< %s | FileCheck --check-prefix=CI --check-prefix=CHECK %s
3; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck --check-prefix=CI --check-prefix=CHECK %s
4
5define amdgpu_kernel void @use_gep_address_space([1024 x i32] addrspace(3)* %array) nounwind {
6; CHECK-LABEL: {{^}}use_gep_address_space:
7; CHECK: v_mov_b32_e32 [[PTR:v[0-9]+]], s{{[0-9]+}}
8; CHECK: ds_write_b32 [[PTR]], v{{[0-9]+}} offset:64
9  %p = getelementptr [1024 x i32], [1024 x i32] addrspace(3)* %array, i16 0, i16 16
10  store i32 99, i32 addrspace(3)* %p
11  ret void
12}
13
14; CHECK-LABEL: {{^}}use_gep_address_space_large_offset:
15; The LDS offset will be 65536 bytes, which is larger than the size of LDS on
16; SI, which is why it is being OR'd with the base pointer.
17; SI: s_bitset1_b32
18; CI: s_add_i32
19; CHECK: ds_write_b32
20define amdgpu_kernel void @use_gep_address_space_large_offset([1024 x i32] addrspace(3)* %array) nounwind {
21  %p = getelementptr [1024 x i32], [1024 x i32] addrspace(3)* %array, i16 0, i16 16384
22  store i32 99, i32 addrspace(3)* %p
23  ret void
24}
25
26; CHECK-LABEL: {{^}}gep_as_vector_v4:
27; SI: s_add_i32
28; SI: s_add_i32
29; SI: s_add_i32
30; SI: s_add_i32
31
32; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
33; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
34; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
35; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
36
37; CI-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:64
38; CI-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:64
39; CI-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:64
40; CI-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:64
41; CHECK: s_endpgm
42define amdgpu_kernel void @gep_as_vector_v4(<4 x [1024 x i32] addrspace(3)*> %array) nounwind {
43  %p = getelementptr [1024 x i32], <4 x [1024 x i32] addrspace(3)*> %array, <4 x i16> zeroinitializer, <4 x i16> <i16 16, i16 16, i16 16, i16 16>
44  %p0 = extractelement <4 x i32 addrspace(3)*> %p, i32 0
45  %p1 = extractelement <4 x i32 addrspace(3)*> %p, i32 1
46  %p2 = extractelement <4 x i32 addrspace(3)*> %p, i32 2
47  %p3 = extractelement <4 x i32 addrspace(3)*> %p, i32 3
48  store i32 99, i32 addrspace(3)* %p0
49  store i32 99, i32 addrspace(3)* %p1
50  store i32 99, i32 addrspace(3)* %p2
51  store i32 99, i32 addrspace(3)* %p3
52  ret void
53}
54
55; CHECK-LABEL: {{^}}gep_as_vector_v2:
56; SI: s_add_i32
57; SI: s_add_i32
58; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
59; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
60; CI-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:64
61; CI-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:64
62; CHECK: s_endpgm
63define amdgpu_kernel void @gep_as_vector_v2(<2 x [1024 x i32] addrspace(3)*> %array) nounwind {
64  %p = getelementptr [1024 x i32], <2 x [1024 x i32] addrspace(3)*> %array, <2 x i16> zeroinitializer, <2 x i16> <i16 16, i16 16>
65  %p0 = extractelement <2 x i32 addrspace(3)*> %p, i32 0
66  %p1 = extractelement <2 x i32 addrspace(3)*> %p, i32 1
67  store i32 99, i32 addrspace(3)* %p0
68  store i32 99, i32 addrspace(3)* %p1
69  ret void
70}
71
72