1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=si-remove-short-exec-branches -amdgpu-skip-threshold=10 -verify-machineinstrs %s -o - | FileCheck %s 3# Make sure mandatory skips are not removed around mode defs. 4# FIXME: -amdgpu-skip-threshold seems to be backwards. 5 6--- 7 8name: need_skip_setreg_imm32_b32 9body: | 10 ; CHECK-LABEL: name: need_skip_setreg_imm32_b32 11 ; CHECK: bb.0: 12 ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) 13 ; CHECK: S_CBRANCH_EXECZ %bb.2, implicit $exec 14 ; CHECK: bb.1: 15 ; CHECK: successors: %bb.2(0x80000000) 16 ; CHECK: $vgpr0 = V_MOV_B32_e32 0, implicit $exec 17 ; CHECK: S_SETREG_IMM32_B32 3, 2177, implicit-def $mode, implicit $mode 18 ; CHECK: bb.2: 19 ; CHECK: S_ENDPGM 0 20 bb.0: 21 successors: %bb.1, %bb.2 22 S_CBRANCH_EXECZ %bb.2, implicit $exec 23 24 bb.1: 25 successors: %bb.2 26 $vgpr0 = V_MOV_B32_e32 0, implicit $exec 27 S_SETREG_IMM32_B32 3, 2177, implicit-def $mode, implicit $mode 28 29 bb.2: 30 S_ENDPGM 0 31... 32 33--- 34 35name: need_skip_setreg_b32 36body: | 37 ; CHECK-LABEL: name: need_skip_setreg_b32 38 ; CHECK: bb.0: 39 ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) 40 ; CHECK: S_CBRANCH_EXECZ %bb.2, implicit $exec 41 ; CHECK: bb.1: 42 ; CHECK: successors: %bb.2(0x80000000) 43 ; CHECK: $vgpr0 = V_MOV_B32_e32 0, implicit $exec 44 ; CHECK: S_SETREG_B32 $sgpr0, 3, implicit-def $mode, implicit $mode 45 ; CHECK: bb.2: 46 ; CHECK: S_ENDPGM 0 47 bb.0: 48 liveins: $sgpr0 49 successors: %bb.1, %bb.2 50 S_CBRANCH_EXECZ %bb.2, implicit $exec 51 52 bb.1: 53 liveins: $sgpr0 54 $vgpr0 = V_MOV_B32_e32 0, implicit $exec 55 S_SETREG_B32 $sgpr0, 3, implicit-def $mode, implicit $mode 56 57 bb.2: 58 S_ENDPGM 0 59... 60 61--- 62 63name: need_skip_denorm_mode 64body: | 65 ; CHECK-LABEL: name: need_skip_denorm_mode 66 ; CHECK: bb.0: 67 ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) 68 ; CHECK: S_CBRANCH_EXECZ %bb.2, implicit $exec 69 ; CHECK: bb.1: 70 ; CHECK: successors: %bb.2(0x80000000) 71 ; CHECK: $vgpr0 = V_MOV_B32_e32 0, implicit $exec 72 ; CHECK: S_DENORM_MODE 3, implicit-def $mode, implicit $mode 73 ; CHECK: bb.2: 74 ; CHECK: S_ENDPGM 0 75 bb.0: 76 successors: %bb.1, %bb.2 77 S_CBRANCH_EXECZ %bb.2, implicit $exec 78 79 bb.1: 80 $vgpr0 = V_MOV_B32_e32 0, implicit $exec 81 S_DENORM_MODE 3, implicit-def $mode, implicit $mode 82 83 bb.2: 84 S_ENDPGM 0 85... 86 87--- 88 89name: need_skip_round_mode 90body: | 91 ; CHECK-LABEL: name: need_skip_round_mode 92 ; CHECK: bb.0: 93 ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) 94 ; CHECK: S_CBRANCH_EXECZ %bb.2, implicit $exec 95 ; CHECK: bb.1: 96 ; CHECK: successors: %bb.2(0x80000000) 97 ; CHECK: $vgpr0 = V_MOV_B32_e32 0, implicit $exec 98 ; CHECK: S_ROUND_MODE 3, implicit-def $mode, implicit $mode 99 ; CHECK: bb.2: 100 ; CHECK: S_ENDPGM 0 101 bb.0: 102 successors: %bb.1, %bb.2 103 S_CBRANCH_EXECZ %bb.2, implicit $exec 104 105 bb.1: 106 $vgpr0 = V_MOV_B32_e32 0, implicit $exec 107 S_ROUND_MODE 3, implicit-def $mode, implicit $mode 108 109 bb.2: 110 S_ENDPGM 0 111... 112 113--- 114 115name: need_skip_writelane_b32 116body: | 117 ; CHECK-LABEL: name: need_skip_writelane_b32 118 ; CHECK: bb.0: 119 ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) 120 ; CHECK: S_CBRANCH_EXECZ %bb.2, implicit $exec 121 ; CHECK: bb.1: 122 ; CHECK: successors: %bb.2(0x80000000) 123 ; CHECK: $sgpr0 = IMPLICIT_DEF 124 ; CHECK: $vgpr0 = V_WRITELANE_B32 $sgpr0, 0, $vgpr0 125 ; CHECK: bb.2: 126 ; CHECK: S_ENDPGM 0 127 bb.0: 128 successors: %bb.1, %bb.2 129 S_CBRANCH_EXECZ %bb.2, implicit $exec 130 131 bb.1: 132 successors: %bb.2 133 $sgpr0 = IMPLICIT_DEF 134 $vgpr0 = V_WRITELANE_B32 $sgpr0, 0, $vgpr0 135 136 bb.2: 137 S_ENDPGM 0 138... 139 140--- 141name: need_skip_readlane_b32 142body: | 143 ; CHECK-LABEL: name: need_skip_readlane_b32 144 ; CHECK: bb.0: 145 ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) 146 ; CHECK: S_CBRANCH_EXECZ %bb.2, implicit $exec 147 ; CHECK: bb.1: 148 ; CHECK: successors: %bb.2(0x80000000) 149 ; CHECK: $vgpr0 = IMPLICIT_DEF 150 ; CHECK: $sgpr0 = V_READLANE_B32 $vgpr0, 0 151 ; CHECK: bb.2: 152 ; CHECK: S_ENDPGM 0 153 bb.0: 154 successors: %bb.1, %bb.2 155 S_CBRANCH_EXECZ %bb.2, implicit $exec 156 157 bb.1: 158 successors: %bb.2 159 $vgpr0 = IMPLICIT_DEF 160 $sgpr0 = V_READLANE_B32 $vgpr0, 0 161 162 bb.2: 163 S_ENDPGM 0 164... 165