1; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \ 2; RUN: -verify-machineinstrs < %s | FileCheck %s 3 4; Function Attrs: nounwind readnone 5define zeroext i32 @testCTZ32(i32 signext %a) { 6entry: 7 %0 = tail call i32 @llvm.cttz.i32(i32 %a, i1 false) 8 ret i32 %0 9; CHECK-LABEL: testCTZ32 10; CHECK: cnttzw 3, 3 11} 12 13; Function Attrs: nounwind readnone 14declare i32 @llvm.cttz.i32(i32, i1) 15 16; Function Attrs: nounwind readnone 17define zeroext i32 @testCTZ64(i64 %a) { 18entry: 19 %0 = tail call i64 @llvm.cttz.i64(i64 %a, i1 false) 20 %cast = trunc i64 %0 to i32 21 ret i32 %cast 22; CHECK-LABEL: testCTZ64 23; CHECK: cnttzd 3, 3 24} 25 26; Function Attrs: nounwind readnone 27declare i64 @llvm.cttz.i64(i64, i1) 28 29; Function Attrs: nounwind readnone 30define <16 x i8> @testVCMPNEB(<16 x i8> %a, <16 x i8> %b) { 31entry: 32 %0 = tail call <16 x i8> @llvm.ppc.altivec.vcmpneb(<16 x i8> %a, <16 x i8> %b) 33 ret <16 x i8> %0 34; CHECK-LABEL: testVCMPNEB 35; CHECK: vcmpneb 2, 2 36} 37 38; Function Attrs: nounwind readnone 39declare <16 x i8> @llvm.ppc.altivec.vcmpneb(<16 x i8>, <16 x i8>) 40 41; Function Attrs: nounwind readnone 42define <16 x i8> @testVCMPNEZB(<16 x i8> %a, <16 x i8> %b) { 43entry: 44 %0 = tail call <16 x i8> @llvm.ppc.altivec.vcmpnezb(<16 x i8> %a, <16 x i8> %b) 45 ret <16 x i8> %0 46; CHECK-LABEL: testVCMPNEZB 47; CHECK: vcmpnezb 2, 2 48} 49 50; Function Attrs: nounwind readnone 51declare <16 x i8> @llvm.ppc.altivec.vcmpnezb(<16 x i8>, <16 x i8>) 52 53; Function Attrs: nounwind readnone 54define <8 x i16> @testVCMPNEH(<8 x i16> %a, <8 x i16> %b) { 55entry: 56 %0 = tail call <8 x i16> @llvm.ppc.altivec.vcmpneh(<8 x i16> %a, <8 x i16> %b) 57 ret <8 x i16> %0 58; CHECK-LABEL: testVCMPNEH 59; CHECK: vcmpneh 2, 2 60} 61 62; Function Attrs: nounwind readnone 63declare <8 x i16> @llvm.ppc.altivec.vcmpneh(<8 x i16>, <8 x i16>) 64 65; Function Attrs: nounwind readnone 66define <8 x i16> @testVCMPNEZH(<8 x i16> %a, <8 x i16> %b) { 67entry: 68 %0 = tail call <8 x i16> @llvm.ppc.altivec.vcmpnezh(<8 x i16> %a, <8 x i16> %b) 69 ret <8 x i16> %0 70; CHECK-LABEL: testVCMPNEZH 71; CHECK: vcmpnezh 2, 2 72} 73 74; Function Attrs: nounwind readnone 75declare <8 x i16> @llvm.ppc.altivec.vcmpnezh(<8 x i16>, <8 x i16>) 76 77; Function Attrs: nounwind readnone 78define <4 x i32> @testVCMPNEW(<4 x i32> %a, <4 x i32> %b) { 79entry: 80 %0 = tail call <4 x i32> @llvm.ppc.altivec.vcmpnew(<4 x i32> %a, <4 x i32> %b) 81 ret <4 x i32> %0 82; CHECK-LABEL: testVCMPNEW 83; CHECK: vcmpnew 2, 2 84} 85 86; Function Attrs: nounwind readnone 87declare <4 x i32> @llvm.ppc.altivec.vcmpnew(<4 x i32>, <4 x i32>) 88 89; Function Attrs: nounwind readnone 90define <4 x i32> @testVCMPNEZW(<4 x i32> %a, <4 x i32> %b) { 91entry: 92 %0 = tail call <4 x i32> @llvm.ppc.altivec.vcmpnezw(<4 x i32> %a, <4 x i32> %b) 93 ret <4 x i32> %0 94; CHECK-LABEL: testVCMPNEZW 95; CHECK: vcmpnezw 2, 2 96} 97 98; Function Attrs: nounwind readnone 99declare <4 x i32> @llvm.ppc.altivec.vcmpnezw(<4 x i32>, <4 x i32>) 100 101; Function Attrs: nounwind readnone 102define <16 x i8> @testVCNTTZB(<16 x i8> %a) { 103entry: 104 %0 = tail call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %a, i1 false) 105 ret <16 x i8> %0 106; CHECK-LABEL: testVCNTTZB 107; CHECK: vctzb 2, 2 108} 109 110; Function Attrs: nounwind readnone 111define <8 x i16> @testVCNTTZH(<8 x i16> %a) { 112entry: 113 %0 = tail call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %a, i1 false) 114 ret <8 x i16> %0 115; CHECK-LABEL: testVCNTTZH 116; CHECK: vctzh 2, 2 117} 118 119; Function Attrs: nounwind readnone 120define <4 x i32> @testVCNTTZW(<4 x i32> %a) { 121entry: 122 %0 = tail call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %a, i1 false) 123 ret <4 x i32> %0 124; CHECK-LABEL: testVCNTTZW 125; CHECK: vctzw 2, 2 126} 127 128; Function Attrs: nounwind readnone 129define <2 x i64> @testVCNTTZD(<2 x i64> %a) { 130entry: 131 %0 = tail call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a, i1 false) 132 ret <2 x i64> %0 133; CHECK-LABEL: testVCNTTZD 134; CHECK: vctzd 2, 2 135} 136 137; Function Attrs: nounwind readnone 138declare <16 x i8> @llvm.cttz.v16i8(<16 x i8>, i1) 139 140; Function Attrs: nounwind readnone 141declare <8 x i16> @llvm.cttz.v8i16(<8 x i16>, i1) 142 143; Function Attrs: nounwind readnone 144declare <4 x i32> @llvm.cttz.v4i32(<4 x i32>, i1) 145 146; Function Attrs: nounwind readnone 147declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>, i1) 148 149; Function Attrs: nounwind readnone 150define i32 @testVCLZLSBB(<16 x i8> %a) { 151entry: 152 %0 = tail call i32 @llvm.ppc.altivec.vclzlsbb(<16 x i8> %a) 153 ret i32 %0 154; CHECK-LABEL: testVCLZLSBB 155; CHECK: vclzlsbb 3, 2 156} 157; Function Attrs: nounwind readnone 158declare i32 @llvm.ppc.altivec.vclzlsbb(<16 x i8>) 159 160; Function Attrs: nounwind readnone 161define i32 @testVCTZLSBB(<16 x i8> %a) { 162entry: 163 %0 = tail call i32 @llvm.ppc.altivec.vctzlsbb(<16 x i8> %a) 164 ret i32 %0 165; CHECK-LABEL: testVCTZLSBB 166; CHECK: vctzlsbb 3, 2 167} 168; Function Attrs: nounwind readnone 169declare i32 @llvm.ppc.altivec.vctzlsbb(<16 x i8>) 170 171; Function Attrs: nounwind readnone 172define <4 x i32> @testVPRTYBW(<4 x i32> %a) { 173entry: 174 %0 = tail call <4 x i32> @llvm.ppc.altivec.vprtybw(<4 x i32> %a) 175 ret <4 x i32> %0 176; CHECK-LABEL: testVPRTYBW 177; CHECK: vprtybw 2, 2 178} 179; Function Attrs: nounwind readnone 180declare <4 x i32> @llvm.ppc.altivec.vprtybw(<4 x i32>) 181 182; Function Attrs: nounwind readnone 183define <2 x i64> @testVPRTYBD(<2 x i64> %a) { 184entry: 185 %0 = tail call <2 x i64> @llvm.ppc.altivec.vprtybd(<2 x i64> %a) 186 ret <2 x i64> %0 187; CHECK-LABEL: testVPRTYBD 188; CHECK: vprtybd 2, 2 189} 190; Function Attrs: nounwind readnone 191declare <2 x i64> @llvm.ppc.altivec.vprtybd(<2 x i64>) 192 193; Function Attrs: nounwind readnone 194define <1 x i128> @testVPRTYBQ(<1 x i128> %a) { 195entry: 196 %0 = tail call <1 x i128> @llvm.ppc.altivec.vprtybq(<1 x i128> %a) 197 ret <1 x i128> %0 198; CHECK-LABEL: testVPRTYBQ 199; CHECK: vprtybq 2, 2 200} 201; Function Attrs: nounwind readnone 202declare <1 x i128> @llvm.ppc.altivec.vprtybq(<1 x i128>) 203