1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-LE
3; RUN: llc -mtriple=powerpc64-linux-gnu -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-BE
4
5@as = dso_local local_unnamed_addr global i16 0, align 2
6@bs = dso_local local_unnamed_addr global i16 0, align 2
7@ai = dso_local local_unnamed_addr global i32 0, align 4
8@bi = dso_local local_unnamed_addr global i32 0, align 4
9
10define dso_local void @bswapStorei64Toi32() {
11; CHECK-LABEL: bswapStorei64Toi32:
12; CHECK:       # %bb.0: # %entry
13; CHECK-NEXT:    addis 3, 2, ai@toc@ha
14; CHECK-NEXT:    addis 4, 2, bi@toc@ha
15; CHECK-NEXT:    lwa 3, ai@toc@l(3)
16; CHECK-NEXT:    addi 4, 4, bi@toc@l
17; CHECK-NEXT:    rldicl 3, 3, 32, 32
18; CHECK-NEXT:    stwbrx 3, 0, 4
19; CHECK-NEXT:    blr
20; CHECK-LE-LABEL: bswapStorei64Toi32:
21; CHECK-LE:       # %bb.0: # %entry
22; CHECK-LE-NEXT:    addis 3, 2, ai@toc@ha
23; CHECK-LE-NEXT:    addis 4, 2, bi@toc@ha
24; CHECK-LE-NEXT:    lwa 3, ai@toc@l(3)
25; CHECK-LE-NEXT:    addi 4, 4, bi@toc@l
26; CHECK-LE-NEXT:    rldicl 3, 3, 32, 32
27; CHECK-LE-NEXT:    stwbrx 3, 0, 4
28; CHECK-LE-NEXT:    blr
29;
30; CHECK-BE-LABEL: bswapStorei64Toi32:
31; CHECK-BE:       # %bb.0: # %entry
32; CHECK-BE-NEXT:    addis 3, 2, ai@toc@ha
33; CHECK-BE-NEXT:    addis 4, 2, bi@toc@ha
34; CHECK-BE-NEXT:    lwa 3, ai@toc@l(3)
35; CHECK-BE-NEXT:    addi 4, 4, bi@toc@l
36; CHECK-BE-NEXT:    rldicl 3, 3, 32, 32
37; CHECK-BE-NEXT:    stwbrx 3, 0, 4
38; CHECK-BE-NEXT:    blr
39entry:
40  %0 = load i32, i32* @ai, align 4
41  %conv.i = sext i32 %0 to i64
42  %or26.i = tail call i64 @llvm.bswap.i64(i64 %conv.i)
43  %conv = trunc i64 %or26.i to i32
44  store i32 %conv, i32* @bi, align 4
45  ret void
46}
47
48define dso_local void @bswapStorei32Toi16() {
49; CHECK-LABEL: bswapStorei32Toi16:
50; CHECK:       # %bb.0: # %entry
51; CHECK-NEXT:    addis 3, 2, as@toc@ha
52; CHECK-NEXT:    addis 4, 2, bs@toc@ha
53; CHECK-NEXT:    lha 3, as@toc@l(3)
54; CHECK-NEXT:    addi 4, 4, bs@toc@l
55; CHECK-NEXT:    srwi 3, 3, 16
56; CHECK-NEXT:    sthbrx 3, 0, 4
57; CHECK-NEXT:    blr
58; CHECK-LE-LABEL: bswapStorei32Toi16:
59; CHECK-LE:       # %bb.0: # %entry
60; CHECK-LE-NEXT:    addis 3, 2, as@toc@ha
61; CHECK-LE-NEXT:    addis 4, 2, bs@toc@ha
62; CHECK-LE-NEXT:    lha 3, as@toc@l(3)
63; CHECK-LE-NEXT:    addi 4, 4, bs@toc@l
64; CHECK-LE-NEXT:    srwi 3, 3, 16
65; CHECK-LE-NEXT:    sthbrx 3, 0, 4
66; CHECK-LE-NEXT:    blr
67;
68; CHECK-BE-LABEL: bswapStorei32Toi16:
69; CHECK-BE:       # %bb.0: # %entry
70; CHECK-BE-NEXT:    addis 3, 2, as@toc@ha
71; CHECK-BE-NEXT:    addis 4, 2, bs@toc@ha
72; CHECK-BE-NEXT:    lha 3, as@toc@l(3)
73; CHECK-BE-NEXT:    addi 4, 4, bs@toc@l
74; CHECK-BE-NEXT:    srwi 3, 3, 16
75; CHECK-BE-NEXT:    sthbrx 3, 0, 4
76; CHECK-BE-NEXT:    blr
77entry:
78  %0 = load i16, i16* @as, align 2
79  %conv.i = sext i16 %0 to i32
80  %or26.i = tail call i32 @llvm.bswap.i32(i32 %conv.i)
81  %conv = trunc i32 %or26.i to i16
82  store i16 %conv, i16* @bs, align 2
83  ret void
84}
85
86define dso_local void @bswapStorei64Toi16() {
87; CHECK-LABEL: bswapStorei64Toi16:
88; CHECK:       # %bb.0: # %entry
89; CHECK-NEXT:    addis 3, 2, as@toc@ha
90; CHECK-NEXT:    addis 4, 2, bs@toc@ha
91; CHECK-NEXT:    lha 3, as@toc@l(3)
92; CHECK-NEXT:    addi 4, 4, bs@toc@l
93; CHECK-NEXT:    rldicl 3, 3, 16, 48
94; CHECK-NEXT:    sthbrx 3, 0, 4
95; CHECK-NEXT:    blr
96; CHECK-LE-LABEL: bswapStorei64Toi16:
97; CHECK-LE:       # %bb.0: # %entry
98; CHECK-LE-NEXT:    addis 3, 2, as@toc@ha
99; CHECK-LE-NEXT:    addis 4, 2, bs@toc@ha
100; CHECK-LE-NEXT:    lha 3, as@toc@l(3)
101; CHECK-LE-NEXT:    addi 4, 4, bs@toc@l
102; CHECK-LE-NEXT:    rldicl 3, 3, 16, 48
103; CHECK-LE-NEXT:    sthbrx 3, 0, 4
104; CHECK-LE-NEXT:    blr
105;
106; CHECK-BE-LABEL: bswapStorei64Toi16:
107; CHECK-BE:       # %bb.0: # %entry
108; CHECK-BE-NEXT:    addis 3, 2, as@toc@ha
109; CHECK-BE-NEXT:    addis 4, 2, bs@toc@ha
110; CHECK-BE-NEXT:    lha 3, as@toc@l(3)
111; CHECK-BE-NEXT:    addi 4, 4, bs@toc@l
112; CHECK-BE-NEXT:    rldicl 3, 3, 16, 48
113; CHECK-BE-NEXT:    sthbrx 3, 0, 4
114; CHECK-BE-NEXT:    blr
115entry:
116  %0 = load i16, i16* @as, align 2
117  %conv.i = sext i16 %0 to i64
118  %or26.i = tail call i64 @llvm.bswap.i64(i64 %conv.i)
119  %conv = trunc i64 %or26.i to i16
120  store i16 %conv, i16* @bs, align 2
121  ret void
122}
123
124declare i32 @llvm.bswap.i32(i32)
125declare i64 @llvm.bswap.i64(i64)
126