1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=powerpc64le-- | FileCheck %s
3
4; If positive...
5
6define i32 @zext_ifpos(i32 %x) {
7; CHECK-LABEL: zext_ifpos:
8; CHECK:       # %bb.0:
9; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
10; CHECK-NEXT:    xori 3, 3, 1
11; CHECK-NEXT:    blr
12  %c = icmp sgt i32 %x, -1
13  %e = zext i1 %c to i32
14  ret i32 %e
15}
16
17define i32 @add_zext_ifpos(i32 %x) {
18; CHECK-LABEL: add_zext_ifpos:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    srawi 3, 3, 31
21; CHECK-NEXT:    addi 3, 3, 42
22; CHECK-NEXT:    blr
23  %c = icmp sgt i32 %x, -1
24  %e = zext i1 %c to i32
25  %r = add i32 %e, 41
26  ret i32 %r
27}
28
29define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) {
30; CHECK-LABEL: add_zext_ifpos_vec_splat:
31; CHECK:       # %bb.0:
32; CHECK-NEXT:    xxleqv 35, 35, 35
33; CHECK-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
34; CHECK-NEXT:    addi 3, 3, .LCPI2_0@toc@l
35; CHECK-NEXT:    vcmpgtsw 2, 2, 3
36; CHECK-NEXT:    lvx 3, 0, 3
37; CHECK-NEXT:    vsubuwm 2, 3, 2
38; CHECK-NEXT:    blr
39  %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
40  %e = zext <4 x i1> %c to <4 x i32>
41  %r = add <4 x i32> %e, <i32 41, i32 41, i32 41, i32 41>
42  ret <4 x i32> %r
43}
44
45define i32 @sel_ifpos_tval_bigger(i32 %x) {
46; CHECK-LABEL: sel_ifpos_tval_bigger:
47; CHECK:       # %bb.0:
48; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
49; CHECK-NEXT:    xori 3, 3, 1
50; CHECK-NEXT:    addi 3, 3, 41
51; CHECK-NEXT:    blr
52  %c = icmp sgt i32 %x, -1
53  %r = select i1 %c, i32 42, i32 41
54  ret i32 %r
55}
56
57define i32 @sext_ifpos(i32 %x) {
58; CHECK-LABEL: sext_ifpos:
59; CHECK:       # %bb.0:
60; CHECK-NEXT:    not 3, 3
61; CHECK-NEXT:    srawi 3, 3, 31
62; CHECK-NEXT:    blr
63  %c = icmp sgt i32 %x, -1
64  %e = sext i1 %c to i32
65  ret i32 %e
66}
67
68define i32 @add_sext_ifpos(i32 %x) {
69; CHECK-LABEL: add_sext_ifpos:
70; CHECK:       # %bb.0:
71; CHECK-NEXT:    srwi 3, 3, 31
72; CHECK-NEXT:    addi 3, 3, 41
73; CHECK-NEXT:    blr
74  %c = icmp sgt i32 %x, -1
75  %e = sext i1 %c to i32
76  %r = add i32 %e, 42
77  ret i32 %r
78}
79
80define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) {
81; CHECK-LABEL: add_sext_ifpos_vec_splat:
82; CHECK:       # %bb.0:
83; CHECK-NEXT:    xxleqv 35, 35, 35
84; CHECK-NEXT:    addis 3, 2, .LCPI6_0@toc@ha
85; CHECK-NEXT:    addi 3, 3, .LCPI6_0@toc@l
86; CHECK-NEXT:    vcmpgtsw 2, 2, 3
87; CHECK-NEXT:    lvx 3, 0, 3
88; CHECK-NEXT:    vadduwm 2, 2, 3
89; CHECK-NEXT:    blr
90  %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
91  %e = sext <4 x i1> %c to <4 x i32>
92  %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
93  ret <4 x i32> %r
94}
95
96define i32 @sel_ifpos_fval_bigger(i32 %x) {
97; CHECK-LABEL: sel_ifpos_fval_bigger:
98; CHECK:       # %bb.0:
99; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
100; CHECK-NEXT:    xori 3, 3, 1
101; CHECK-NEXT:    subfic 3, 3, 42
102; CHECK-NEXT:    blr
103  %c = icmp sgt i32 %x, -1
104  %r = select i1 %c, i32 41, i32 42
105  ret i32 %r
106}
107
108; If negative...
109
110define i32 @zext_ifneg(i32 %x) {
111; CHECK-LABEL: zext_ifneg:
112; CHECK:       # %bb.0:
113; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
114; CHECK-NEXT:    blr
115  %c = icmp slt i32 %x, 0
116  %r = zext i1 %c to i32
117  ret i32 %r
118}
119
120define i32 @add_zext_ifneg(i32 %x) {
121; CHECK-LABEL: add_zext_ifneg:
122; CHECK:       # %bb.0:
123; CHECK-NEXT:    srwi 3, 3, 31
124; CHECK-NEXT:    addi 3, 3, 41
125; CHECK-NEXT:    blr
126  %c = icmp slt i32 %x, 0
127  %e = zext i1 %c to i32
128  %r = add i32 %e, 41
129  ret i32 %r
130}
131
132define i32 @sel_ifneg_tval_bigger(i32 %x) {
133; CHECK-LABEL: sel_ifneg_tval_bigger:
134; CHECK:       # %bb.0:
135; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
136; CHECK-NEXT:    addi 3, 3, 41
137; CHECK-NEXT:    blr
138  %c = icmp slt i32 %x, 0
139  %r = select i1 %c, i32 42, i32 41
140  ret i32 %r
141}
142
143define i32 @sext_ifneg(i32 %x) {
144; CHECK-LABEL: sext_ifneg:
145; CHECK:       # %bb.0:
146; CHECK-NEXT:    srawi 3, 3, 31
147; CHECK-NEXT:    blr
148  %c = icmp slt i32 %x, 0
149  %r = sext i1 %c to i32
150  ret i32 %r
151}
152
153define i32 @add_sext_ifneg(i32 %x) {
154; CHECK-LABEL: add_sext_ifneg:
155; CHECK:       # %bb.0:
156; CHECK-NEXT:    srawi 3, 3, 31
157; CHECK-NEXT:    addi 3, 3, 42
158; CHECK-NEXT:    blr
159  %c = icmp slt i32 %x, 0
160  %e = sext i1 %c to i32
161  %r = add i32 %e, 42
162  ret i32 %r
163}
164
165define i32 @sel_ifneg_fval_bigger(i32 %x) {
166; CHECK-LABEL: sel_ifneg_fval_bigger:
167; CHECK:       # %bb.0:
168; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
169; CHECK-NEXT:    subfic 3, 3, 42
170; CHECK-NEXT:    blr
171  %c = icmp slt i32 %x, 0
172  %r = select i1 %c, i32 41, i32 42
173  ret i32 %r
174}
175
176define i32 @add_lshr_not(i32 %x) {
177; CHECK-LABEL: add_lshr_not:
178; CHECK:       # %bb.0:
179; CHECK-NEXT:    srawi 3, 3, 31
180; CHECK-NEXT:    addi 3, 3, 42
181; CHECK-NEXT:    blr
182  %not = xor i32 %x, -1
183  %sh = lshr i32 %not, 31
184  %r = add i32 %sh, 41
185  ret i32 %r
186}
187
188define <4 x i32> @add_lshr_not_vec_splat(<4 x i32> %x) {
189; CHECK-LABEL: add_lshr_not_vec_splat:
190; CHECK:       # %bb.0:
191; CHECK-NEXT:    vspltisw 3, -16
192; CHECK-NEXT:    vspltisw 4, 15
193; CHECK-NEXT:    addis 3, 2, .LCPI15_0@toc@ha
194; CHECK-NEXT:    addi 3, 3, .LCPI15_0@toc@l
195; CHECK-NEXT:    vsubuwm 3, 4, 3
196; CHECK-NEXT:    vsraw 2, 2, 3
197; CHECK-NEXT:    lvx 3, 0, 3
198; CHECK-NEXT:    vadduwm 2, 2, 3
199; CHECK-NEXT:    blr
200  %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
201  %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
202  %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
203  ret <4 x i32> %r
204}
205
206define i32 @sub_lshr_not(i32 %x) {
207; CHECK-LABEL: sub_lshr_not:
208; CHECK:       # %bb.0:
209; CHECK-NEXT:    srwi 3, 3, 31
210; CHECK-NEXT:    ori 3, 3, 42
211; CHECK-NEXT:    blr
212  %not = xor i32 %x, -1
213  %sh = lshr i32 %not, 31
214  %r = sub i32 43, %sh
215  ret i32 %r
216}
217
218define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) {
219; CHECK-LABEL: sub_lshr_not_vec_splat:
220; CHECK:       # %bb.0:
221; CHECK-NEXT:    vspltisw 3, -16
222; CHECK-NEXT:    vspltisw 4, 15
223; CHECK-NEXT:    addis 3, 2, .LCPI17_0@toc@ha
224; CHECK-NEXT:    addi 3, 3, .LCPI17_0@toc@l
225; CHECK-NEXT:    vsubuwm 3, 4, 3
226; CHECK-NEXT:    vsrw 2, 2, 3
227; CHECK-NEXT:    lvx 3, 0, 3
228; CHECK-NEXT:    vadduwm 2, 2, 3
229; CHECK-NEXT:    blr
230  %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
231  %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
232  %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e
233  ret <4 x i32> %r
234}
235
236define i32 @sub_lshr(i32 %x, i32 %y) {
237; CHECK-LABEL: sub_lshr:
238; CHECK:       # %bb.0:
239; CHECK-NEXT:    srawi 3, 3, 31
240; CHECK-NEXT:    add 3, 4, 3
241; CHECK-NEXT:    blr
242  %sh = lshr i32 %x, 31
243  %r = sub i32 %y, %sh
244  ret i32 %r
245}
246
247define <4 x i32> @sub_lshr_vec(<4 x i32> %x, <4 x i32> %y) {
248; CHECK-LABEL: sub_lshr_vec:
249; CHECK:       # %bb.0:
250; CHECK-NEXT:    vspltisw 4, -16
251; CHECK-NEXT:    vspltisw 5, 15
252; CHECK-NEXT:    vsubuwm 4, 5, 4
253; CHECK-NEXT:    vsraw 2, 2, 4
254; CHECK-NEXT:    vadduwm 2, 3, 2
255; CHECK-NEXT:    blr
256  %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
257  %r = sub <4 x i32> %y, %sh
258  ret <4 x i32> %r
259}
260
261define i32 @sub_const_op_lshr(i32 %x) {
262; CHECK-LABEL: sub_const_op_lshr:
263; CHECK:       # %bb.0:
264; CHECK-NEXT:    srawi 3, 3, 31
265; CHECK-NEXT:    addi 3, 3, 43
266; CHECK-NEXT:    blr
267  %sh = lshr i32 %x, 31
268  %r = sub i32 43, %sh
269  ret i32 %r
270}
271
272define <4 x i32> @sub_const_op_lshr_vec(<4 x i32> %x) {
273; CHECK-LABEL: sub_const_op_lshr_vec:
274; CHECK:       # %bb.0:
275; CHECK-NEXT:    vspltisw 3, -16
276; CHECK-NEXT:    vspltisw 4, 15
277; CHECK-NEXT:    addis 3, 2, .LCPI21_0@toc@ha
278; CHECK-NEXT:    addi 3, 3, .LCPI21_0@toc@l
279; CHECK-NEXT:    vsubuwm 3, 4, 3
280; CHECK-NEXT:    vsraw 2, 2, 3
281; CHECK-NEXT:    lvx 3, 0, 3
282; CHECK-NEXT:    vadduwm 2, 2, 3
283; CHECK-NEXT:    blr
284  %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
285  %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %sh
286  ret <4 x i32> %r
287}
288
289