1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
7; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
8; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
9; RUN:   -ppc-asm-full-reg-names -mcpu=pwr10 < %s | \
10; RUN:   FileCheck %s --check-prefix=CHECK-P10
11; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
12; RUN:   -ppc-asm-full-reg-names -mcpu=pwr10 < %s | \
13; RUN:   FileCheck %s --check-prefix=CHECK-P10
14; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
15; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr10 < %s | \
16; RUN:   FileCheck %s --check-prefix=CHECK-P10-CMP \
17; RUN:   --implicit-check-not cmpld --implicit-check-not cmplw
18; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
19; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr10 < %s | \
20; RUN:   FileCheck %s --check-prefix=CHECK-P10-CMP \
21; RUN:   --implicit-check-not cmpld --implicit-check-not cmplw
22
23define signext i32 @test(i8 zeroext %a, i8 zeroext %b) {
24; CHECK-LABEL: test:
25; CHECK:       # %bb.0: # %entry
26; CHECK-NEXT:    clrlwi r3, r3, 31
27; CHECK-NEXT:    clrlwi r4, r4, 31
28; CHECK-NEXT:    clrldi r3, r3, 32
29; CHECK-NEXT:    clrldi r4, r4, 32
30; CHECK-NEXT:    sub r3, r4, r3
31; CHECK-NEXT:    rldicl r3, r3, 1, 63
32; CHECK-NEXT:    xori r3, r3, 1
33; CHECK-NEXT:    blr
34;
35; CHECK-P10-LABEL: test:
36; CHECK-P10:       # %bb.0: # %entry
37; CHECK-P10-NEXT:    clrlwi r3, r3, 31
38; CHECK-P10-NEXT:    clrlwi r4, r4, 31
39; CHECK-P10-NEXT:    cmplw r3, r4
40; CHECK-P10-NEXT:    setbcr r3, gt
41; CHECK-P10-NEXT:    blr
42;
43; CHECK-P10-CMP-LABEL: test:
44; CHECK-P10-CMP:       # %bb.0: # %entry
45; CHECK-P10-CMP-NEXT:    clrlwi r3, r3, 31
46; CHECK-P10-CMP-NEXT:    clrlwi r4, r4, 31
47; CHECK-P10-CMP-NEXT:    clrldi r3, r3, 32
48; CHECK-P10-CMP-NEXT:    clrldi r4, r4, 32
49; CHECK-P10-CMP-NEXT:    sub r3, r4, r3
50; CHECK-P10-CMP-NEXT:    rldicl r3, r3, 1, 63
51; CHECK-P10-CMP-NEXT:    xori r3, r3, 1
52; CHECK-P10-CMP-NEXT:    blr
53entry:
54  %0 = and i8 %a, 1
55  %1 = and i8 %b, 1
56  %cmp = icmp ule i8 %0, %1
57  %conv3 = zext i1 %cmp to i32
58  ret i32 %conv3
59}
60