1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 3; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 4; RUN: FileCheck %s --check-prefix=CHECK-P8 5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 6; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 7; RUN: FileCheck %s --check-prefix=CHECK-P9 8; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ 9; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 10; RUN: FileCheck %s --check-prefix=CHECK-BE 11 12define <2 x i64> @test2elt(i64 %a.coerce) local_unnamed_addr #0 { 13; CHECK-P8-LABEL: test2elt: 14; CHECK-P8: # %bb.0: # %entry 15; CHECK-P8-NEXT: mtfprd f0, r3 16; CHECK-P8-NEXT: xxswapd v2, vs0 17; CHECK-P8-NEXT: xxmrglw vs0, v2, v2 18; CHECK-P8-NEXT: xvcvspdp vs0, vs0 19; CHECK-P8-NEXT: xvcvdpuxds v2, vs0 20; CHECK-P8-NEXT: blr 21; 22; CHECK-P9-LABEL: test2elt: 23; CHECK-P9: # %bb.0: # %entry 24; CHECK-P9-NEXT: mtfprd f0, r3 25; CHECK-P9-NEXT: xxswapd v2, vs0 26; CHECK-P9-NEXT: xxmrglw vs0, v2, v2 27; CHECK-P9-NEXT: xvcvspdp vs0, vs0 28; CHECK-P9-NEXT: xvcvdpuxds v2, vs0 29; CHECK-P9-NEXT: blr 30; 31; CHECK-BE-LABEL: test2elt: 32; CHECK-BE: # %bb.0: # %entry 33; CHECK-BE-NEXT: mtfprd f0, r3 34; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs0 35; CHECK-BE-NEXT: xvcvspdp vs0, vs0 36; CHECK-BE-NEXT: xvcvdpuxds v2, vs0 37; CHECK-BE-NEXT: blr 38entry: 39 %0 = bitcast i64 %a.coerce to <2 x float> 40 %1 = fptoui <2 x float> %0 to <2 x i64> 41 ret <2 x i64> %1 42} 43 44define void @test4elt(<4 x i64>* noalias nocapture sret(<4 x i64>) %agg.result, <4 x float> %a) local_unnamed_addr #1 { 45; CHECK-P8-LABEL: test4elt: 46; CHECK-P8: # %bb.0: # %entry 47; CHECK-P8-NEXT: xxmrglw vs0, v2, v2 48; CHECK-P8-NEXT: xxmrghw vs1, v2, v2 49; CHECK-P8-NEXT: li r4, 16 50; CHECK-P8-NEXT: xvcvspdp vs0, vs0 51; CHECK-P8-NEXT: xvcvspdp vs1, vs1 52; CHECK-P8-NEXT: xvcvdpuxds v2, vs0 53; CHECK-P8-NEXT: xvcvdpuxds v3, vs1 54; CHECK-P8-NEXT: xxswapd vs1, v2 55; CHECK-P8-NEXT: xxswapd vs0, v3 56; CHECK-P8-NEXT: stxvd2x vs0, r3, r4 57; CHECK-P8-NEXT: stxvd2x vs1, 0, r3 58; CHECK-P8-NEXT: blr 59; 60; CHECK-P9-LABEL: test4elt: 61; CHECK-P9: # %bb.0: # %entry 62; CHECK-P9-NEXT: xxmrglw vs0, v2, v2 63; CHECK-P9-NEXT: xxmrghw vs1, v2, v2 64; CHECK-P9-NEXT: xvcvspdp vs0, vs0 65; CHECK-P9-NEXT: xvcvspdp vs1, vs1 66; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0 67; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1 68; CHECK-P9-NEXT: stxv vs1, 16(r3) 69; CHECK-P9-NEXT: stxv vs0, 0(r3) 70; CHECK-P9-NEXT: blr 71; 72; CHECK-BE-LABEL: test4elt: 73; CHECK-BE: # %bb.0: # %entry 74; CHECK-BE-NEXT: xxmrghw vs0, v2, v2 75; CHECK-BE-NEXT: xxmrglw vs1, v2, v2 76; CHECK-BE-NEXT: xvcvspdp vs0, vs0 77; CHECK-BE-NEXT: xvcvspdp vs1, vs1 78; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0 79; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1 80; CHECK-BE-NEXT: stxv vs1, 16(r3) 81; CHECK-BE-NEXT: stxv vs0, 0(r3) 82; CHECK-BE-NEXT: blr 83entry: 84 %0 = fptoui <4 x float> %a to <4 x i64> 85 store <4 x i64> %0, <4 x i64>* %agg.result, align 32 86 ret void 87} 88 89define void @test8elt(<8 x i64>* noalias nocapture sret(<8 x i64>) %agg.result, <8 x float>* nocapture readonly) local_unnamed_addr #2 { 90; CHECK-P8-LABEL: test8elt: 91; CHECK-P8: # %bb.0: # %entry 92; CHECK-P8-NEXT: li r5, 16 93; CHECK-P8-NEXT: lvx v3, 0, r4 94; CHECK-P8-NEXT: li r6, 32 95; CHECK-P8-NEXT: lvx v2, r4, r5 96; CHECK-P8-NEXT: li r4, 48 97; CHECK-P8-NEXT: xxmrglw vs2, v3, v3 98; CHECK-P8-NEXT: xxmrghw vs3, v3, v3 99; CHECK-P8-NEXT: xxmrglw vs0, v2, v2 100; CHECK-P8-NEXT: xxmrghw vs1, v2, v2 101; CHECK-P8-NEXT: xvcvspdp vs2, vs2 102; CHECK-P8-NEXT: xvcvspdp vs0, vs0 103; CHECK-P8-NEXT: xvcvspdp vs1, vs1 104; CHECK-P8-NEXT: xvcvspdp vs3, vs3 105; CHECK-P8-NEXT: xvcvdpuxds v4, vs2 106; CHECK-P8-NEXT: xvcvdpuxds v2, vs0 107; CHECK-P8-NEXT: xvcvdpuxds v3, vs1 108; CHECK-P8-NEXT: xvcvdpuxds v5, vs3 109; CHECK-P8-NEXT: xxswapd vs3, v4 110; CHECK-P8-NEXT: xxswapd vs1, v2 111; CHECK-P8-NEXT: xxswapd vs0, v3 112; CHECK-P8-NEXT: xxswapd vs2, v5 113; CHECK-P8-NEXT: stxvd2x vs0, r3, r4 114; CHECK-P8-NEXT: stxvd2x vs1, r3, r6 115; CHECK-P8-NEXT: stxvd2x vs2, r3, r5 116; CHECK-P8-NEXT: stxvd2x vs3, 0, r3 117; CHECK-P8-NEXT: blr 118; 119; CHECK-P9-LABEL: test8elt: 120; CHECK-P9: # %bb.0: # %entry 121; CHECK-P9-NEXT: lxv vs0, 16(r4) 122; CHECK-P9-NEXT: lxv vs1, 0(r4) 123; CHECK-P9-NEXT: xxmrglw vs2, vs1, vs1 124; CHECK-P9-NEXT: xxmrghw vs1, vs1, vs1 125; CHECK-P9-NEXT: xxmrglw vs3, vs0, vs0 126; CHECK-P9-NEXT: xxmrghw vs0, vs0, vs0 127; CHECK-P9-NEXT: xvcvspdp vs2, vs2 128; CHECK-P9-NEXT: xvcvspdp vs1, vs1 129; CHECK-P9-NEXT: xvcvspdp vs3, vs3 130; CHECK-P9-NEXT: xvcvspdp vs0, vs0 131; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2 132; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1 133; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3 134; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0 135; CHECK-P9-NEXT: stxv vs0, 48(r3) 136; CHECK-P9-NEXT: stxv vs3, 32(r3) 137; CHECK-P9-NEXT: stxv vs1, 16(r3) 138; CHECK-P9-NEXT: stxv vs2, 0(r3) 139; CHECK-P9-NEXT: blr 140; 141; CHECK-BE-LABEL: test8elt: 142; CHECK-BE: # %bb.0: # %entry 143; CHECK-BE-NEXT: lxv vs0, 16(r4) 144; CHECK-BE-NEXT: lxv vs1, 0(r4) 145; CHECK-BE-NEXT: xxmrghw vs2, vs1, vs1 146; CHECK-BE-NEXT: xxmrglw vs1, vs1, vs1 147; CHECK-BE-NEXT: xxmrghw vs3, vs0, vs0 148; CHECK-BE-NEXT: xxmrglw vs0, vs0, vs0 149; CHECK-BE-NEXT: xvcvspdp vs2, vs2 150; CHECK-BE-NEXT: xvcvspdp vs1, vs1 151; CHECK-BE-NEXT: xvcvspdp vs3, vs3 152; CHECK-BE-NEXT: xvcvspdp vs0, vs0 153; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2 154; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1 155; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3 156; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0 157; CHECK-BE-NEXT: stxv vs0, 48(r3) 158; CHECK-BE-NEXT: stxv vs3, 32(r3) 159; CHECK-BE-NEXT: stxv vs1, 16(r3) 160; CHECK-BE-NEXT: stxv vs2, 0(r3) 161; CHECK-BE-NEXT: blr 162entry: 163 %a = load <8 x float>, <8 x float>* %0, align 32 164 %1 = fptoui <8 x float> %a to <8 x i64> 165 store <8 x i64> %1, <8 x i64>* %agg.result, align 64 166 ret void 167} 168 169define void @test16elt(<16 x i64>* noalias nocapture sret(<16 x i64>) %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #2 { 170; CHECK-P8-LABEL: test16elt: 171; CHECK-P8: # %bb.0: # %entry 172; CHECK-P8-NEXT: li r7, 48 173; CHECK-P8-NEXT: li r5, 16 174; CHECK-P8-NEXT: li r6, 32 175; CHECK-P8-NEXT: li r8, 64 176; CHECK-P8-NEXT: lvx v4, r4, r7 177; CHECK-P8-NEXT: lvx v2, r4, r5 178; CHECK-P8-NEXT: lvx v3, r4, r6 179; CHECK-P8-NEXT: xxmrghw vs3, v4, v4 180; CHECK-P8-NEXT: xxmrglw vs5, v4, v4 181; CHECK-P8-NEXT: xxmrglw vs0, v2, v2 182; CHECK-P8-NEXT: xxmrghw vs1, v2, v2 183; CHECK-P8-NEXT: lvx v2, 0, r4 184; CHECK-P8-NEXT: li r4, 112 185; CHECK-P8-NEXT: xxmrglw vs2, v3, v3 186; CHECK-P8-NEXT: xxmrghw vs4, v3, v3 187; CHECK-P8-NEXT: xvcvspdp vs3, vs3 188; CHECK-P8-NEXT: xxmrglw vs6, v2, v2 189; CHECK-P8-NEXT: xxmrghw vs7, v2, v2 190; CHECK-P8-NEXT: xvcvspdp vs5, vs5 191; CHECK-P8-NEXT: xvcvspdp vs0, vs0 192; CHECK-P8-NEXT: xvcvspdp vs1, vs1 193; CHECK-P8-NEXT: xvcvspdp vs2, vs2 194; CHECK-P8-NEXT: xvcvspdp vs4, vs4 195; CHECK-P8-NEXT: xvcvspdp vs6, vs6 196; CHECK-P8-NEXT: xvcvspdp vs7, vs7 197; CHECK-P8-NEXT: xvcvdpuxds v3, vs3 198; CHECK-P8-NEXT: xvcvdpuxds v5, vs5 199; CHECK-P8-NEXT: xvcvdpuxds v2, vs0 200; CHECK-P8-NEXT: xvcvdpuxds v4, vs1 201; CHECK-P8-NEXT: xvcvdpuxds v0, vs4 202; CHECK-P8-NEXT: xvcvdpuxds v1, vs2 203; CHECK-P8-NEXT: xvcvdpuxds v6, vs6 204; CHECK-P8-NEXT: xxswapd vs0, v3 205; CHECK-P8-NEXT: xvcvdpuxds v7, vs7 206; CHECK-P8-NEXT: xxswapd vs1, v5 207; CHECK-P8-NEXT: xxswapd vs4, v2 208; CHECK-P8-NEXT: stxvd2x vs0, r3, r4 209; CHECK-P8-NEXT: li r4, 96 210; CHECK-P8-NEXT: xxswapd vs3, v4 211; CHECK-P8-NEXT: xxswapd vs2, v0 212; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 213; CHECK-P8-NEXT: li r4, 80 214; CHECK-P8-NEXT: xxswapd vs0, v1 215; CHECK-P8-NEXT: xxswapd vs5, v6 216; CHECK-P8-NEXT: xxswapd vs1, v7 217; CHECK-P8-NEXT: stxvd2x vs2, r3, r4 218; CHECK-P8-NEXT: stxvd2x vs0, r3, r8 219; CHECK-P8-NEXT: stxvd2x vs3, r3, r7 220; CHECK-P8-NEXT: stxvd2x vs4, r3, r6 221; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 222; CHECK-P8-NEXT: stxvd2x vs5, 0, r3 223; CHECK-P8-NEXT: blr 224; 225; CHECK-P9-LABEL: test16elt: 226; CHECK-P9: # %bb.0: # %entry 227; CHECK-P9-NEXT: lxv vs0, 48(r4) 228; CHECK-P9-NEXT: lxv vs1, 0(r4) 229; CHECK-P9-NEXT: lxv vs3, 16(r4) 230; CHECK-P9-NEXT: lxv vs5, 32(r4) 231; CHECK-P9-NEXT: xxmrglw vs2, vs1, vs1 232; CHECK-P9-NEXT: xxmrghw vs1, vs1, vs1 233; CHECK-P9-NEXT: xxmrglw vs4, vs3, vs3 234; CHECK-P9-NEXT: xxmrghw vs3, vs3, vs3 235; CHECK-P9-NEXT: xxmrglw vs6, vs5, vs5 236; CHECK-P9-NEXT: xxmrghw vs5, vs5, vs5 237; CHECK-P9-NEXT: xxmrglw vs7, vs0, vs0 238; CHECK-P9-NEXT: xxmrghw vs0, vs0, vs0 239; CHECK-P9-NEXT: xvcvspdp vs2, vs2 240; CHECK-P9-NEXT: xvcvspdp vs1, vs1 241; CHECK-P9-NEXT: xvcvspdp vs4, vs4 242; CHECK-P9-NEXT: xvcvspdp vs3, vs3 243; CHECK-P9-NEXT: xvcvspdp vs6, vs6 244; CHECK-P9-NEXT: xvcvspdp vs5, vs5 245; CHECK-P9-NEXT: xvcvspdp vs7, vs7 246; CHECK-P9-NEXT: xvcvspdp vs0, vs0 247; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2 248; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1 249; CHECK-P9-NEXT: xvcvdpuxds vs4, vs4 250; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3 251; CHECK-P9-NEXT: xvcvdpuxds vs6, vs6 252; CHECK-P9-NEXT: xvcvdpuxds vs5, vs5 253; CHECK-P9-NEXT: xvcvdpuxds vs7, vs7 254; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0 255; CHECK-P9-NEXT: stxv vs0, 112(r3) 256; CHECK-P9-NEXT: stxv vs7, 96(r3) 257; CHECK-P9-NEXT: stxv vs5, 80(r3) 258; CHECK-P9-NEXT: stxv vs6, 64(r3) 259; CHECK-P9-NEXT: stxv vs3, 48(r3) 260; CHECK-P9-NEXT: stxv vs4, 32(r3) 261; CHECK-P9-NEXT: stxv vs1, 16(r3) 262; CHECK-P9-NEXT: stxv vs2, 0(r3) 263; CHECK-P9-NEXT: blr 264; 265; CHECK-BE-LABEL: test16elt: 266; CHECK-BE: # %bb.0: # %entry 267; CHECK-BE-NEXT: lxv vs0, 48(r4) 268; CHECK-BE-NEXT: lxv vs1, 0(r4) 269; CHECK-BE-NEXT: lxv vs3, 16(r4) 270; CHECK-BE-NEXT: lxv vs5, 32(r4) 271; CHECK-BE-NEXT: xxmrghw vs2, vs1, vs1 272; CHECK-BE-NEXT: xxmrglw vs1, vs1, vs1 273; CHECK-BE-NEXT: xxmrghw vs4, vs3, vs3 274; CHECK-BE-NEXT: xxmrglw vs3, vs3, vs3 275; CHECK-BE-NEXT: xxmrghw vs6, vs5, vs5 276; CHECK-BE-NEXT: xxmrglw vs5, vs5, vs5 277; CHECK-BE-NEXT: xxmrghw vs7, vs0, vs0 278; CHECK-BE-NEXT: xxmrglw vs0, vs0, vs0 279; CHECK-BE-NEXT: xvcvspdp vs2, vs2 280; CHECK-BE-NEXT: xvcvspdp vs1, vs1 281; CHECK-BE-NEXT: xvcvspdp vs4, vs4 282; CHECK-BE-NEXT: xvcvspdp vs3, vs3 283; CHECK-BE-NEXT: xvcvspdp vs6, vs6 284; CHECK-BE-NEXT: xvcvspdp vs5, vs5 285; CHECK-BE-NEXT: xvcvspdp vs7, vs7 286; CHECK-BE-NEXT: xvcvspdp vs0, vs0 287; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2 288; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1 289; CHECK-BE-NEXT: xvcvdpuxds vs4, vs4 290; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3 291; CHECK-BE-NEXT: xvcvdpuxds vs6, vs6 292; CHECK-BE-NEXT: xvcvdpuxds vs5, vs5 293; CHECK-BE-NEXT: xvcvdpuxds vs7, vs7 294; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0 295; CHECK-BE-NEXT: stxv vs0, 112(r3) 296; CHECK-BE-NEXT: stxv vs7, 96(r3) 297; CHECK-BE-NEXT: stxv vs5, 80(r3) 298; CHECK-BE-NEXT: stxv vs6, 64(r3) 299; CHECK-BE-NEXT: stxv vs3, 48(r3) 300; CHECK-BE-NEXT: stxv vs4, 32(r3) 301; CHECK-BE-NEXT: stxv vs1, 16(r3) 302; CHECK-BE-NEXT: stxv vs2, 0(r3) 303; CHECK-BE-NEXT: blr 304entry: 305 %a = load <16 x float>, <16 x float>* %0, align 64 306 %1 = fptoui <16 x float> %a to <16 x i64> 307 store <16 x i64> %1, <16 x i64>* %agg.result, align 128 308 ret void 309} 310 311define <2 x i64> @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 { 312; CHECK-P8-LABEL: test2elt_signed: 313; CHECK-P8: # %bb.0: # %entry 314; CHECK-P8-NEXT: mtfprd f0, r3 315; CHECK-P8-NEXT: xxswapd v2, vs0 316; CHECK-P8-NEXT: xxmrglw vs0, v2, v2 317; CHECK-P8-NEXT: xvcvspdp vs0, vs0 318; CHECK-P8-NEXT: xvcvdpuxds v2, vs0 319; CHECK-P8-NEXT: blr 320; 321; CHECK-P9-LABEL: test2elt_signed: 322; CHECK-P9: # %bb.0: # %entry 323; CHECK-P9-NEXT: mtfprd f0, r3 324; CHECK-P9-NEXT: xxswapd v2, vs0 325; CHECK-P9-NEXT: xxmrglw vs0, v2, v2 326; CHECK-P9-NEXT: xvcvspdp vs0, vs0 327; CHECK-P9-NEXT: xvcvdpuxds v2, vs0 328; CHECK-P9-NEXT: blr 329; 330; CHECK-BE-LABEL: test2elt_signed: 331; CHECK-BE: # %bb.0: # %entry 332; CHECK-BE-NEXT: mtfprd f0, r3 333; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs0 334; CHECK-BE-NEXT: xvcvspdp vs0, vs0 335; CHECK-BE-NEXT: xvcvdpuxds v2, vs0 336; CHECK-BE-NEXT: blr 337entry: 338 %0 = bitcast i64 %a.coerce to <2 x float> 339 %1 = fptoui <2 x float> %0 to <2 x i64> 340 ret <2 x i64> %1 341} 342 343define void @test4elt_signed(<4 x i64>* noalias nocapture sret(<4 x i64>) %agg.result, <4 x float> %a) local_unnamed_addr #1 { 344; CHECK-P8-LABEL: test4elt_signed: 345; CHECK-P8: # %bb.0: # %entry 346; CHECK-P8-NEXT: xxmrglw vs0, v2, v2 347; CHECK-P8-NEXT: xxmrghw vs1, v2, v2 348; CHECK-P8-NEXT: li r4, 16 349; CHECK-P8-NEXT: xvcvspdp vs0, vs0 350; CHECK-P8-NEXT: xvcvspdp vs1, vs1 351; CHECK-P8-NEXT: xvcvdpuxds v2, vs0 352; CHECK-P8-NEXT: xvcvdpuxds v3, vs1 353; CHECK-P8-NEXT: xxswapd vs1, v2 354; CHECK-P8-NEXT: xxswapd vs0, v3 355; CHECK-P8-NEXT: stxvd2x vs0, r3, r4 356; CHECK-P8-NEXT: stxvd2x vs1, 0, r3 357; CHECK-P8-NEXT: blr 358; 359; CHECK-P9-LABEL: test4elt_signed: 360; CHECK-P9: # %bb.0: # %entry 361; CHECK-P9-NEXT: xxmrglw vs0, v2, v2 362; CHECK-P9-NEXT: xxmrghw vs1, v2, v2 363; CHECK-P9-NEXT: xvcvspdp vs0, vs0 364; CHECK-P9-NEXT: xvcvspdp vs1, vs1 365; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0 366; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1 367; CHECK-P9-NEXT: stxv vs1, 16(r3) 368; CHECK-P9-NEXT: stxv vs0, 0(r3) 369; CHECK-P9-NEXT: blr 370; 371; CHECK-BE-LABEL: test4elt_signed: 372; CHECK-BE: # %bb.0: # %entry 373; CHECK-BE-NEXT: xxmrghw vs0, v2, v2 374; CHECK-BE-NEXT: xxmrglw vs1, v2, v2 375; CHECK-BE-NEXT: xvcvspdp vs0, vs0 376; CHECK-BE-NEXT: xvcvspdp vs1, vs1 377; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0 378; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1 379; CHECK-BE-NEXT: stxv vs1, 16(r3) 380; CHECK-BE-NEXT: stxv vs0, 0(r3) 381; CHECK-BE-NEXT: blr 382entry: 383 %0 = fptoui <4 x float> %a to <4 x i64> 384 store <4 x i64> %0, <4 x i64>* %agg.result, align 32 385 ret void 386} 387 388define void @test8elt_signed(<8 x i64>* noalias nocapture sret(<8 x i64>) %agg.result, <8 x float>* nocapture readonly) local_unnamed_addr #2 { 389; CHECK-P8-LABEL: test8elt_signed: 390; CHECK-P8: # %bb.0: # %entry 391; CHECK-P8-NEXT: li r5, 16 392; CHECK-P8-NEXT: lvx v3, 0, r4 393; CHECK-P8-NEXT: li r6, 32 394; CHECK-P8-NEXT: lvx v2, r4, r5 395; CHECK-P8-NEXT: li r4, 48 396; CHECK-P8-NEXT: xxmrglw vs2, v3, v3 397; CHECK-P8-NEXT: xxmrghw vs3, v3, v3 398; CHECK-P8-NEXT: xxmrglw vs0, v2, v2 399; CHECK-P8-NEXT: xxmrghw vs1, v2, v2 400; CHECK-P8-NEXT: xvcvspdp vs2, vs2 401; CHECK-P8-NEXT: xvcvspdp vs0, vs0 402; CHECK-P8-NEXT: xvcvspdp vs1, vs1 403; CHECK-P8-NEXT: xvcvspdp vs3, vs3 404; CHECK-P8-NEXT: xvcvdpuxds v4, vs2 405; CHECK-P8-NEXT: xvcvdpuxds v2, vs0 406; CHECK-P8-NEXT: xvcvdpuxds v3, vs1 407; CHECK-P8-NEXT: xvcvdpuxds v5, vs3 408; CHECK-P8-NEXT: xxswapd vs3, v4 409; CHECK-P8-NEXT: xxswapd vs1, v2 410; CHECK-P8-NEXT: xxswapd vs0, v3 411; CHECK-P8-NEXT: xxswapd vs2, v5 412; CHECK-P8-NEXT: stxvd2x vs0, r3, r4 413; CHECK-P8-NEXT: stxvd2x vs1, r3, r6 414; CHECK-P8-NEXT: stxvd2x vs2, r3, r5 415; CHECK-P8-NEXT: stxvd2x vs3, 0, r3 416; CHECK-P8-NEXT: blr 417; 418; CHECK-P9-LABEL: test8elt_signed: 419; CHECK-P9: # %bb.0: # %entry 420; CHECK-P9-NEXT: lxv vs0, 16(r4) 421; CHECK-P9-NEXT: lxv vs1, 0(r4) 422; CHECK-P9-NEXT: xxmrglw vs2, vs1, vs1 423; CHECK-P9-NEXT: xxmrghw vs1, vs1, vs1 424; CHECK-P9-NEXT: xxmrglw vs3, vs0, vs0 425; CHECK-P9-NEXT: xxmrghw vs0, vs0, vs0 426; CHECK-P9-NEXT: xvcvspdp vs2, vs2 427; CHECK-P9-NEXT: xvcvspdp vs1, vs1 428; CHECK-P9-NEXT: xvcvspdp vs3, vs3 429; CHECK-P9-NEXT: xvcvspdp vs0, vs0 430; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2 431; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1 432; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3 433; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0 434; CHECK-P9-NEXT: stxv vs0, 48(r3) 435; CHECK-P9-NEXT: stxv vs3, 32(r3) 436; CHECK-P9-NEXT: stxv vs1, 16(r3) 437; CHECK-P9-NEXT: stxv vs2, 0(r3) 438; CHECK-P9-NEXT: blr 439; 440; CHECK-BE-LABEL: test8elt_signed: 441; CHECK-BE: # %bb.0: # %entry 442; CHECK-BE-NEXT: lxv vs0, 16(r4) 443; CHECK-BE-NEXT: lxv vs1, 0(r4) 444; CHECK-BE-NEXT: xxmrghw vs2, vs1, vs1 445; CHECK-BE-NEXT: xxmrglw vs1, vs1, vs1 446; CHECK-BE-NEXT: xxmrghw vs3, vs0, vs0 447; CHECK-BE-NEXT: xxmrglw vs0, vs0, vs0 448; CHECK-BE-NEXT: xvcvspdp vs2, vs2 449; CHECK-BE-NEXT: xvcvspdp vs1, vs1 450; CHECK-BE-NEXT: xvcvspdp vs3, vs3 451; CHECK-BE-NEXT: xvcvspdp vs0, vs0 452; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2 453; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1 454; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3 455; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0 456; CHECK-BE-NEXT: stxv vs0, 48(r3) 457; CHECK-BE-NEXT: stxv vs3, 32(r3) 458; CHECK-BE-NEXT: stxv vs1, 16(r3) 459; CHECK-BE-NEXT: stxv vs2, 0(r3) 460; CHECK-BE-NEXT: blr 461entry: 462 %a = load <8 x float>, <8 x float>* %0, align 32 463 %1 = fptoui <8 x float> %a to <8 x i64> 464 store <8 x i64> %1, <8 x i64>* %agg.result, align 64 465 ret void 466} 467 468define void @test16elt_signed(<16 x i64>* noalias nocapture sret(<16 x i64>) %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #2 { 469; CHECK-P8-LABEL: test16elt_signed: 470; CHECK-P8: # %bb.0: # %entry 471; CHECK-P8-NEXT: li r7, 48 472; CHECK-P8-NEXT: li r5, 16 473; CHECK-P8-NEXT: li r6, 32 474; CHECK-P8-NEXT: li r8, 64 475; CHECK-P8-NEXT: lvx v4, r4, r7 476; CHECK-P8-NEXT: lvx v2, r4, r5 477; CHECK-P8-NEXT: lvx v3, r4, r6 478; CHECK-P8-NEXT: xxmrghw vs3, v4, v4 479; CHECK-P8-NEXT: xxmrglw vs5, v4, v4 480; CHECK-P8-NEXT: xxmrglw vs0, v2, v2 481; CHECK-P8-NEXT: xxmrghw vs1, v2, v2 482; CHECK-P8-NEXT: lvx v2, 0, r4 483; CHECK-P8-NEXT: li r4, 112 484; CHECK-P8-NEXT: xxmrglw vs2, v3, v3 485; CHECK-P8-NEXT: xxmrghw vs4, v3, v3 486; CHECK-P8-NEXT: xvcvspdp vs3, vs3 487; CHECK-P8-NEXT: xxmrglw vs6, v2, v2 488; CHECK-P8-NEXT: xxmrghw vs7, v2, v2 489; CHECK-P8-NEXT: xvcvspdp vs5, vs5 490; CHECK-P8-NEXT: xvcvspdp vs0, vs0 491; CHECK-P8-NEXT: xvcvspdp vs1, vs1 492; CHECK-P8-NEXT: xvcvspdp vs2, vs2 493; CHECK-P8-NEXT: xvcvspdp vs4, vs4 494; CHECK-P8-NEXT: xvcvspdp vs6, vs6 495; CHECK-P8-NEXT: xvcvspdp vs7, vs7 496; CHECK-P8-NEXT: xvcvdpuxds v3, vs3 497; CHECK-P8-NEXT: xvcvdpuxds v5, vs5 498; CHECK-P8-NEXT: xvcvdpuxds v2, vs0 499; CHECK-P8-NEXT: xvcvdpuxds v4, vs1 500; CHECK-P8-NEXT: xvcvdpuxds v0, vs4 501; CHECK-P8-NEXT: xvcvdpuxds v1, vs2 502; CHECK-P8-NEXT: xvcvdpuxds v6, vs6 503; CHECK-P8-NEXT: xxswapd vs0, v3 504; CHECK-P8-NEXT: xvcvdpuxds v7, vs7 505; CHECK-P8-NEXT: xxswapd vs1, v5 506; CHECK-P8-NEXT: xxswapd vs4, v2 507; CHECK-P8-NEXT: stxvd2x vs0, r3, r4 508; CHECK-P8-NEXT: li r4, 96 509; CHECK-P8-NEXT: xxswapd vs3, v4 510; CHECK-P8-NEXT: xxswapd vs2, v0 511; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 512; CHECK-P8-NEXT: li r4, 80 513; CHECK-P8-NEXT: xxswapd vs0, v1 514; CHECK-P8-NEXT: xxswapd vs5, v6 515; CHECK-P8-NEXT: xxswapd vs1, v7 516; CHECK-P8-NEXT: stxvd2x vs2, r3, r4 517; CHECK-P8-NEXT: stxvd2x vs0, r3, r8 518; CHECK-P8-NEXT: stxvd2x vs3, r3, r7 519; CHECK-P8-NEXT: stxvd2x vs4, r3, r6 520; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 521; CHECK-P8-NEXT: stxvd2x vs5, 0, r3 522; CHECK-P8-NEXT: blr 523; 524; CHECK-P9-LABEL: test16elt_signed: 525; CHECK-P9: # %bb.0: # %entry 526; CHECK-P9-NEXT: lxv vs0, 48(r4) 527; CHECK-P9-NEXT: lxv vs1, 0(r4) 528; CHECK-P9-NEXT: lxv vs3, 16(r4) 529; CHECK-P9-NEXT: lxv vs5, 32(r4) 530; CHECK-P9-NEXT: xxmrglw vs2, vs1, vs1 531; CHECK-P9-NEXT: xxmrghw vs1, vs1, vs1 532; CHECK-P9-NEXT: xxmrglw vs4, vs3, vs3 533; CHECK-P9-NEXT: xxmrghw vs3, vs3, vs3 534; CHECK-P9-NEXT: xxmrglw vs6, vs5, vs5 535; CHECK-P9-NEXT: xxmrghw vs5, vs5, vs5 536; CHECK-P9-NEXT: xxmrglw vs7, vs0, vs0 537; CHECK-P9-NEXT: xxmrghw vs0, vs0, vs0 538; CHECK-P9-NEXT: xvcvspdp vs2, vs2 539; CHECK-P9-NEXT: xvcvspdp vs1, vs1 540; CHECK-P9-NEXT: xvcvspdp vs4, vs4 541; CHECK-P9-NEXT: xvcvspdp vs3, vs3 542; CHECK-P9-NEXT: xvcvspdp vs6, vs6 543; CHECK-P9-NEXT: xvcvspdp vs5, vs5 544; CHECK-P9-NEXT: xvcvspdp vs7, vs7 545; CHECK-P9-NEXT: xvcvspdp vs0, vs0 546; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2 547; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1 548; CHECK-P9-NEXT: xvcvdpuxds vs4, vs4 549; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3 550; CHECK-P9-NEXT: xvcvdpuxds vs6, vs6 551; CHECK-P9-NEXT: xvcvdpuxds vs5, vs5 552; CHECK-P9-NEXT: xvcvdpuxds vs7, vs7 553; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0 554; CHECK-P9-NEXT: stxv vs0, 112(r3) 555; CHECK-P9-NEXT: stxv vs7, 96(r3) 556; CHECK-P9-NEXT: stxv vs5, 80(r3) 557; CHECK-P9-NEXT: stxv vs6, 64(r3) 558; CHECK-P9-NEXT: stxv vs3, 48(r3) 559; CHECK-P9-NEXT: stxv vs4, 32(r3) 560; CHECK-P9-NEXT: stxv vs1, 16(r3) 561; CHECK-P9-NEXT: stxv vs2, 0(r3) 562; CHECK-P9-NEXT: blr 563; 564; CHECK-BE-LABEL: test16elt_signed: 565; CHECK-BE: # %bb.0: # %entry 566; CHECK-BE-NEXT: lxv vs0, 48(r4) 567; CHECK-BE-NEXT: lxv vs1, 0(r4) 568; CHECK-BE-NEXT: lxv vs3, 16(r4) 569; CHECK-BE-NEXT: lxv vs5, 32(r4) 570; CHECK-BE-NEXT: xxmrghw vs2, vs1, vs1 571; CHECK-BE-NEXT: xxmrglw vs1, vs1, vs1 572; CHECK-BE-NEXT: xxmrghw vs4, vs3, vs3 573; CHECK-BE-NEXT: xxmrglw vs3, vs3, vs3 574; CHECK-BE-NEXT: xxmrghw vs6, vs5, vs5 575; CHECK-BE-NEXT: xxmrglw vs5, vs5, vs5 576; CHECK-BE-NEXT: xxmrghw vs7, vs0, vs0 577; CHECK-BE-NEXT: xxmrglw vs0, vs0, vs0 578; CHECK-BE-NEXT: xvcvspdp vs2, vs2 579; CHECK-BE-NEXT: xvcvspdp vs1, vs1 580; CHECK-BE-NEXT: xvcvspdp vs4, vs4 581; CHECK-BE-NEXT: xvcvspdp vs3, vs3 582; CHECK-BE-NEXT: xvcvspdp vs6, vs6 583; CHECK-BE-NEXT: xvcvspdp vs5, vs5 584; CHECK-BE-NEXT: xvcvspdp vs7, vs7 585; CHECK-BE-NEXT: xvcvspdp vs0, vs0 586; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2 587; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1 588; CHECK-BE-NEXT: xvcvdpuxds vs4, vs4 589; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3 590; CHECK-BE-NEXT: xvcvdpuxds vs6, vs6 591; CHECK-BE-NEXT: xvcvdpuxds vs5, vs5 592; CHECK-BE-NEXT: xvcvdpuxds vs7, vs7 593; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0 594; CHECK-BE-NEXT: stxv vs0, 112(r3) 595; CHECK-BE-NEXT: stxv vs7, 96(r3) 596; CHECK-BE-NEXT: stxv vs5, 80(r3) 597; CHECK-BE-NEXT: stxv vs6, 64(r3) 598; CHECK-BE-NEXT: stxv vs3, 48(r3) 599; CHECK-BE-NEXT: stxv vs4, 32(r3) 600; CHECK-BE-NEXT: stxv vs1, 16(r3) 601; CHECK-BE-NEXT: stxv vs2, 0(r3) 602; CHECK-BE-NEXT: blr 603entry: 604 %a = load <16 x float>, <16 x float>* %0, align 64 605 %1 = fptoui <16 x float> %a to <16 x i64> 606 store <16 x i64> %1, <16 x i64>* %agg.result, align 128 607 ret void 608} 609