1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3; RUN:     -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4; RUN: FileCheck %s --check-prefix=CHECK-P8
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
6; RUN:     -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
7; RUN: FileCheck %s --check-prefix=CHECK-P9
8; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
9; RUN:     -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
10; RUN: FileCheck %s --check-prefix=CHECK-BE
11
12define <2 x double> @test2elt(i16 %a.coerce) local_unnamed_addr #0 {
13; CHECK-P8-LABEL: test2elt:
14; CHECK-P8:       # %bb.0: # %entry
15; CHECK-P8-NEXT:    addis r4, r2, .LCPI0_0@toc@ha
16; CHECK-P8-NEXT:    mtvsrwz v2, r3
17; CHECK-P8-NEXT:    addi r4, r4, .LCPI0_0@toc@l
18; CHECK-P8-NEXT:    xxlxor v4, v4, v4
19; CHECK-P8-NEXT:    lvx v3, 0, r4
20; CHECK-P8-NEXT:    vperm v2, v4, v2, v3
21; CHECK-P8-NEXT:    xvcvuxddp v2, v2
22; CHECK-P8-NEXT:    blr
23;
24; CHECK-P9-LABEL: test2elt:
25; CHECK-P9:       # %bb.0: # %entry
26; CHECK-P9-NEXT:    mtvsrws v2, r3
27; CHECK-P9-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
28; CHECK-P9-NEXT:    xxlxor v4, v4, v4
29; CHECK-P9-NEXT:    addi r3, r3, .LCPI0_0@toc@l
30; CHECK-P9-NEXT:    lxvx v3, 0, r3
31; CHECK-P9-NEXT:    vperm v2, v4, v2, v3
32; CHECK-P9-NEXT:    xvcvuxddp v2, v2
33; CHECK-P9-NEXT:    blr
34;
35; CHECK-BE-LABEL: test2elt:
36; CHECK-BE:       # %bb.0: # %entry
37; CHECK-BE-NEXT:    mtvsrws v2, r3
38; CHECK-BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
39; CHECK-BE-NEXT:    xxlxor v4, v4, v4
40; CHECK-BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
41; CHECK-BE-NEXT:    lxvx v3, 0, r3
42; CHECK-BE-NEXT:    vperm v2, v2, v4, v3
43; CHECK-BE-NEXT:    xvcvuxddp v2, v2
44; CHECK-BE-NEXT:    blr
45entry:
46  %0 = bitcast i16 %a.coerce to <2 x i8>
47  %1 = uitofp <2 x i8> %0 to <2 x double>
48  ret <2 x double> %1
49}
50
51define void @test4elt(<4 x double>* noalias nocapture sret(<4 x double>) %agg.result, i32 %a.coerce) local_unnamed_addr #1 {
52; CHECK-P8-LABEL: test4elt:
53; CHECK-P8:       # %bb.0: # %entry
54; CHECK-P8-NEXT:    addis r5, r2, .LCPI1_0@toc@ha
55; CHECK-P8-NEXT:    addis r6, r2, .LCPI1_1@toc@ha
56; CHECK-P8-NEXT:    mtvsrwz v2, r4
57; CHECK-P8-NEXT:    addi r5, r5, .LCPI1_0@toc@l
58; CHECK-P8-NEXT:    addi r4, r6, .LCPI1_1@toc@l
59; CHECK-P8-NEXT:    xxlxor v4, v4, v4
60; CHECK-P8-NEXT:    lvx v3, 0, r5
61; CHECK-P8-NEXT:    lvx v5, 0, r4
62; CHECK-P8-NEXT:    li r4, 16
63; CHECK-P8-NEXT:    vperm v3, v4, v2, v3
64; CHECK-P8-NEXT:    vperm v2, v4, v2, v5
65; CHECK-P8-NEXT:    xvcvuxddp vs0, v3
66; CHECK-P8-NEXT:    xvcvuxddp vs1, v2
67; CHECK-P8-NEXT:    xxswapd vs0, vs0
68; CHECK-P8-NEXT:    xxswapd vs1, vs1
69; CHECK-P8-NEXT:    stxvd2x vs1, r3, r4
70; CHECK-P8-NEXT:    stxvd2x vs0, 0, r3
71; CHECK-P8-NEXT:    blr
72;
73; CHECK-P9-LABEL: test4elt:
74; CHECK-P9:       # %bb.0: # %entry
75; CHECK-P9-NEXT:    mtvsrws v2, r4
76; CHECK-P9-NEXT:    addis r4, r2, .LCPI1_0@toc@ha
77; CHECK-P9-NEXT:    xxlxor v4, v4, v4
78; CHECK-P9-NEXT:    addi r4, r4, .LCPI1_0@toc@l
79; CHECK-P9-NEXT:    lxvx v3, 0, r4
80; CHECK-P9-NEXT:    addis r4, r2, .LCPI1_1@toc@ha
81; CHECK-P9-NEXT:    addi r4, r4, .LCPI1_1@toc@l
82; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
83; CHECK-P9-NEXT:    xvcvuxddp vs0, v3
84; CHECK-P9-NEXT:    lxvx v3, 0, r4
85; CHECK-P9-NEXT:    vperm v2, v4, v2, v3
86; CHECK-P9-NEXT:    stxv vs0, 0(r3)
87; CHECK-P9-NEXT:    xvcvuxddp vs1, v2
88; CHECK-P9-NEXT:    stxv vs1, 16(r3)
89; CHECK-P9-NEXT:    blr
90;
91; CHECK-BE-LABEL: test4elt:
92; CHECK-BE:       # %bb.0: # %entry
93; CHECK-BE-NEXT:    mtvsrws v2, r4
94; CHECK-BE-NEXT:    addis r4, r2, .LCPI1_0@toc@ha
95; CHECK-BE-NEXT:    xxlxor v4, v4, v4
96; CHECK-BE-NEXT:    addi r4, r4, .LCPI1_0@toc@l
97; CHECK-BE-NEXT:    lxvx v3, 0, r4
98; CHECK-BE-NEXT:    addis r4, r2, .LCPI1_1@toc@ha
99; CHECK-BE-NEXT:    addi r4, r4, .LCPI1_1@toc@l
100; CHECK-BE-NEXT:    vperm v3, v2, v4, v3
101; CHECK-BE-NEXT:    xvcvuxddp vs0, v3
102; CHECK-BE-NEXT:    lxvx v3, 0, r4
103; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
104; CHECK-BE-NEXT:    stxv vs0, 0(r3)
105; CHECK-BE-NEXT:    xvcvuxddp vs1, v2
106; CHECK-BE-NEXT:    stxv vs1, 16(r3)
107; CHECK-BE-NEXT:    blr
108entry:
109  %0 = bitcast i32 %a.coerce to <4 x i8>
110  %1 = uitofp <4 x i8> %0 to <4 x double>
111  store <4 x double> %1, <4 x double>* %agg.result, align 32
112  ret void
113}
114
115define void @test8elt(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 {
116; CHECK-P8-LABEL: test8elt:
117; CHECK-P8:       # %bb.0: # %entry
118; CHECK-P8-NEXT:    addis r5, r2, .LCPI2_0@toc@ha
119; CHECK-P8-NEXT:    addis r6, r2, .LCPI2_2@toc@ha
120; CHECK-P8-NEXT:    mtvsrd v2, r4
121; CHECK-P8-NEXT:    addis r4, r2, .LCPI2_3@toc@ha
122; CHECK-P8-NEXT:    addi r5, r5, .LCPI2_0@toc@l
123; CHECK-P8-NEXT:    addi r4, r4, .LCPI2_3@toc@l
124; CHECK-P8-NEXT:    xxlxor v4, v4, v4
125; CHECK-P8-NEXT:    lvx v3, 0, r5
126; CHECK-P8-NEXT:    addi r5, r6, .LCPI2_2@toc@l
127; CHECK-P8-NEXT:    lvx v0, 0, r4
128; CHECK-P8-NEXT:    li r4, 48
129; CHECK-P8-NEXT:    lvx v5, 0, r5
130; CHECK-P8-NEXT:    addis r5, r2, .LCPI2_1@toc@ha
131; CHECK-P8-NEXT:    addi r5, r5, .LCPI2_1@toc@l
132; CHECK-P8-NEXT:    lvx v1, 0, r5
133; CHECK-P8-NEXT:    vperm v0, v4, v2, v0
134; CHECK-P8-NEXT:    li r5, 32
135; CHECK-P8-NEXT:    vperm v3, v4, v2, v3
136; CHECK-P8-NEXT:    vperm v5, v4, v2, v5
137; CHECK-P8-NEXT:    vperm v2, v4, v2, v1
138; CHECK-P8-NEXT:    xvcvuxddp vs2, v0
139; CHECK-P8-NEXT:    xvcvuxddp vs0, v3
140; CHECK-P8-NEXT:    xvcvuxddp vs1, v5
141; CHECK-P8-NEXT:    xvcvuxddp vs3, v2
142; CHECK-P8-NEXT:    xxswapd vs2, vs2
143; CHECK-P8-NEXT:    xxswapd vs0, vs0
144; CHECK-P8-NEXT:    xxswapd vs1, vs1
145; CHECK-P8-NEXT:    xxswapd vs3, vs3
146; CHECK-P8-NEXT:    stxvd2x vs2, r3, r4
147; CHECK-P8-NEXT:    li r4, 16
148; CHECK-P8-NEXT:    stxvd2x vs1, r3, r5
149; CHECK-P8-NEXT:    stxvd2x vs3, r3, r4
150; CHECK-P8-NEXT:    stxvd2x vs0, 0, r3
151; CHECK-P8-NEXT:    blr
152;
153; CHECK-P9-LABEL: test8elt:
154; CHECK-P9:       # %bb.0: # %entry
155; CHECK-P9-NEXT:    mtvsrd v2, r4
156; CHECK-P9-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
157; CHECK-P9-NEXT:    xxlxor v4, v4, v4
158; CHECK-P9-NEXT:    addi r4, r4, .LCPI2_0@toc@l
159; CHECK-P9-NEXT:    lxvx v3, 0, r4
160; CHECK-P9-NEXT:    addis r4, r2, .LCPI2_1@toc@ha
161; CHECK-P9-NEXT:    addi r4, r4, .LCPI2_1@toc@l
162; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
163; CHECK-P9-NEXT:    xvcvuxddp vs0, v3
164; CHECK-P9-NEXT:    lxvx v3, 0, r4
165; CHECK-P9-NEXT:    addis r4, r2, .LCPI2_2@toc@ha
166; CHECK-P9-NEXT:    addi r4, r4, .LCPI2_2@toc@l
167; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
168; CHECK-P9-NEXT:    stxv vs0, 0(r3)
169; CHECK-P9-NEXT:    xvcvuxddp vs1, v3
170; CHECK-P9-NEXT:    lxvx v3, 0, r4
171; CHECK-P9-NEXT:    addis r4, r2, .LCPI2_3@toc@ha
172; CHECK-P9-NEXT:    addi r4, r4, .LCPI2_3@toc@l
173; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
174; CHECK-P9-NEXT:    stxv vs1, 16(r3)
175; CHECK-P9-NEXT:    xvcvuxddp vs2, v3
176; CHECK-P9-NEXT:    lxvx v3, 0, r4
177; CHECK-P9-NEXT:    vperm v2, v4, v2, v3
178; CHECK-P9-NEXT:    stxv vs2, 32(r3)
179; CHECK-P9-NEXT:    xvcvuxddp vs3, v2
180; CHECK-P9-NEXT:    stxv vs3, 48(r3)
181; CHECK-P9-NEXT:    blr
182;
183; CHECK-BE-LABEL: test8elt:
184; CHECK-BE:       # %bb.0: # %entry
185; CHECK-BE-NEXT:    mtvsrd v2, r4
186; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
187; CHECK-BE-NEXT:    xxlxor v4, v4, v4
188; CHECK-BE-NEXT:    addi r4, r4, .LCPI2_0@toc@l
189; CHECK-BE-NEXT:    lxvx v3, 0, r4
190; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_1@toc@ha
191; CHECK-BE-NEXT:    addi r4, r4, .LCPI2_1@toc@l
192; CHECK-BE-NEXT:    vperm v3, v2, v4, v3
193; CHECK-BE-NEXT:    xvcvuxddp vs0, v3
194; CHECK-BE-NEXT:    lxvx v3, 0, r4
195; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_2@toc@ha
196; CHECK-BE-NEXT:    addi r4, r4, .LCPI2_2@toc@l
197; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
198; CHECK-BE-NEXT:    stxv vs0, 0(r3)
199; CHECK-BE-NEXT:    xvcvuxddp vs1, v3
200; CHECK-BE-NEXT:    lxvx v3, 0, r4
201; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_3@toc@ha
202; CHECK-BE-NEXT:    addi r4, r4, .LCPI2_3@toc@l
203; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
204; CHECK-BE-NEXT:    stxv vs1, 16(r3)
205; CHECK-BE-NEXT:    xvcvuxddp vs2, v3
206; CHECK-BE-NEXT:    lxvx v3, 0, r4
207; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
208; CHECK-BE-NEXT:    stxv vs2, 32(r3)
209; CHECK-BE-NEXT:    xvcvuxddp vs3, v2
210; CHECK-BE-NEXT:    stxv vs3, 48(r3)
211; CHECK-BE-NEXT:    blr
212entry:
213  %0 = bitcast i64 %a.coerce to <8 x i8>
214  %1 = uitofp <8 x i8> %0 to <8 x double>
215  store <8 x double> %1, <8 x double>* %agg.result, align 64
216  ret void
217}
218
219define void @test16elt(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i8> %a) local_unnamed_addr #2 {
220; CHECK-P8-LABEL: test16elt:
221; CHECK-P8:       # %bb.0: # %entry
222; CHECK-P8-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
223; CHECK-P8-NEXT:    addis r5, r2, .LCPI3_1@toc@ha
224; CHECK-P8-NEXT:    xxlxor v4, v4, v4
225; CHECK-P8-NEXT:    addi r4, r4, .LCPI3_0@toc@l
226; CHECK-P8-NEXT:    addi r5, r5, .LCPI3_1@toc@l
227; CHECK-P8-NEXT:    lvx v3, 0, r4
228; CHECK-P8-NEXT:    addis r4, r2, .LCPI3_2@toc@ha
229; CHECK-P8-NEXT:    lvx v5, 0, r5
230; CHECK-P8-NEXT:    addis r5, r2, .LCPI3_4@toc@ha
231; CHECK-P8-NEXT:    addi r4, r4, .LCPI3_2@toc@l
232; CHECK-P8-NEXT:    addi r5, r5, .LCPI3_4@toc@l
233; CHECK-P8-NEXT:    lvx v0, 0, r4
234; CHECK-P8-NEXT:    addis r4, r2, .LCPI3_6@toc@ha
235; CHECK-P8-NEXT:    lvx v1, 0, r5
236; CHECK-P8-NEXT:    addis r5, r2, .LCPI3_7@toc@ha
237; CHECK-P8-NEXT:    addi r4, r4, .LCPI3_6@toc@l
238; CHECK-P8-NEXT:    addi r5, r5, .LCPI3_7@toc@l
239; CHECK-P8-NEXT:    vperm v3, v4, v2, v3
240; CHECK-P8-NEXT:    lvx v6, 0, r4
241; CHECK-P8-NEXT:    addis r4, r2, .LCPI3_5@toc@ha
242; CHECK-P8-NEXT:    lvx v7, 0, r5
243; CHECK-P8-NEXT:    addis r5, r2, .LCPI3_3@toc@ha
244; CHECK-P8-NEXT:    vperm v5, v4, v2, v5
245; CHECK-P8-NEXT:    addi r4, r4, .LCPI3_5@toc@l
246; CHECK-P8-NEXT:    addi r5, r5, .LCPI3_3@toc@l
247; CHECK-P8-NEXT:    vperm v0, v4, v2, v0
248; CHECK-P8-NEXT:    lvx v8, 0, r4
249; CHECK-P8-NEXT:    lvx v9, 0, r5
250; CHECK-P8-NEXT:    vperm v1, v4, v2, v1
251; CHECK-P8-NEXT:    li r4, 112
252; CHECK-P8-NEXT:    li r5, 96
253; CHECK-P8-NEXT:    vperm v6, v4, v2, v6
254; CHECK-P8-NEXT:    vperm v7, v4, v2, v7
255; CHECK-P8-NEXT:    vperm v8, v4, v2, v8
256; CHECK-P8-NEXT:    vperm v2, v4, v2, v9
257; CHECK-P8-NEXT:    xvcvuxddp vs0, v0
258; CHECK-P8-NEXT:    xvcvuxddp vs1, v1
259; CHECK-P8-NEXT:    xvcvuxddp vs2, v6
260; CHECK-P8-NEXT:    xvcvuxddp vs3, v7
261; CHECK-P8-NEXT:    xvcvuxddp vs4, v8
262; CHECK-P8-NEXT:    xvcvuxddp vs5, v2
263; CHECK-P8-NEXT:    xvcvuxddp vs6, v3
264; CHECK-P8-NEXT:    xxswapd vs0, vs0
265; CHECK-P8-NEXT:    xvcvuxddp vs7, v5
266; CHECK-P8-NEXT:    xxswapd vs1, vs1
267; CHECK-P8-NEXT:    xxswapd vs2, vs2
268; CHECK-P8-NEXT:    xxswapd vs3, vs3
269; CHECK-P8-NEXT:    xxswapd vs4, vs4
270; CHECK-P8-NEXT:    xxswapd vs5, vs5
271; CHECK-P8-NEXT:    stxvd2x vs3, r3, r4
272; CHECK-P8-NEXT:    stxvd2x vs2, r3, r5
273; CHECK-P8-NEXT:    li r4, 80
274; CHECK-P8-NEXT:    li r5, 64
275; CHECK-P8-NEXT:    xxswapd vs2, vs7
276; CHECK-P8-NEXT:    xxswapd vs3, vs6
277; CHECK-P8-NEXT:    stxvd2x vs4, r3, r4
278; CHECK-P8-NEXT:    li r4, 48
279; CHECK-P8-NEXT:    stxvd2x vs1, r3, r5
280; CHECK-P8-NEXT:    li r5, 32
281; CHECK-P8-NEXT:    stxvd2x vs5, r3, r4
282; CHECK-P8-NEXT:    li r4, 16
283; CHECK-P8-NEXT:    stxvd2x vs0, r3, r5
284; CHECK-P8-NEXT:    stxvd2x vs2, r3, r4
285; CHECK-P8-NEXT:    stxvd2x vs3, 0, r3
286; CHECK-P8-NEXT:    blr
287;
288; CHECK-P9-LABEL: test16elt:
289; CHECK-P9:       # %bb.0: # %entry
290; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
291; CHECK-P9-NEXT:    xxlxor v4, v4, v4
292; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_0@toc@l
293; CHECK-P9-NEXT:    lxvx v3, 0, r4
294; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_1@toc@ha
295; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_1@toc@l
296; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
297; CHECK-P9-NEXT:    xvcvuxddp vs0, v3
298; CHECK-P9-NEXT:    lxvx v3, 0, r4
299; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_2@toc@ha
300; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_2@toc@l
301; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
302; CHECK-P9-NEXT:    stxv vs0, 0(r3)
303; CHECK-P9-NEXT:    xvcvuxddp vs1, v3
304; CHECK-P9-NEXT:    lxvx v3, 0, r4
305; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_3@toc@ha
306; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_3@toc@l
307; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
308; CHECK-P9-NEXT:    stxv vs1, 16(r3)
309; CHECK-P9-NEXT:    xvcvuxddp vs2, v3
310; CHECK-P9-NEXT:    lxvx v3, 0, r4
311; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_4@toc@ha
312; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_4@toc@l
313; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
314; CHECK-P9-NEXT:    stxv vs2, 32(r3)
315; CHECK-P9-NEXT:    xvcvuxddp vs3, v3
316; CHECK-P9-NEXT:    lxvx v3, 0, r4
317; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_5@toc@ha
318; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_5@toc@l
319; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
320; CHECK-P9-NEXT:    stxv vs3, 48(r3)
321; CHECK-P9-NEXT:    xvcvuxddp vs4, v3
322; CHECK-P9-NEXT:    lxvx v3, 0, r4
323; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_6@toc@ha
324; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_6@toc@l
325; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
326; CHECK-P9-NEXT:    stxv vs4, 64(r3)
327; CHECK-P9-NEXT:    xvcvuxddp vs5, v3
328; CHECK-P9-NEXT:    lxvx v3, 0, r4
329; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_7@toc@ha
330; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_7@toc@l
331; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
332; CHECK-P9-NEXT:    stxv vs5, 80(r3)
333; CHECK-P9-NEXT:    xvcvuxddp vs6, v3
334; CHECK-P9-NEXT:    lxvx v3, 0, r4
335; CHECK-P9-NEXT:    vperm v2, v4, v2, v3
336; CHECK-P9-NEXT:    stxv vs6, 96(r3)
337; CHECK-P9-NEXT:    xvcvuxddp vs7, v2
338; CHECK-P9-NEXT:    stxv vs7, 112(r3)
339; CHECK-P9-NEXT:    blr
340;
341; CHECK-BE-LABEL: test16elt:
342; CHECK-BE:       # %bb.0: # %entry
343; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
344; CHECK-BE-NEXT:    xxlxor v4, v4, v4
345; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_0@toc@l
346; CHECK-BE-NEXT:    lxvx v3, 0, r4
347; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_1@toc@ha
348; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_1@toc@l
349; CHECK-BE-NEXT:    vperm v3, v2, v4, v3
350; CHECK-BE-NEXT:    xvcvuxddp vs0, v3
351; CHECK-BE-NEXT:    lxvx v3, 0, r4
352; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_2@toc@ha
353; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_2@toc@l
354; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
355; CHECK-BE-NEXT:    stxv vs0, 0(r3)
356; CHECK-BE-NEXT:    xvcvuxddp vs1, v3
357; CHECK-BE-NEXT:    lxvx v3, 0, r4
358; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_3@toc@ha
359; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_3@toc@l
360; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
361; CHECK-BE-NEXT:    stxv vs1, 16(r3)
362; CHECK-BE-NEXT:    xvcvuxddp vs2, v3
363; CHECK-BE-NEXT:    lxvx v3, 0, r4
364; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_4@toc@ha
365; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_4@toc@l
366; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
367; CHECK-BE-NEXT:    stxv vs2, 32(r3)
368; CHECK-BE-NEXT:    xvcvuxddp vs3, v3
369; CHECK-BE-NEXT:    lxvx v3, 0, r4
370; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_5@toc@ha
371; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_5@toc@l
372; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
373; CHECK-BE-NEXT:    stxv vs3, 48(r3)
374; CHECK-BE-NEXT:    xvcvuxddp vs4, v3
375; CHECK-BE-NEXT:    lxvx v3, 0, r4
376; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_6@toc@ha
377; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_6@toc@l
378; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
379; CHECK-BE-NEXT:    stxv vs4, 64(r3)
380; CHECK-BE-NEXT:    xvcvuxddp vs5, v3
381; CHECK-BE-NEXT:    lxvx v3, 0, r4
382; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_7@toc@ha
383; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_7@toc@l
384; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
385; CHECK-BE-NEXT:    stxv vs5, 80(r3)
386; CHECK-BE-NEXT:    xvcvuxddp vs6, v3
387; CHECK-BE-NEXT:    lxvx v3, 0, r4
388; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
389; CHECK-BE-NEXT:    stxv vs6, 96(r3)
390; CHECK-BE-NEXT:    xvcvuxddp vs7, v2
391; CHECK-BE-NEXT:    stxv vs7, 112(r3)
392; CHECK-BE-NEXT:    blr
393entry:
394  %0 = uitofp <16 x i8> %a to <16 x double>
395  store <16 x double> %0, <16 x double>* %agg.result, align 128
396  ret void
397}
398
399define <2 x double> @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 {
400; CHECK-P8-LABEL: test2elt_signed:
401; CHECK-P8:       # %bb.0: # %entry
402; CHECK-P8-NEXT:    addis r4, r2, .LCPI4_0@toc@ha
403; CHECK-P8-NEXT:    mtvsrwz v3, r3
404; CHECK-P8-NEXT:    addis r3, r2, .LCPI4_1@toc@ha
405; CHECK-P8-NEXT:    addi r4, r4, .LCPI4_0@toc@l
406; CHECK-P8-NEXT:    addi r3, r3, .LCPI4_1@toc@l
407; CHECK-P8-NEXT:    lvx v2, 0, r4
408; CHECK-P8-NEXT:    lxvd2x vs0, 0, r3
409; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
410; CHECK-P8-NEXT:    xxswapd v3, vs0
411; CHECK-P8-NEXT:    vsld v2, v2, v3
412; CHECK-P8-NEXT:    vsrad v2, v2, v3
413; CHECK-P8-NEXT:    xvcvsxddp v2, v2
414; CHECK-P8-NEXT:    blr
415;
416; CHECK-P9-LABEL: test2elt_signed:
417; CHECK-P9:       # %bb.0: # %entry
418; CHECK-P9-NEXT:    mtvsrws v2, r3
419; CHECK-P9-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
420; CHECK-P9-NEXT:    addi r3, r3, .LCPI4_0@toc@l
421; CHECK-P9-NEXT:    lxvx v3, 0, r3
422; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
423; CHECK-P9-NEXT:    vextsb2d v2, v2
424; CHECK-P9-NEXT:    xvcvsxddp v2, v2
425; CHECK-P9-NEXT:    blr
426;
427; CHECK-BE-LABEL: test2elt_signed:
428; CHECK-BE:       # %bb.0: # %entry
429; CHECK-BE-NEXT:    mtvsrws v2, r3
430; CHECK-BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
431; CHECK-BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
432; CHECK-BE-NEXT:    lxvx v3, 0, r3
433; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
434; CHECK-BE-NEXT:    vextsb2d v2, v2
435; CHECK-BE-NEXT:    xvcvsxddp v2, v2
436; CHECK-BE-NEXT:    blr
437entry:
438  %0 = bitcast i16 %a.coerce to <2 x i8>
439  %1 = sitofp <2 x i8> %0 to <2 x double>
440  ret <2 x double> %1
441}
442
443define void @test4elt_signed(<4 x double>* noalias nocapture sret(<4 x double>) %agg.result, i32 %a.coerce) local_unnamed_addr #1 {
444; CHECK-P8-LABEL: test4elt_signed:
445; CHECK-P8:       # %bb.0: # %entry
446; CHECK-P8-NEXT:    addis r5, r2, .LCPI5_0@toc@ha
447; CHECK-P8-NEXT:    addis r6, r2, .LCPI5_2@toc@ha
448; CHECK-P8-NEXT:    mtvsrwz v3, r4
449; CHECK-P8-NEXT:    addis r4, r2, .LCPI5_1@toc@ha
450; CHECK-P8-NEXT:    addi r5, r5, .LCPI5_0@toc@l
451; CHECK-P8-NEXT:    addi r4, r4, .LCPI5_1@toc@l
452; CHECK-P8-NEXT:    lvx v2, 0, r5
453; CHECK-P8-NEXT:    addi r5, r6, .LCPI5_2@toc@l
454; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
455; CHECK-P8-NEXT:    li r4, 16
456; CHECK-P8-NEXT:    lvx v4, 0, r5
457; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
458; CHECK-P8-NEXT:    vperm v3, v3, v3, v4
459; CHECK-P8-NEXT:    xxswapd v4, vs0
460; CHECK-P8-NEXT:    vsld v2, v2, v4
461; CHECK-P8-NEXT:    vsld v3, v3, v4
462; CHECK-P8-NEXT:    vsrad v2, v2, v4
463; CHECK-P8-NEXT:    vsrad v3, v3, v4
464; CHECK-P8-NEXT:    xvcvsxddp vs0, v2
465; CHECK-P8-NEXT:    xvcvsxddp vs1, v3
466; CHECK-P8-NEXT:    xxswapd vs0, vs0
467; CHECK-P8-NEXT:    xxswapd vs1, vs1
468; CHECK-P8-NEXT:    stxvd2x vs1, r3, r4
469; CHECK-P8-NEXT:    stxvd2x vs0, 0, r3
470; CHECK-P8-NEXT:    blr
471;
472; CHECK-P9-LABEL: test4elt_signed:
473; CHECK-P9:       # %bb.0: # %entry
474; CHECK-P9-NEXT:    mtvsrws v2, r4
475; CHECK-P9-NEXT:    addis r4, r2, .LCPI5_0@toc@ha
476; CHECK-P9-NEXT:    addi r4, r4, .LCPI5_0@toc@l
477; CHECK-P9-NEXT:    lxvx v3, 0, r4
478; CHECK-P9-NEXT:    addis r4, r2, .LCPI5_1@toc@ha
479; CHECK-P9-NEXT:    addi r4, r4, .LCPI5_1@toc@l
480; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
481; CHECK-P9-NEXT:    vextsb2d v3, v3
482; CHECK-P9-NEXT:    xvcvsxddp vs0, v3
483; CHECK-P9-NEXT:    lxvx v3, 0, r4
484; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
485; CHECK-P9-NEXT:    stxv vs0, 0(r3)
486; CHECK-P9-NEXT:    vextsb2d v2, v2
487; CHECK-P9-NEXT:    xvcvsxddp vs1, v2
488; CHECK-P9-NEXT:    stxv vs1, 16(r3)
489; CHECK-P9-NEXT:    blr
490;
491; CHECK-BE-LABEL: test4elt_signed:
492; CHECK-BE:       # %bb.0: # %entry
493; CHECK-BE-NEXT:    mtvsrws v2, r4
494; CHECK-BE-NEXT:    addis r4, r2, .LCPI5_0@toc@ha
495; CHECK-BE-NEXT:    xxlxor v3, v3, v3
496; CHECK-BE-NEXT:    addi r4, r4, .LCPI5_0@toc@l
497; CHECK-BE-NEXT:    lxvx v4, 0, r4
498; CHECK-BE-NEXT:    addis r4, r2, .LCPI5_1@toc@ha
499; CHECK-BE-NEXT:    addi r4, r4, .LCPI5_1@toc@l
500; CHECK-BE-NEXT:    vperm v3, v3, v2, v4
501; CHECK-BE-NEXT:    vextsb2d v3, v3
502; CHECK-BE-NEXT:    xvcvsxddp vs0, v3
503; CHECK-BE-NEXT:    lxvx v3, 0, r4
504; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
505; CHECK-BE-NEXT:    stxv vs0, 16(r3)
506; CHECK-BE-NEXT:    vextsb2d v2, v2
507; CHECK-BE-NEXT:    xvcvsxddp vs1, v2
508; CHECK-BE-NEXT:    stxv vs1, 0(r3)
509; CHECK-BE-NEXT:    blr
510entry:
511  %0 = bitcast i32 %a.coerce to <4 x i8>
512  %1 = sitofp <4 x i8> %0 to <4 x double>
513  store <4 x double> %1, <4 x double>* %agg.result, align 32
514  ret void
515}
516
517define void @test8elt_signed(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 {
518; CHECK-P8-LABEL: test8elt_signed:
519; CHECK-P8:       # %bb.0: # %entry
520; CHECK-P8-NEXT:    addis r5, r2, .LCPI6_0@toc@ha
521; CHECK-P8-NEXT:    addis r6, r2, .LCPI6_2@toc@ha
522; CHECK-P8-NEXT:    mtvsrd v3, r4
523; CHECK-P8-NEXT:    addis r4, r2, .LCPI6_1@toc@ha
524; CHECK-P8-NEXT:    addi r5, r5, .LCPI6_0@toc@l
525; CHECK-P8-NEXT:    addi r6, r6, .LCPI6_2@toc@l
526; CHECK-P8-NEXT:    addi r4, r4, .LCPI6_1@toc@l
527; CHECK-P8-NEXT:    lvx v2, 0, r5
528; CHECK-P8-NEXT:    addis r5, r2, .LCPI6_3@toc@ha
529; CHECK-P8-NEXT:    lvx v4, 0, r6
530; CHECK-P8-NEXT:    addis r6, r2, .LCPI6_4@toc@ha
531; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
532; CHECK-P8-NEXT:    li r4, 48
533; CHECK-P8-NEXT:    addi r5, r5, .LCPI6_3@toc@l
534; CHECK-P8-NEXT:    lvx v5, 0, r5
535; CHECK-P8-NEXT:    addi r5, r6, .LCPI6_4@toc@l
536; CHECK-P8-NEXT:    lvx v0, 0, r5
537; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
538; CHECK-P8-NEXT:    li r5, 32
539; CHECK-P8-NEXT:    vperm v4, v3, v3, v4
540; CHECK-P8-NEXT:    vperm v5, v3, v3, v5
541; CHECK-P8-NEXT:    vperm v3, v3, v3, v0
542; CHECK-P8-NEXT:    xxswapd v0, vs0
543; CHECK-P8-NEXT:    vsld v2, v2, v0
544; CHECK-P8-NEXT:    vsld v4, v4, v0
545; CHECK-P8-NEXT:    vsld v5, v5, v0
546; CHECK-P8-NEXT:    vsld v3, v3, v0
547; CHECK-P8-NEXT:    vsrad v2, v2, v0
548; CHECK-P8-NEXT:    vsrad v3, v3, v0
549; CHECK-P8-NEXT:    vsrad v4, v4, v0
550; CHECK-P8-NEXT:    vsrad v5, v5, v0
551; CHECK-P8-NEXT:    xvcvsxddp vs2, v3
552; CHECK-P8-NEXT:    xvcvsxddp vs0, v2
553; CHECK-P8-NEXT:    xvcvsxddp vs1, v5
554; CHECK-P8-NEXT:    xvcvsxddp vs3, v4
555; CHECK-P8-NEXT:    xxswapd vs2, vs2
556; CHECK-P8-NEXT:    xxswapd vs0, vs0
557; CHECK-P8-NEXT:    xxswapd vs1, vs1
558; CHECK-P8-NEXT:    xxswapd vs3, vs3
559; CHECK-P8-NEXT:    stxvd2x vs2, r3, r4
560; CHECK-P8-NEXT:    li r4, 16
561; CHECK-P8-NEXT:    stxvd2x vs1, r3, r5
562; CHECK-P8-NEXT:    stxvd2x vs3, r3, r4
563; CHECK-P8-NEXT:    stxvd2x vs0, 0, r3
564; CHECK-P8-NEXT:    blr
565;
566; CHECK-P9-LABEL: test8elt_signed:
567; CHECK-P9:       # %bb.0: # %entry
568; CHECK-P9-NEXT:    mtvsrd v2, r4
569; CHECK-P9-NEXT:    addis r4, r2, .LCPI6_0@toc@ha
570; CHECK-P9-NEXT:    addi r4, r4, .LCPI6_0@toc@l
571; CHECK-P9-NEXT:    lxvx v3, 0, r4
572; CHECK-P9-NEXT:    addis r4, r2, .LCPI6_1@toc@ha
573; CHECK-P9-NEXT:    addi r4, r4, .LCPI6_1@toc@l
574; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
575; CHECK-P9-NEXT:    vextsb2d v3, v3
576; CHECK-P9-NEXT:    xvcvsxddp vs0, v3
577; CHECK-P9-NEXT:    lxvx v3, 0, r4
578; CHECK-P9-NEXT:    addis r4, r2, .LCPI6_2@toc@ha
579; CHECK-P9-NEXT:    addi r4, r4, .LCPI6_2@toc@l
580; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
581; CHECK-P9-NEXT:    stxv vs0, 0(r3)
582; CHECK-P9-NEXT:    vextsb2d v3, v3
583; CHECK-P9-NEXT:    xvcvsxddp vs1, v3
584; CHECK-P9-NEXT:    lxvx v3, 0, r4
585; CHECK-P9-NEXT:    addis r4, r2, .LCPI6_3@toc@ha
586; CHECK-P9-NEXT:    addi r4, r4, .LCPI6_3@toc@l
587; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
588; CHECK-P9-NEXT:    stxv vs1, 16(r3)
589; CHECK-P9-NEXT:    vextsb2d v3, v3
590; CHECK-P9-NEXT:    xvcvsxddp vs2, v3
591; CHECK-P9-NEXT:    lxvx v3, 0, r4
592; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
593; CHECK-P9-NEXT:    stxv vs2, 32(r3)
594; CHECK-P9-NEXT:    vextsb2d v2, v2
595; CHECK-P9-NEXT:    xvcvsxddp vs3, v2
596; CHECK-P9-NEXT:    stxv vs3, 48(r3)
597; CHECK-P9-NEXT:    blr
598;
599; CHECK-BE-LABEL: test8elt_signed:
600; CHECK-BE:       # %bb.0: # %entry
601; CHECK-BE-NEXT:    mtvsrd v2, r4
602; CHECK-BE-NEXT:    addis r4, r2, .LCPI6_0@toc@ha
603; CHECK-BE-NEXT:    xxlxor v4, v4, v4
604; CHECK-BE-NEXT:    addi r4, r4, .LCPI6_0@toc@l
605; CHECK-BE-NEXT:    lxvx v3, 0, r4
606; CHECK-BE-NEXT:    addis r4, r2, .LCPI6_1@toc@ha
607; CHECK-BE-NEXT:    addi r4, r4, .LCPI6_1@toc@l
608; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
609; CHECK-BE-NEXT:    vextsb2d v3, v3
610; CHECK-BE-NEXT:    xvcvsxddp vs0, v3
611; CHECK-BE-NEXT:    lxvx v3, 0, r4
612; CHECK-BE-NEXT:    addis r4, r2, .LCPI6_2@toc@ha
613; CHECK-BE-NEXT:    addi r4, r4, .LCPI6_2@toc@l
614; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
615; CHECK-BE-NEXT:    stxv vs0, 16(r3)
616; CHECK-BE-NEXT:    vextsb2d v3, v3
617; CHECK-BE-NEXT:    xvcvsxddp vs1, v3
618; CHECK-BE-NEXT:    lxvx v3, 0, r4
619; CHECK-BE-NEXT:    addis r4, r2, .LCPI6_3@toc@ha
620; CHECK-BE-NEXT:    addi r4, r4, .LCPI6_3@toc@l
621; CHECK-BE-NEXT:    vperm v3, v2, v2, v3
622; CHECK-BE-NEXT:    stxv vs1, 48(r3)
623; CHECK-BE-NEXT:    vextsb2d v3, v3
624; CHECK-BE-NEXT:    xvcvsxddp vs2, v3
625; CHECK-BE-NEXT:    lxvx v3, 0, r4
626; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
627; CHECK-BE-NEXT:    stxv vs2, 0(r3)
628; CHECK-BE-NEXT:    vextsb2d v2, v2
629; CHECK-BE-NEXT:    xvcvsxddp vs3, v2
630; CHECK-BE-NEXT:    stxv vs3, 32(r3)
631; CHECK-BE-NEXT:    blr
632entry:
633  %0 = bitcast i64 %a.coerce to <8 x i8>
634  %1 = sitofp <8 x i8> %0 to <8 x double>
635  store <8 x double> %1, <8 x double>* %agg.result, align 64
636  ret void
637}
638
639define void @test16elt_signed(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i8> %a) local_unnamed_addr #2 {
640; CHECK-P8-LABEL: test16elt_signed:
641; CHECK-P8:       # %bb.0: # %entry
642; CHECK-P8-NEXT:    addis r4, r2, .LCPI7_0@toc@ha
643; CHECK-P8-NEXT:    addis r5, r2, .LCPI7_2@toc@ha
644; CHECK-P8-NEXT:    addis r6, r2, .LCPI7_3@toc@ha
645; CHECK-P8-NEXT:    addi r4, r4, .LCPI7_0@toc@l
646; CHECK-P8-NEXT:    addi r5, r5, .LCPI7_2@toc@l
647; CHECK-P8-NEXT:    addi r6, r6, .LCPI7_3@toc@l
648; CHECK-P8-NEXT:    lvx v3, 0, r4
649; CHECK-P8-NEXT:    addis r4, r2, .LCPI7_4@toc@ha
650; CHECK-P8-NEXT:    lvx v4, 0, r5
651; CHECK-P8-NEXT:    addis r5, r2, .LCPI7_5@toc@ha
652; CHECK-P8-NEXT:    lvx v5, 0, r6
653; CHECK-P8-NEXT:    addis r6, r2, .LCPI7_1@toc@ha
654; CHECK-P8-NEXT:    addi r4, r4, .LCPI7_4@toc@l
655; CHECK-P8-NEXT:    addi r5, r5, .LCPI7_5@toc@l
656; CHECK-P8-NEXT:    addi r6, r6, .LCPI7_1@toc@l
657; CHECK-P8-NEXT:    lvx v0, 0, r4
658; CHECK-P8-NEXT:    addis r4, r2, .LCPI7_6@toc@ha
659; CHECK-P8-NEXT:    lvx v1, 0, r5
660; CHECK-P8-NEXT:    addis r5, r2, .LCPI7_7@toc@ha
661; CHECK-P8-NEXT:    lxvd2x vs0, 0, r6
662; CHECK-P8-NEXT:    addi r4, r4, .LCPI7_6@toc@l
663; CHECK-P8-NEXT:    addi r5, r5, .LCPI7_7@toc@l
664; CHECK-P8-NEXT:    vperm v3, v2, v2, v3
665; CHECK-P8-NEXT:    lvx v6, 0, r4
666; CHECK-P8-NEXT:    addis r4, r2, .LCPI7_8@toc@ha
667; CHECK-P8-NEXT:    lvx v7, 0, r5
668; CHECK-P8-NEXT:    vperm v4, v2, v2, v4
669; CHECK-P8-NEXT:    li r5, 96
670; CHECK-P8-NEXT:    addi r4, r4, .LCPI7_8@toc@l
671; CHECK-P8-NEXT:    vperm v5, v2, v2, v5
672; CHECK-P8-NEXT:    xxswapd v9, vs0
673; CHECK-P8-NEXT:    lvx v8, 0, r4
674; CHECK-P8-NEXT:    vperm v0, v2, v2, v0
675; CHECK-P8-NEXT:    li r4, 112
676; CHECK-P8-NEXT:    vperm v1, v2, v2, v1
677; CHECK-P8-NEXT:    vperm v6, v2, v2, v6
678; CHECK-P8-NEXT:    vperm v7, v2, v2, v7
679; CHECK-P8-NEXT:    vperm v2, v2, v2, v8
680; CHECK-P8-NEXT:    vsld v3, v3, v9
681; CHECK-P8-NEXT:    vsld v0, v0, v9
682; CHECK-P8-NEXT:    vsld v1, v1, v9
683; CHECK-P8-NEXT:    vsld v6, v6, v9
684; CHECK-P8-NEXT:    vsld v7, v7, v9
685; CHECK-P8-NEXT:    vsld v2, v2, v9
686; CHECK-P8-NEXT:    vsrad v7, v7, v9
687; CHECK-P8-NEXT:    vsrad v2, v2, v9
688; CHECK-P8-NEXT:    vsld v4, v4, v9
689; CHECK-P8-NEXT:    vsld v5, v5, v9
690; CHECK-P8-NEXT:    vsrad v6, v6, v9
691; CHECK-P8-NEXT:    vsrad v0, v0, v9
692; CHECK-P8-NEXT:    vsrad v1, v1, v9
693; CHECK-P8-NEXT:    xvcvsxddp vs2, v7
694; CHECK-P8-NEXT:    xvcvsxddp vs3, v2
695; CHECK-P8-NEXT:    vsrad v3, v3, v9
696; CHECK-P8-NEXT:    vsrad v4, v4, v9
697; CHECK-P8-NEXT:    vsrad v5, v5, v9
698; CHECK-P8-NEXT:    xvcvsxddp vs4, v6
699; CHECK-P8-NEXT:    xvcvsxddp vs1, v1
700; CHECK-P8-NEXT:    xxswapd vs2, vs2
701; CHECK-P8-NEXT:    xvcvsxddp vs5, v0
702; CHECK-P8-NEXT:    xxswapd vs3, vs3
703; CHECK-P8-NEXT:    xvcvsxddp vs0, v5
704; CHECK-P8-NEXT:    xvcvsxddp vs6, v3
705; CHECK-P8-NEXT:    xvcvsxddp vs7, v4
706; CHECK-P8-NEXT:    stxvd2x vs3, r3, r4
707; CHECK-P8-NEXT:    li r4, 80
708; CHECK-P8-NEXT:    xxswapd vs4, vs4
709; CHECK-P8-NEXT:    stxvd2x vs2, r3, r5
710; CHECK-P8-NEXT:    li r5, 64
711; CHECK-P8-NEXT:    xxswapd vs1, vs1
712; CHECK-P8-NEXT:    xxswapd vs5, vs5
713; CHECK-P8-NEXT:    xxswapd vs0, vs0
714; CHECK-P8-NEXT:    stxvd2x vs4, r3, r4
715; CHECK-P8-NEXT:    li r4, 48
716; CHECK-P8-NEXT:    xxswapd vs3, vs6
717; CHECK-P8-NEXT:    stxvd2x vs1, r3, r5
718; CHECK-P8-NEXT:    li r5, 32
719; CHECK-P8-NEXT:    xxswapd vs2, vs7
720; CHECK-P8-NEXT:    stxvd2x vs5, r3, r4
721; CHECK-P8-NEXT:    li r4, 16
722; CHECK-P8-NEXT:    stxvd2x vs0, r3, r5
723; CHECK-P8-NEXT:    stxvd2x vs2, r3, r4
724; CHECK-P8-NEXT:    stxvd2x vs3, 0, r3
725; CHECK-P8-NEXT:    blr
726;
727; CHECK-P9-LABEL: test16elt_signed:
728; CHECK-P9:       # %bb.0: # %entry
729; CHECK-P9-NEXT:    addis r4, r2, .LCPI7_0@toc@ha
730; CHECK-P9-NEXT:    addi r4, r4, .LCPI7_0@toc@l
731; CHECK-P9-NEXT:    lxvx v3, 0, r4
732; CHECK-P9-NEXT:    addis r4, r2, .LCPI7_1@toc@ha
733; CHECK-P9-NEXT:    addi r4, r4, .LCPI7_1@toc@l
734; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
735; CHECK-P9-NEXT:    vextsb2d v3, v3
736; CHECK-P9-NEXT:    xvcvsxddp vs0, v3
737; CHECK-P9-NEXT:    lxvx v3, 0, r4
738; CHECK-P9-NEXT:    addis r4, r2, .LCPI7_2@toc@ha
739; CHECK-P9-NEXT:    addi r4, r4, .LCPI7_2@toc@l
740; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
741; CHECK-P9-NEXT:    stxv vs0, 0(r3)
742; CHECK-P9-NEXT:    vextsb2d v3, v3
743; CHECK-P9-NEXT:    xvcvsxddp vs1, v3
744; CHECK-P9-NEXT:    lxvx v3, 0, r4
745; CHECK-P9-NEXT:    addis r4, r2, .LCPI7_3@toc@ha
746; CHECK-P9-NEXT:    addi r4, r4, .LCPI7_3@toc@l
747; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
748; CHECK-P9-NEXT:    stxv vs1, 16(r3)
749; CHECK-P9-NEXT:    vextsb2d v3, v3
750; CHECK-P9-NEXT:    xvcvsxddp vs2, v3
751; CHECK-P9-NEXT:    lxvx v3, 0, r4
752; CHECK-P9-NEXT:    addis r4, r2, .LCPI7_4@toc@ha
753; CHECK-P9-NEXT:    addi r4, r4, .LCPI7_4@toc@l
754; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
755; CHECK-P9-NEXT:    stxv vs2, 32(r3)
756; CHECK-P9-NEXT:    vextsb2d v3, v3
757; CHECK-P9-NEXT:    xvcvsxddp vs3, v3
758; CHECK-P9-NEXT:    lxvx v3, 0, r4
759; CHECK-P9-NEXT:    addis r4, r2, .LCPI7_5@toc@ha
760; CHECK-P9-NEXT:    addi r4, r4, .LCPI7_5@toc@l
761; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
762; CHECK-P9-NEXT:    stxv vs3, 48(r3)
763; CHECK-P9-NEXT:    vextsb2d v3, v3
764; CHECK-P9-NEXT:    xvcvsxddp vs4, v3
765; CHECK-P9-NEXT:    lxvx v3, 0, r4
766; CHECK-P9-NEXT:    addis r4, r2, .LCPI7_6@toc@ha
767; CHECK-P9-NEXT:    addi r4, r4, .LCPI7_6@toc@l
768; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
769; CHECK-P9-NEXT:    stxv vs4, 64(r3)
770; CHECK-P9-NEXT:    vextsb2d v3, v3
771; CHECK-P9-NEXT:    xvcvsxddp vs5, v3
772; CHECK-P9-NEXT:    lxvx v3, 0, r4
773; CHECK-P9-NEXT:    addis r4, r2, .LCPI7_7@toc@ha
774; CHECK-P9-NEXT:    addi r4, r4, .LCPI7_7@toc@l
775; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
776; CHECK-P9-NEXT:    stxv vs5, 80(r3)
777; CHECK-P9-NEXT:    vextsb2d v3, v3
778; CHECK-P9-NEXT:    xvcvsxddp vs6, v3
779; CHECK-P9-NEXT:    lxvx v3, 0, r4
780; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
781; CHECK-P9-NEXT:    stxv vs6, 96(r3)
782; CHECK-P9-NEXT:    vextsb2d v2, v2
783; CHECK-P9-NEXT:    xvcvsxddp vs7, v2
784; CHECK-P9-NEXT:    stxv vs7, 112(r3)
785; CHECK-P9-NEXT:    blr
786;
787; CHECK-BE-LABEL: test16elt_signed:
788; CHECK-BE:       # %bb.0: # %entry
789; CHECK-BE-NEXT:    addis r4, r2, .LCPI7_0@toc@ha
790; CHECK-BE-NEXT:    xxlxor v3, v3, v3
791; CHECK-BE-NEXT:    addi r4, r4, .LCPI7_0@toc@l
792; CHECK-BE-NEXT:    lxvx v4, 0, r4
793; CHECK-BE-NEXT:    addis r4, r2, .LCPI7_1@toc@ha
794; CHECK-BE-NEXT:    addi r4, r4, .LCPI7_1@toc@l
795; CHECK-BE-NEXT:    vperm v4, v3, v2, v4
796; CHECK-BE-NEXT:    vextsb2d v4, v4
797; CHECK-BE-NEXT:    xvcvsxddp vs0, v4
798; CHECK-BE-NEXT:    lxvx v4, 0, r4
799; CHECK-BE-NEXT:    addis r4, r2, .LCPI7_2@toc@ha
800; CHECK-BE-NEXT:    addi r4, r4, .LCPI7_2@toc@l
801; CHECK-BE-NEXT:    vperm v4, v3, v2, v4
802; CHECK-BE-NEXT:    stxv vs0, 16(r3)
803; CHECK-BE-NEXT:    vextsb2d v4, v4
804; CHECK-BE-NEXT:    xvcvsxddp vs1, v4
805; CHECK-BE-NEXT:    lxvx v4, 0, r4
806; CHECK-BE-NEXT:    addis r4, r2, .LCPI7_3@toc@ha
807; CHECK-BE-NEXT:    addi r4, r4, .LCPI7_3@toc@l
808; CHECK-BE-NEXT:    vperm v4, v3, v2, v4
809; CHECK-BE-NEXT:    stxv vs1, 48(r3)
810; CHECK-BE-NEXT:    vextsb2d v4, v4
811; CHECK-BE-NEXT:    xvcvsxddp vs2, v4
812; CHECK-BE-NEXT:    lxvx v4, 0, r4
813; CHECK-BE-NEXT:    addis r4, r2, .LCPI7_4@toc@ha
814; CHECK-BE-NEXT:    addi r4, r4, .LCPI7_4@toc@l
815; CHECK-BE-NEXT:    vperm v3, v3, v2, v4
816; CHECK-BE-NEXT:    stxv vs2, 80(r3)
817; CHECK-BE-NEXT:    vextsb2d v3, v3
818; CHECK-BE-NEXT:    xvcvsxddp vs3, v3
819; CHECK-BE-NEXT:    lxvx v3, 0, r4
820; CHECK-BE-NEXT:    addis r4, r2, .LCPI7_5@toc@ha
821; CHECK-BE-NEXT:    addi r4, r4, .LCPI7_5@toc@l
822; CHECK-BE-NEXT:    vperm v3, v2, v2, v3
823; CHECK-BE-NEXT:    stxv vs3, 112(r3)
824; CHECK-BE-NEXT:    vextsb2d v3, v3
825; CHECK-BE-NEXT:    xvcvsxddp vs4, v3
826; CHECK-BE-NEXT:    lxvx v3, 0, r4
827; CHECK-BE-NEXT:    addis r4, r2, .LCPI7_6@toc@ha
828; CHECK-BE-NEXT:    addi r4, r4, .LCPI7_6@toc@l
829; CHECK-BE-NEXT:    vperm v3, v2, v2, v3
830; CHECK-BE-NEXT:    stxv vs4, 0(r3)
831; CHECK-BE-NEXT:    vextsb2d v3, v3
832; CHECK-BE-NEXT:    xvcvsxddp vs5, v3
833; CHECK-BE-NEXT:    lxvx v3, 0, r4
834; CHECK-BE-NEXT:    addis r4, r2, .LCPI7_7@toc@ha
835; CHECK-BE-NEXT:    addi r4, r4, .LCPI7_7@toc@l
836; CHECK-BE-NEXT:    vperm v3, v2, v2, v3
837; CHECK-BE-NEXT:    stxv vs5, 32(r3)
838; CHECK-BE-NEXT:    vextsb2d v3, v3
839; CHECK-BE-NEXT:    xvcvsxddp vs6, v3
840; CHECK-BE-NEXT:    lxvx v3, 0, r4
841; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
842; CHECK-BE-NEXT:    stxv vs6, 64(r3)
843; CHECK-BE-NEXT:    vextsb2d v2, v2
844; CHECK-BE-NEXT:    xvcvsxddp vs7, v2
845; CHECK-BE-NEXT:    stxv vs7, 96(r3)
846; CHECK-BE-NEXT:    blr
847entry:
848  %0 = sitofp <16 x i8> %a to <16 x double>
849  store <16 x double> %0, <16 x double>* %agg.result, align 128
850  ret void
851}
852