1; RUN: llc < %s -mtriple=s390x-linux-gnu -verify-machineinstrs | FileCheck %s 2; RUN: llc < %s -mtriple=s390x-linux-gnu -O0 -verify-machineinstrs | FileCheck --check-prefix=CHECK-O0 %s 3 4@var = global i32 0 5 6; Test how llvm handles return type of {i16, i8}. The return value will be 7; passed in %r2 and %r3. 8; CHECK-LABEL: test: 9; CHECK: st %r2 10; CHECK: brasl %r14, gen 11; CHECK-DAG: lhr %{{r[0,2]+}}, %r2 12; CHECK-DAG: lbr %{{r[0,2]+}}, %r3 13; CHECK: ar %r2, %r0 14; CHECK-O0-LABEL: test 15; CHECK-O0: st %r2 16; CHECK-O0: brasl %r14, gen 17; CHECK-O0-DAG: lhr %r2, %r2 18; CHECK-O0-DAG: lbr %[[REG2:r[0-9]+]], %r3 19; CHECK-O0: ar %r2, %[[REG2]] 20define i16 @test(i32 %key) { 21entry: 22 %key.addr = alloca i32, align 4 23 store i32 %key, i32* %key.addr, align 4 24 %0 = load i32, i32* %key.addr, align 4 25 %call = call swiftcc { i16, i8 } @gen(i32 %0) 26 %v3 = extractvalue { i16, i8 } %call, 0 27 %v1 = sext i16 %v3 to i32 28 %v5 = extractvalue { i16, i8 } %call, 1 29 %v2 = sext i8 %v5 to i32 30 %add = add nsw i32 %v1, %v2 31 %conv = trunc i32 %add to i16 32 ret i16 %conv 33} 34 35declare swiftcc { i16, i8 } @gen(i32) 36 37; If we can't pass every return value in registers, we will pass everything 38; in memroy. The caller provides space for the return value and passes 39; the address in %r2. The first input argument will be in %r3. 40; CHECK-LABEL: test2: 41; CHECK: lr %r3, %r2 42; CHECK-DAG: la %r2, 160(%r15) 43; CHECK: brasl %r14, gen2 44; CHECK: l %r2, 160(%r15) 45; CHECK: a %r2, 164(%r15) 46; CHECK: a %r2, 168(%r15) 47; CHECK: a %r2, 172(%r15) 48; CHECK: a %r2, 176(%r15) 49; CHECK-O0-LABEL: test2: 50; CHECK-O0: st %r2, [[SPILL1:[0-9]+]](%r15) 51; CHECK-O0: l %r3, [[SPILL1]](%r15) 52; CHECK-O0: la %r2, 160(%r15) 53; CHECK-O0: brasl %r14, gen2 54; CHECK-O0-DAG: l %r{{.*}}, 176(%r15) 55; CHECK-O0-DAG: l %r{{.*}}, 172(%r15) 56; CHECK-O0-DAG: l %r{{.*}}, 168(%r15) 57; CHECK-O0-DAG: l %r{{.*}}, 164(%r15) 58; CHECK-O0-DAG: l %r{{.*}}, 160(%r15) 59; CHECK-O0: ar 60; CHECK-O0: ar 61; CHECK-O0: ar 62; CHECK-O0: ar 63define i32 @test2(i32 %key) #0 { 64entry: 65 %key.addr = alloca i32, align 4 66 store i32 %key, i32* %key.addr, align 4 67 %0 = load i32, i32* %key.addr, align 4 68 %call = call swiftcc { i32, i32, i32, i32, i32 } @gen2(i32 %0) 69 70 %v3 = extractvalue { i32, i32, i32, i32, i32 } %call, 0 71 %v5 = extractvalue { i32, i32, i32, i32, i32 } %call, 1 72 %v6 = extractvalue { i32, i32, i32, i32, i32 } %call, 2 73 %v7 = extractvalue { i32, i32, i32, i32, i32 } %call, 3 74 %v8 = extractvalue { i32, i32, i32, i32, i32 } %call, 4 75 76 %add = add nsw i32 %v3, %v5 77 %add1 = add nsw i32 %add, %v6 78 %add2 = add nsw i32 %add1, %v7 79 %add3 = add nsw i32 %add2, %v8 80 ret i32 %add3 81} 82 83; The address of the return value is passed in %r2. 84; On return, %r2 will contain the adddress that has been passed in by the caller in %r2. 85; CHECK-LABEL: gen2: 86; CHECK: st %r3, 16(%r2) 87; CHECK: st %r3, 12(%r2) 88; CHECK: st %r3, 8(%r2) 89; CHECK: st %r3, 4(%r2) 90; CHECK: st %r3, 0(%r2) 91; CHECK-O0-LABEL: gen2: 92; CHECK-O0-DAG: st %r3, 16(%r2) 93; CHECK-O0-DAG: st %r3, 12(%r2) 94; CHECK-O0-DAG: st %r3, 8(%r2) 95; CHECK-O0-DAG: st %r3, 4(%r2) 96; CHECK-O0-DAG: st %r3, 0(%r2) 97define swiftcc { i32, i32, i32, i32, i32 } @gen2(i32 %key) { 98 %Y = insertvalue { i32, i32, i32, i32, i32 } undef, i32 %key, 0 99 %Z = insertvalue { i32, i32, i32, i32, i32 } %Y, i32 %key, 1 100 %Z2 = insertvalue { i32, i32, i32, i32, i32 } %Z, i32 %key, 2 101 %Z3 = insertvalue { i32, i32, i32, i32, i32 } %Z2, i32 %key, 3 102 %Z4 = insertvalue { i32, i32, i32, i32, i32 } %Z3, i32 %key, 4 103 ret { i32, i32, i32, i32, i32 } %Z4 104} 105 106; The return value {i32, i32, i32, i32} will be returned via registers 107; %r2, %r3, %r4, %r5. 108; CHECK-LABEL: test3: 109; CHECK: brasl %r14, gen3 110; CHECK: ar %r2, %r3 111; CHECK: ar %r2, %r4 112; CHECK: ar %r2, %r5 113; CHECK-O0-LABEL: test3: 114; CHECK-O0: brasl %r14, gen3 115; CHECK-O0: ar %r2, %r3 116; CHECK-O0: ar %r2, %r4 117; CHECK-O0: ar %r2, %r5 118define i32 @test3(i32 %key) #0 { 119entry: 120 %key.addr = alloca i32, align 4 121 store i32 %key, i32* %key.addr, align 4 122 %0 = load i32, i32* %key.addr, align 4 123 %call = call swiftcc { i32, i32, i32, i32 } @gen3(i32 %0) 124 125 %v3 = extractvalue { i32, i32, i32, i32 } %call, 0 126 %v5 = extractvalue { i32, i32, i32, i32 } %call, 1 127 %v6 = extractvalue { i32, i32, i32, i32 } %call, 2 128 %v7 = extractvalue { i32, i32, i32, i32 } %call, 3 129 130 %add = add nsw i32 %v3, %v5 131 %add1 = add nsw i32 %add, %v6 132 %add2 = add nsw i32 %add1, %v7 133 ret i32 %add2 134} 135 136declare swiftcc { i32, i32, i32, i32 } @gen3(i32 %key) 137 138; The return value {float, float, float, float} will be returned via registers 139; %f0, %f2, %f4, %f6. 140; CHECK-LABEL: test4: 141; CHECK: brasl %r14, gen4 142; CHECK: aebr %f0, %f2 143; CHECK: aebr %f0, %f4 144; CHECK: aebr %f0, %f6 145; CHECK-O0-LABEL: test4: 146; CHECK-O0: brasl %r14, gen4 147; CHECK-O0: aebr %f0, %f2 148; CHECK-O0: aebr %f0, %f4 149; CHECK-O0: aebr %f0, %f6 150define float @test4(float %key) #0 { 151entry: 152 %key.addr = alloca float, align 4 153 store float %key, float* %key.addr, align 4 154 %0 = load float, float* %key.addr, align 4 155 %call = call swiftcc { float, float, float, float } @gen4(float %0) 156 157 %v3 = extractvalue { float, float, float, float } %call, 0 158 %v5 = extractvalue { float, float, float, float } %call, 1 159 %v6 = extractvalue { float, float, float, float } %call, 2 160 %v7 = extractvalue { float, float, float, float } %call, 3 161 162 %add = fadd float %v3, %v5 163 %add1 = fadd float %add, %v6 164 %add2 = fadd float %add1, %v7 165 ret float %add2 166} 167 168declare swiftcc { float, float, float, float } @gen4(float %key) 169 170; CHECK-LABEL: consume_i1_ret: 171; CHECK: brasl %r14, produce_i1_ret 172; CHECK: nilf %r2, 1 173; CHECK: nilf %r3, 1 174; CHECK: nilf %r4, 1 175; CHECK: nilf %r5, 1 176; CHECK-O0-LABEL: consume_i1_ret: 177; CHECK-O0: brasl %r14, produce_i1_ret 178; CHECK-O0: nilf %r2, 1 179; CHECK-O0: nilf %r3, 1 180; CHECK-O0: nilf %r4, 1 181; CHECK-O0: nilf %r5, 1 182define void @consume_i1_ret() { 183 %call = call swiftcc { i1, i1, i1, i1 } @produce_i1_ret() 184 %v3 = extractvalue { i1, i1, i1, i1 } %call, 0 185 %v5 = extractvalue { i1, i1, i1, i1 } %call, 1 186 %v6 = extractvalue { i1, i1, i1, i1 } %call, 2 187 %v7 = extractvalue { i1, i1, i1, i1 } %call, 3 188 %val = zext i1 %v3 to i32 189 store volatile i32 %val, i32* @var 190 %val2 = zext i1 %v5 to i32 191 store volatile i32 %val2, i32* @var 192 %val3 = zext i1 %v6 to i32 193 store volatile i32 %val3, i32* @var 194 %val4 = zext i1 %v7 to i32 195 store i32 %val4, i32* @var 196 ret void 197} 198 199declare swiftcc { i1, i1, i1, i1 } @produce_i1_ret() 200