1; RUN: opt < %s -licm -loop-vectorize -force-vector-width=4 -dce -instcombine -licm -S | FileCheck %s 2 3; First licm pass is to hoist/sink invariant stores if possible. Today LICM does 4; not hoist/sink the invariant stores. Even if that changes, we should still 5; vectorize this loop in case licm is not run. 6 7; The next licm pass after vectorization is to hoist/sink loop invariant 8; instructions. 9target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" 10 11; all tests check that it is legal to vectorize the stores to invariant 12; address. 13 14 15; CHECK-LABEL: inv_val_store_to_inv_address_with_reduction( 16; memory check is found.conflict = b[max(n-1,1)] > a && (i8* a)+1 > (i8* b) 17; CHECK: vector.memcheck: 18; CHECK: found.conflict 19 20; CHECK-LABEL: vector.body: 21; CHECK: %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ [[ADD:%[a-zA-Z0-9.]+]], %vector.body ] 22; CHECK: %wide.load = load <4 x i32> 23; CHECK: [[ADD]] = add <4 x i32> %vec.phi, %wide.load 24; CHECK-NEXT: store i32 %ntrunc, i32* %a 25; CHECK-NEXT: %index.next = add i64 %index, 4 26; CHECK-NEXT: icmp eq i64 %index.next, %n.vec 27; CHECK-NEXT: br i1 28 29; CHECK-LABEL: middle.block: 30; CHECK: %rdx.shuf = shufflevector <4 x i32> 31define i32 @inv_val_store_to_inv_address_with_reduction(i32* %a, i64 %n, i32* %b) { 32entry: 33 %ntrunc = trunc i64 %n to i32 34 br label %for.body 35 36for.body: ; preds = %for.body, %entry 37 %i = phi i64 [ %i.next, %for.body ], [ 0, %entry ] 38 %tmp0 = phi i32 [ %tmp3, %for.body ], [ 0, %entry ] 39 %tmp1 = getelementptr inbounds i32, i32* %b, i64 %i 40 %tmp2 = load i32, i32* %tmp1, align 8 41 %tmp3 = add i32 %tmp0, %tmp2 42 store i32 %ntrunc, i32* %a 43 %i.next = add nuw nsw i64 %i, 1 44 %cond = icmp slt i64 %i.next, %n 45 br i1 %cond, label %for.body, label %for.end 46 47for.end: ; preds = %for.body 48 %tmp4 = phi i32 [ %tmp3, %for.body ] 49 ret i32 %tmp4 50} 51 52; CHECK-LABEL: inv_val_store_to_inv_address( 53; CHECK-LABEL: vector.body: 54; CHECK: store i32 %ntrunc, i32* %a 55; CHECK: store <4 x i32> 56; CHECK-NEXT: %index.next = add i64 %index, 4 57; CHECK-NEXT: icmp eq i64 %index.next, %n.vec 58; CHECK-NEXT: br i1 59define void @inv_val_store_to_inv_address(i32* %a, i64 %n, i32* %b) { 60entry: 61 %ntrunc = trunc i64 %n to i32 62 br label %for.body 63 64for.body: ; preds = %for.body, %entry 65 %i = phi i64 [ %i.next, %for.body ], [ 0, %entry ] 66 %tmp1 = getelementptr inbounds i32, i32* %b, i64 %i 67 %tmp2 = load i32, i32* %tmp1, align 8 68 store i32 %ntrunc, i32* %a 69 store i32 %ntrunc, i32* %tmp1 70 %i.next = add nuw nsw i64 %i, 1 71 %cond = icmp slt i64 %i.next, %n 72 br i1 %cond, label %for.body, label %for.end 73 74for.end: ; preds = %for.body 75 ret void 76} 77 78 79; Both of these tests below are handled as predicated stores. 80 81; Conditional store 82; if (b[i] == k) a = ntrunc 83; TODO: We can be better with the code gen for the first test and we can have 84; just one scalar store if vector.or.reduce(vector_cmp(b[i] == k)) is 1. 85 86; CHECK-LABEL:inv_val_store_to_inv_address_conditional( 87; CHECK-LABEL: vector.body: 88; CHECK: %wide.load = load <4 x i32>, <4 x i32>* 89; CHECK: [[CMP:%[a-zA-Z0-9.]+]] = icmp eq <4 x i32> %wide.load, %{{.*}} 90; CHECK: store <4 x i32> 91; CHECK-NEXT: [[EE:%[a-zA-Z0-9.]+]] = extractelement <4 x i1> [[CMP]], i32 0 92; CHECK-NEXT: br i1 [[EE]], label %pred.store.if, label %pred.store.continue 93 94; CHECK-LABEL: pred.store.if: 95; CHECK-NEXT: store i32 %ntrunc, i32* %a 96; CHECK-NEXT: br label %pred.store.continue 97 98; CHECK-LABEL: pred.store.continue: 99; CHECK-NEXT: [[EE1:%[a-zA-Z0-9.]+]] = extractelement <4 x i1> [[CMP]], i32 1 100define void @inv_val_store_to_inv_address_conditional(i32* %a, i64 %n, i32* %b, i32 %k) { 101entry: 102 %ntrunc = trunc i64 %n to i32 103 br label %for.body 104 105for.body: ; preds = %for.body, %entry 106 %i = phi i64 [ %i.next, %latch ], [ 0, %entry ] 107 %tmp1 = getelementptr inbounds i32, i32* %b, i64 %i 108 %tmp2 = load i32, i32* %tmp1, align 8 109 %cmp = icmp eq i32 %tmp2, %k 110 store i32 %ntrunc, i32* %tmp1 111 br i1 %cmp, label %cond_store, label %latch 112 113cond_store: 114 store i32 %ntrunc, i32* %a 115 br label %latch 116 117latch: 118 %i.next = add nuw nsw i64 %i, 1 119 %cond = icmp slt i64 %i.next, %n 120 br i1 %cond, label %for.body, label %for.end 121 122for.end: ; preds = %for.body 123 ret void 124} 125 126; if (b[i] == k) 127; a = ntrunc 128; else a = k; 129; TODO: We could vectorize this once we support multiple uniform stores to the 130; same address. 131; CHECK-LABEL:inv_val_store_to_inv_address_conditional_diff_values( 132; CHECK-NOT: load <4 x i32> 133define void @inv_val_store_to_inv_address_conditional_diff_values(i32* %a, i64 %n, i32* %b, i32 %k) { 134entry: 135 %ntrunc = trunc i64 %n to i32 136 br label %for.body 137 138for.body: ; preds = %for.body, %entry 139 %i = phi i64 [ %i.next, %latch ], [ 0, %entry ] 140 %tmp1 = getelementptr inbounds i32, i32* %b, i64 %i 141 %tmp2 = load i32, i32* %tmp1, align 8 142 %cmp = icmp eq i32 %tmp2, %k 143 store i32 %ntrunc, i32* %tmp1 144 br i1 %cmp, label %cond_store, label %cond_store_k 145 146cond_store: 147 store i32 %ntrunc, i32* %a 148 br label %latch 149 150cond_store_k: 151 store i32 %k, i32 * %a 152 br label %latch 153 154latch: 155 %i.next = add nuw nsw i64 %i, 1 156 %cond = icmp slt i64 %i.next, %n 157 br i1 %cond, label %for.body, label %for.end 158 159for.end: ; preds = %for.body 160 ret void 161} 162 163; Instcombine'd version of above test. Now the store is no longer of invariant 164; value. 165; scalar store the value extracted from the last element of the vector value. 166; CHECK-LABEL: inv_val_store_to_inv_address_conditional_diff_values_ic 167; CHECK-NEXT: entry: 168; CHECK-NEXT: [[NTRUNC:%.*]] = trunc i64 [[N:%.*]] to i32 169; CHECK-NEXT: [[TMP0:%.*]] = icmp sgt i64 [[N]], 1 170; CHECK-NEXT: [[SMAX:%.*]] = select i1 [[TMP0]], i64 [[N]], i64 1 171; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[SMAX]], 4 172; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]] 173; CHECK: vector.memcheck: 174; CHECK-NEXT: [[A4:%.*]] = bitcast i32* [[A:%.*]] to i8* 175; CHECK-NEXT: [[B1:%.*]] = bitcast i32* [[B:%.*]] to i8* 176; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i64 [[N]], 1 177; CHECK-NEXT: [[SMAX2:%.*]] = select i1 [[TMP1]], i64 [[N]], i64 1 178; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i32, i32* [[B]], i64 [[SMAX2]] 179; CHECK-NEXT: [[UGLYGEP:%.*]] = getelementptr i8, i8* [[A4]], i64 1 180; CHECK-NEXT: [[BOUND0:%.*]] = icmp ugt i8* [[UGLYGEP]], [[B1]] 181; CHECK-NEXT: [[BOUND1:%.*]] = icmp ugt i32* [[SCEVGEP]], [[A]] 182; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] 183; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] 184; CHECK: vector.ph: 185; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[SMAX]], 9223372036854775804 186; CHECK-NEXT: [[BROADCAST_SPLATINSERT5:%.*]] = insertelement <4 x i32> poison, i32 [[K:%.*]], i32 0 187; CHECK-NEXT: [[BROADCAST_SPLAT6:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT5]], <4 x i32> poison, <4 x i32> zeroinitializer 188; CHECK-NEXT: [[BROADCAST_SPLATINSERT7:%.*]] = insertelement <4 x i32> poison, i32 [[NTRUNC]], i32 0 189; CHECK-NEXT: [[BROADCAST_SPLAT8:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT7]], <4 x i32> poison, <4 x i32> zeroinitializer 190; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 191; CHECK: vector.body: 192; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 193; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 [[INDEX]] 194; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32* [[TMP2]] to <4 x i32>* 195; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, <4 x i32>* [[TMP3]], align 8 196; CHECK-NEXT: [[TMP4:%.*]] = icmp eq <4 x i32> [[WIDE_LOAD]], [[BROADCAST_SPLAT6]] 197; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32* [[TMP2]] to <4 x i32>* 198; CHECK-NEXT: store <4 x i32> [[BROADCAST_SPLAT8]], <4 x i32>* [[TMP5]], align 4 199; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP4]], <4 x i32> [[BROADCAST_SPLAT8]], <4 x i32> [[BROADCAST_SPLAT6]] 200; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[PREDPHI]], i32 3 201; CHECK-NEXT: store i32 [[TMP6]], i32* [[A]], align 4 202; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4 203; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 204; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]] 205; CHECK: middle.block: 206; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[SMAX]], [[N_VEC]] 207; CHECK-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[SCALAR_PH]] 208; CHECK: scalar.ph: 209; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_MEMCHECK]] ] 210; CHECK-NEXT: br label [[FOR_BODY:%.*]] 211; CHECK: for.body: 212; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_NEXT:%.*]], [[LATCH:%.*]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] 213; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 [[I]] 214; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 8 215; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP2]], [[K]] 216; CHECK-NEXT: store i32 [[NTRUNC]], i32* [[TMP1]], align 4 217; CHECK-NEXT: br i1 [[CMP]], label [[COND_STORE:%.*]], label [[COND_STORE_K:%.*]] 218; CHECK: cond_store: 219; CHECK-NEXT: br label [[LATCH]] 220; CHECK: cond_store_k: 221; CHECK-NEXT: br label [[LATCH]] 222; CHECK: latch: 223; CHECK-NEXT: [[STOREVAL:%.*]] = phi i32 [ [[NTRUNC]], [[COND_STORE]] ], [ [[K]], [[COND_STORE_K]] ] 224; CHECK-NEXT: store i32 [[STOREVAL]], i32* [[A]], align 4 225; CHECK-NEXT: [[I_NEXT]] = add nuw nsw i64 [[I]], 1 226; CHECK-NEXT: [[COND:%.*]] = icmp slt i64 [[I_NEXT]], [[N]] 227; CHECK-NEXT: br i1 [[COND]], label [[FOR_BODY]], label [[FOR_END_LOOPEXIT:%.*]] 228; CHECK: for.end.loopexit: 229; CHECK-NEXT: br label [[FOR_END]] 230; CHECK: for.end: 231; CHECK-NEXT: ret void 232; 233define void @inv_val_store_to_inv_address_conditional_diff_values_ic(i32* %a, i64 %n, i32* %b, i32 %k) { 234entry: 235 %ntrunc = trunc i64 %n to i32 236 br label %for.body 237 238for.body: ; preds = %for.body, %entry 239 %i = phi i64 [ %i.next, %latch ], [ 0, %entry ] 240 %tmp1 = getelementptr inbounds i32, i32* %b, i64 %i 241 %tmp2 = load i32, i32* %tmp1, align 8 242 %cmp = icmp eq i32 %tmp2, %k 243 store i32 %ntrunc, i32* %tmp1 244 br i1 %cmp, label %cond_store, label %cond_store_k 245 246cond_store: 247 br label %latch 248 249cond_store_k: 250 br label %latch 251 252latch: 253 %storeval = phi i32 [ %ntrunc, %cond_store ], [ %k, %cond_store_k ] 254 store i32 %storeval, i32* %a 255 %i.next = add nuw nsw i64 %i, 1 256 %cond = icmp slt i64 %i.next, %n 257 br i1 %cond, label %for.body, label %for.end 258 259for.end: ; preds = %for.body 260 ret void 261} 262 263; invariant val stored to invariant address predicated on invariant condition 264; This is not treated as a predicated store since the block the store belongs to 265; is the latch block (which doesn't need to be predicated). 266; variant/invariant values being stored to invariant address. 267; test checks that the last element of the phi is extracted and scalar stored 268; into the uniform address within the loop. 269; Since the condition and the phi is loop invariant, they are LICM'ed after 270; vectorization. 271; CHECK-LABEL: inv_val_store_to_inv_address_conditional_inv 272; CHECK-NEXT: entry: 273; CHECK-NEXT: [[NTRUNC:%.*]] = trunc i64 [[N:%.*]] to i32 274; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[NTRUNC]], [[K:%.*]] 275; CHECK-NEXT: [[TMP0:%.*]] = icmp sgt i64 [[N]], 1 276; CHECK-NEXT: [[SMAX:%.*]] = select i1 [[TMP0]], i64 [[N]], i64 1 277; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[SMAX]], 4 278; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]] 279; CHECK: vector.memcheck: 280; CHECK-NEXT: [[A4:%.*]] = bitcast i32* [[A:%.*]] to i8* 281; CHECK-NEXT: [[B1:%.*]] = bitcast i32* [[B:%.*]] to i8* 282; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i64 [[N]], 1 283; CHECK-NEXT: [[SMAX2:%.*]] = select i1 [[TMP1]], i64 [[N]], i64 1 284; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i32, i32* [[B]], i64 [[SMAX2]] 285; CHECK-NEXT: [[UGLYGEP:%.*]] = getelementptr i8, i8* [[A4]], i64 1 286; CHECK-NEXT: [[BOUND0:%.*]] = icmp ugt i8* [[UGLYGEP]], [[B1]] 287; CHECK-NEXT: [[BOUND1:%.*]] = icmp ugt i32* [[SCEVGEP]], [[A]] 288; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] 289; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] 290; CHECK: vector.ph: 291; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[SMAX]], 9223372036854775804 292; CHECK-NEXT: [[BROADCAST_SPLATINSERT5:%.*]] = insertelement <4 x i32> poison, i32 [[NTRUNC]], i32 0 293; CHECK-NEXT: [[BROADCAST_SPLAT6:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT5]], <4 x i32> poison, <4 x i32> zeroinitializer 294; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i1> undef, i1 [[CMP]], i32 3 295; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> poison, i32 [[K]], i32 3 296; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP2]], <4 x i32> [[BROADCAST_SPLAT6]], <4 x i32> [[TMP3]] 297; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[PREDPHI]], i32 3 298; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 299; CHECK: vector.body: 300; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 301; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 [[INDEX]] 302; CHECK-NEXT: [[TMP7:%.*]] = bitcast i32* [[TMP6]] to <4 x i32>* 303; CHECK-NEXT: store <4 x i32> [[BROADCAST_SPLAT6]], <4 x i32>* [[TMP7]], align 4 304; CHECK-NEXT: store i32 [[TMP5]], i32* [[A]], align 4 305; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4 306; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 307; CHECK-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]] 308; CHECK: middle.block: 309; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[SMAX]], [[N_VEC]] 310; CHECK-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[SCALAR_PH]] 311; CHECK: scalar.ph: 312; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_MEMCHECK]] ] 313; CHECK-NEXT: br label [[FOR_BODY:%.*]] 314; CHECK: for.body: 315; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_NEXT:%.*]], [[LATCH:%.*]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] 316; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 [[I]] 317; CHECK-NEXT: store i32 [[NTRUNC]], i32* [[TMP1]], align 4 318; CHECK-NEXT: br i1 [[CMP]], label [[COND_STORE:%.*]], label [[COND_STORE_K:%.*]] 319; CHECK: cond_store: 320; CHECK-NEXT: br label [[LATCH]] 321; CHECK: cond_store_k: 322; CHECK-NEXT: br label [[LATCH]] 323; CHECK: latch: 324; CHECK-NEXT: [[STOREVAL:%.*]] = phi i32 [ [[NTRUNC]], [[COND_STORE]] ], [ [[K]], [[COND_STORE_K]] ] 325; CHECK-NEXT: store i32 [[STOREVAL]], i32* [[A]], align 4 326; CHECK-NEXT: [[I_NEXT]] = add nuw nsw i64 [[I]], 1 327; CHECK-NEXT: [[COND:%.*]] = icmp slt i64 [[I_NEXT]], [[N]] 328; CHECK-NEXT: br i1 [[COND]], label [[FOR_BODY]], label [[FOR_END_LOOPEXIT:%.*]] 329; CHECK: for.end.loopexit: 330; CHECK-NEXT: br label [[FOR_END]] 331; CHECK: for.end: 332; CHECK-NEXT: ret void 333; 334define void @inv_val_store_to_inv_address_conditional_inv(i32* %a, i64 %n, i32* %b, i32 %k) { 335entry: 336 %ntrunc = trunc i64 %n to i32 337 %cmp = icmp eq i32 %ntrunc, %k 338 br label %for.body 339 340for.body: ; preds = %for.body, %entry 341 %i = phi i64 [ %i.next, %latch ], [ 0, %entry ] 342 %tmp1 = getelementptr inbounds i32, i32* %b, i64 %i 343 %tmp2 = load i32, i32* %tmp1, align 8 344 store i32 %ntrunc, i32* %tmp1 345 br i1 %cmp, label %cond_store, label %cond_store_k 346 347cond_store: 348 br label %latch 349 350cond_store_k: 351 br label %latch 352 353latch: 354 %storeval = phi i32 [ %ntrunc, %cond_store ], [ %k, %cond_store_k ] 355 store i32 %storeval, i32* %a 356 %i.next = add nuw nsw i64 %i, 1 357 %cond = icmp slt i64 %i.next, %n 358 br i1 %cond, label %for.body, label %for.end 359 360for.end: ; preds = %for.body 361 ret void 362} 363 364; variant value stored to uniform address tests that the code gen extracts the 365; last element from the variant vector and scalar stores it into the uniform 366; address. 367; CHECK-LABEL: variant_val_store_to_inv_address 368; CHECK-NEXT: entry: 369; CHECK-NEXT: [[TMP0:%.*]] = icmp sgt i64 [[N:%.*]], 1 370; CHECK-NEXT: [[SMAX:%.*]] = select i1 [[TMP0]], i64 [[N]], i64 1 371; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[SMAX]], 4 372; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]] 373; CHECK: vector.memcheck: 374; CHECK-NEXT: [[B2:%.*]] = bitcast i32* [[B:%.*]] to i8* 375; CHECK-NEXT: [[A1:%.*]] = bitcast i32* [[A:%.*]] to i8* 376; CHECK-NEXT: [[UGLYGEP:%.*]] = getelementptr i8, i8* [[A1]], i64 1 377; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i64 [[N]], 1 378; CHECK-NEXT: [[SMAX3:%.*]] = select i1 [[TMP1]], i64 [[N]], i64 1 379; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i32, i32* [[B]], i64 [[SMAX3]] 380; CHECK-NEXT: [[BOUND0:%.*]] = icmp ugt i32* [[SCEVGEP]], [[A]] 381; CHECK-NEXT: [[BOUND1:%.*]] = icmp ugt i8* [[UGLYGEP]], [[B2]] 382; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] 383; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] 384; CHECK: vector.ph: 385; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[SMAX]], 9223372036854775804 386; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 387; CHECK: vector.body: 388; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 389; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP5:%.*]], [[VECTOR_BODY]] ] 390; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 [[INDEX]] 391; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32* [[TMP2]] to <4 x i32>* 392; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, <4 x i32>* [[TMP3]], align 8 393; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[WIDE_LOAD]], i32 3 394; CHECK-NEXT: store i32 [[TMP4]], i32* [[A]], align 4 395; CHECK-NEXT: [[TMP5]] = add <4 x i32> [[VEC_PHI]], [[WIDE_LOAD]] 396; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4 397; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 398; CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]] 399; CHECK: middle.block: 400; CHECK-NEXT: [[DOTLCSSA:%.*]] = phi <4 x i32> [ [[TMP5]], [[VECTOR_BODY]] ] 401; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x i32> [[DOTLCSSA]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef> 402; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[DOTLCSSA]], [[RDX_SHUF]] 403; CHECK-NEXT: [[RDX_SHUF5:%.*]] = shufflevector <4 x i32> [[BIN_RDX]], <4 x i32> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> 404; CHECK-NEXT: [[BIN_RDX6:%.*]] = add <4 x i32> [[BIN_RDX]], [[RDX_SHUF5]] 405; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i32> [[BIN_RDX6]], i32 0 406; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[SMAX]], [[N_VEC]] 407; CHECK-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[SCALAR_PH]] 408; CHECK: scalar.ph: 409; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_MEMCHECK]] ] 410; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP7]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ], [ 0, [[VECTOR_MEMCHECK]] ] 411; CHECK-NEXT: br label [[FOR_BODY:%.*]] 412; CHECK: for.body: 413; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_NEXT:%.*]], [[FOR_BODY]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] 414; CHECK-NEXT: [[TMP0:%.*]] = phi i32 [ [[TMP3:%.*]], [[FOR_BODY]] ], [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ] 415; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 [[I]] 416; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 8 417; CHECK-NEXT: store i32 [[TMP2]], i32* [[A]], align 4 418; CHECK-NEXT: [[TMP3]] = add i32 [[TMP0]], [[TMP2]] 419; CHECK-NEXT: [[I_NEXT]] = add nuw nsw i64 [[I]], 1 420; CHECK-NEXT: [[COND:%.*]] = icmp slt i64 [[I_NEXT]], [[N]] 421; CHECK-NEXT: br i1 [[COND]], label [[FOR_BODY]], label [[FOR_END_LOOPEXIT:%.*]] 422; CHECK: for.end.loopexit: 423; CHECK-NEXT: [[TMP3_LCSSA:%.*]] = phi i32 [ [[TMP3]], [[FOR_BODY]] ] 424; CHECK-NEXT: br label [[FOR_END]] 425define i32 @variant_val_store_to_inv_address(i32* %a, i64 %n, i32* %b, i32 %k) { 426entry: 427 %ntrunc = trunc i64 %n to i32 428 %cmp = icmp eq i32 %ntrunc, %k 429 br label %for.body 430 431for.body: ; preds = %for.body, %entry 432 %i = phi i64 [ %i.next, %for.body ], [ 0, %entry ] 433 %tmp0 = phi i32 [ %tmp3, %for.body ], [ 0, %entry ] 434 %tmp1 = getelementptr inbounds i32, i32* %b, i64 %i 435 %tmp2 = load i32, i32* %tmp1, align 8 436 store i32 %tmp2, i32* %a 437 %tmp3 = add i32 %tmp0, %tmp2 438 %i.next = add nuw nsw i64 %i, 1 439 %cond = icmp slt i64 %i.next, %n 440 br i1 %cond, label %for.body, label %for.end 441 442for.end: ; preds = %for.body 443 %rdx.lcssa = phi i32 [ %tmp3, %for.body ] 444 ret i32 %rdx.lcssa 445} 446 447; Multiple variant stores to the same uniform address 448; We do not vectorize such loops currently. 449; for(; i < itr; i++) { 450; for(; j < itr; j++) { 451; var1[i] = var2[j] + var1[i]; 452; var1[i]++; 453; } 454; } 455 456; CHECK-LABEL: multiple_uniform_stores 457; CHECK-NOT: <4 x i32> 458define i32 @multiple_uniform_stores(i32* nocapture %var1, i32* nocapture readonly %var2, i32 %itr) #0 { 459entry: 460 %cmp20 = icmp eq i32 %itr, 0 461 br i1 %cmp20, label %for.end10, label %for.cond1.preheader 462 463for.cond1.preheader: ; preds = %entry, %for.inc8 464 %indvars.iv23 = phi i64 [ %indvars.iv.next24, %for.inc8 ], [ 0, %entry ] 465 %j.022 = phi i32 [ %j.1.lcssa, %for.inc8 ], [ 0, %entry ] 466 %cmp218 = icmp ult i32 %j.022, %itr 467 br i1 %cmp218, label %for.body3.lr.ph, label %for.inc8 468 469for.body3.lr.ph: ; preds = %for.cond1.preheader 470 %arrayidx5 = getelementptr inbounds i32, i32* %var1, i64 %indvars.iv23 471 %0 = zext i32 %j.022 to i64 472 br label %for.body3 473 474for.body3: ; preds = %for.body3, %for.body3.lr.ph 475 %indvars.iv = phi i64 [ %0, %for.body3.lr.ph ], [ %indvars.iv.next, %for.body3 ] 476 %arrayidx = getelementptr inbounds i32, i32* %var2, i64 %indvars.iv 477 %1 = load i32, i32* %arrayidx, align 4 478 %2 = load i32, i32* %arrayidx5, align 4 479 %add = add nsw i32 %2, %1 480 store i32 %add, i32* %arrayidx5, align 4 481 %3 = load i32, i32* %arrayidx5, align 4 482 %4 = add nsw i32 %3, 1 483 store i32 %4, i32* %arrayidx5, align 4 484 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 485 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 486 %exitcond = icmp eq i32 %lftr.wideiv, %itr 487 br i1 %exitcond, label %for.inc8, label %for.body3 488 489for.inc8: ; preds = %for.body3, %for.cond1.preheader 490 %j.1.lcssa = phi i32 [ %j.022, %for.cond1.preheader ], [ %itr, %for.body3 ] 491 %indvars.iv.next24 = add nuw nsw i64 %indvars.iv23, 1 492 %lftr.wideiv25 = trunc i64 %indvars.iv.next24 to i32 493 %exitcond26 = icmp eq i32 %lftr.wideiv25, %itr 494 br i1 %exitcond26, label %for.end10, label %for.cond1.preheader 495 496for.end10: ; preds = %for.inc8, %entry 497 ret i32 undef 498} 499 500; second uniform store to the same address is conditional. 501; we do not vectorize this. 502; CHECK-LABEL: multiple_uniform_stores_conditional 503; CHECK-NOT: <4 x i32> 504define i32 @multiple_uniform_stores_conditional(i32* nocapture %var1, i32* nocapture readonly %var2, i32 %itr) #0 { 505entry: 506 %cmp20 = icmp eq i32 %itr, 0 507 br i1 %cmp20, label %for.end10, label %for.cond1.preheader 508 509for.cond1.preheader: ; preds = %entry, %for.inc8 510 %indvars.iv23 = phi i64 [ %indvars.iv.next24, %for.inc8 ], [ 0, %entry ] 511 %j.022 = phi i32 [ %j.1.lcssa, %for.inc8 ], [ 0, %entry ] 512 %cmp218 = icmp ult i32 %j.022, %itr 513 br i1 %cmp218, label %for.body3.lr.ph, label %for.inc8 514 515for.body3.lr.ph: ; preds = %for.cond1.preheader 516 %arrayidx5 = getelementptr inbounds i32, i32* %var1, i64 %indvars.iv23 517 %0 = zext i32 %j.022 to i64 518 br label %for.body3 519 520for.body3: ; preds = %for.body3, %for.body3.lr.ph 521 %indvars.iv = phi i64 [ %0, %for.body3.lr.ph ], [ %indvars.iv.next, %latch ] 522 %arrayidx = getelementptr inbounds i32, i32* %var2, i64 %indvars.iv 523 %1 = load i32, i32* %arrayidx, align 4 524 %2 = load i32, i32* %arrayidx5, align 4 525 %add = add nsw i32 %2, %1 526 store i32 %add, i32* %arrayidx5, align 4 527 %3 = load i32, i32* %arrayidx5, align 4 528 %4 = add nsw i32 %3, 1 529 %5 = icmp ugt i32 %3, 42 530 br i1 %5, label %cond_store, label %latch 531 532cond_store: 533 store i32 %4, i32* %arrayidx5, align 4 534 br label %latch 535 536latch: 537 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 538 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 539 %exitcond = icmp eq i32 %lftr.wideiv, %itr 540 br i1 %exitcond, label %for.inc8, label %for.body3 541 542for.inc8: ; preds = %for.body3, %for.cond1.preheader 543 %j.1.lcssa = phi i32 [ %j.022, %for.cond1.preheader ], [ %itr, %latch ] 544 %indvars.iv.next24 = add nuw nsw i64 %indvars.iv23, 1 545 %lftr.wideiv25 = trunc i64 %indvars.iv.next24 to i32 546 %exitcond26 = icmp eq i32 %lftr.wideiv25, %itr 547 br i1 %exitcond26, label %for.end10, label %for.cond1.preheader 548 549for.end10: ; preds = %for.inc8, %entry 550 ret i32 undef 551} 552 553; cannot vectorize loop with unsafe dependency between uniform load (%tmp10) and store 554; (%tmp12) to the same address 555; PR39653 556; Note: %tmp10 could be replaced by phi(%arg4, %tmp12), a potentially vectorizable 557; 1st-order-recurrence 558define void @unsafe_dep_uniform_load_store(i32 %arg, i32 %arg1, i64 %arg2, i16* %arg3, i32 %arg4, i64 %arg5) { 559; CHECK-LABEL: unsafe_dep_uniform_load_store 560; CHECK-NOT: <4 x i32> 561bb: 562 %tmp = alloca i32 563 store i32 %arg4, i32* %tmp 564 %tmp6 = getelementptr inbounds i16, i16* %arg3, i64 %arg5 565 br label %bb7 566 567bb7: 568 %tmp8 = phi i64 [ 0, %bb ], [ %tmp24, %bb7 ] 569 %tmp9 = phi i32 [ %arg1, %bb ], [ %tmp23, %bb7 ] 570 %tmp10 = load i32, i32* %tmp 571 %tmp11 = mul nsw i32 %tmp9, %tmp10 572 %tmp12 = srem i32 %tmp11, 65536 573 %tmp13 = add nsw i32 %tmp12, %tmp9 574 %tmp14 = trunc i32 %tmp13 to i16 575 %tmp15 = trunc i64 %tmp8 to i32 576 %tmp16 = add i32 %arg, %tmp15 577 %tmp17 = zext i32 %tmp16 to i64 578 %tmp18 = getelementptr inbounds i16, i16* %tmp6, i64 %tmp17 579 store i16 %tmp14, i16* %tmp18, align 2 580 %tmp19 = add i32 %tmp13, %tmp9 581 %tmp20 = trunc i32 %tmp19 to i16 582 %tmp21 = and i16 %tmp20, 255 583 %tmp22 = getelementptr inbounds i16, i16* %arg3, i64 %tmp17 584 store i16 %tmp21, i16* %tmp22, align 2 585 %tmp23 = add nsw i32 %tmp9, 1 586 %tmp24 = add nuw nsw i64 %tmp8, 1 587 %tmp25 = icmp eq i64 %tmp24, %arg2 588 store i32 %tmp12, i32* %tmp 589 br i1 %tmp25, label %bb26, label %bb7 590 591bb26: 592 ret void 593} 594