1 //===- SubtargetEmitter.cpp - Generate subtarget enumerations -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This tablegen backend emits subtarget enumerations.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "CodeGenTarget.h"
14 #include "CodeGenSchedule.h"
15 #include "PredicateExpander.h"
16 #include "llvm/ADT/SmallPtrSet.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/ADT/StringRef.h"
20 #include "llvm/MC/MCInstrItineraries.h"
21 #include "llvm/MC/MCSchedule.h"
22 #include "llvm/MC/SubtargetFeature.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/Format.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/TableGen/Error.h"
27 #include "llvm/TableGen/Record.h"
28 #include "llvm/TableGen/TableGenBackend.h"
29 #include <algorithm>
30 #include <cassert>
31 #include <cstdint>
32 #include <iterator>
33 #include <map>
34 #include <string>
35 #include <vector>
36
37 using namespace llvm;
38
39 #define DEBUG_TYPE "subtarget-emitter"
40
41 namespace {
42
43 class SubtargetEmitter {
44 // Each processor has a SchedClassDesc table with an entry for each SchedClass.
45 // The SchedClassDesc table indexes into a global write resource table, write
46 // latency table, and read advance table.
47 struct SchedClassTables {
48 std::vector<std::vector<MCSchedClassDesc>> ProcSchedClasses;
49 std::vector<MCWriteProcResEntry> WriteProcResources;
50 std::vector<MCWriteLatencyEntry> WriteLatencies;
51 std::vector<std::string> WriterNames;
52 std::vector<MCReadAdvanceEntry> ReadAdvanceEntries;
53
54 // Reserve an invalid entry at index 0
SchedClassTables__anon9a07613e0111::SubtargetEmitter::SchedClassTables55 SchedClassTables() {
56 ProcSchedClasses.resize(1);
57 WriteProcResources.resize(1);
58 WriteLatencies.resize(1);
59 WriterNames.push_back("InvalidWrite");
60 ReadAdvanceEntries.resize(1);
61 }
62 };
63
64 struct LessWriteProcResources {
operator ()__anon9a07613e0111::SubtargetEmitter::LessWriteProcResources65 bool operator()(const MCWriteProcResEntry &LHS,
66 const MCWriteProcResEntry &RHS) {
67 return LHS.ProcResourceIdx < RHS.ProcResourceIdx;
68 }
69 };
70
71 const CodeGenTarget &TGT;
72 RecordKeeper &Records;
73 CodeGenSchedModels &SchedModels;
74 std::string Target;
75
76 void Enumeration(raw_ostream &OS, DenseMap<Record *, unsigned> &FeatureMap);
77 unsigned FeatureKeyValues(raw_ostream &OS,
78 const DenseMap<Record *, unsigned> &FeatureMap);
79 unsigned CPUKeyValues(raw_ostream &OS,
80 const DenseMap<Record *, unsigned> &FeatureMap);
81 void FormItineraryStageString(const std::string &Names,
82 Record *ItinData, std::string &ItinString,
83 unsigned &NStages);
84 void FormItineraryOperandCycleString(Record *ItinData, std::string &ItinString,
85 unsigned &NOperandCycles);
86 void FormItineraryBypassString(const std::string &Names,
87 Record *ItinData,
88 std::string &ItinString, unsigned NOperandCycles);
89 void EmitStageAndOperandCycleData(raw_ostream &OS,
90 std::vector<std::vector<InstrItinerary>>
91 &ProcItinLists);
92 void EmitItineraries(raw_ostream &OS,
93 std::vector<std::vector<InstrItinerary>>
94 &ProcItinLists);
95 unsigned EmitRegisterFileTables(const CodeGenProcModel &ProcModel,
96 raw_ostream &OS);
97 void EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,
98 raw_ostream &OS);
99 void EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel,
100 raw_ostream &OS);
101 void EmitProcessorProp(raw_ostream &OS, const Record *R, StringRef Name,
102 char Separator);
103 void EmitProcessorResourceSubUnits(const CodeGenProcModel &ProcModel,
104 raw_ostream &OS);
105 void EmitProcessorResources(const CodeGenProcModel &ProcModel,
106 raw_ostream &OS);
107 Record *FindWriteResources(const CodeGenSchedRW &SchedWrite,
108 const CodeGenProcModel &ProcModel);
109 Record *FindReadAdvance(const CodeGenSchedRW &SchedRead,
110 const CodeGenProcModel &ProcModel);
111 void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
112 const CodeGenProcModel &ProcModel);
113 void GenSchedClassTables(const CodeGenProcModel &ProcModel,
114 SchedClassTables &SchedTables);
115 void EmitSchedClassTables(SchedClassTables &SchedTables, raw_ostream &OS);
116 void EmitProcessorModels(raw_ostream &OS);
117 void EmitSchedModelHelpers(const std::string &ClassName, raw_ostream &OS);
118 void emitSchedModelHelpersImpl(raw_ostream &OS,
119 bool OnlyExpandMCInstPredicates = false);
120 void emitGenMCSubtargetInfo(raw_ostream &OS);
121 void EmitMCInstrAnalysisPredicateFunctions(raw_ostream &OS);
122
123 void EmitSchedModel(raw_ostream &OS);
124 void EmitHwModeCheck(const std::string &ClassName, raw_ostream &OS);
125 void ParseFeaturesFunction(raw_ostream &OS, unsigned NumFeatures,
126 unsigned NumProcs);
127
128 public:
SubtargetEmitter(RecordKeeper & R,CodeGenTarget & TGT)129 SubtargetEmitter(RecordKeeper &R, CodeGenTarget &TGT)
130 : TGT(TGT), Records(R), SchedModels(TGT.getSchedModels()),
131 Target(TGT.getName()) {}
132
133 void run(raw_ostream &o);
134 };
135
136 } // end anonymous namespace
137
138 //
139 // Enumeration - Emit the specified class as an enumeration.
140 //
Enumeration(raw_ostream & OS,DenseMap<Record *,unsigned> & FeatureMap)141 void SubtargetEmitter::Enumeration(raw_ostream &OS,
142 DenseMap<Record *, unsigned> &FeatureMap) {
143 // Get all records of class and sort
144 std::vector<Record*> DefList =
145 Records.getAllDerivedDefinitions("SubtargetFeature");
146 llvm::sort(DefList, LessRecord());
147
148 unsigned N = DefList.size();
149 if (N == 0)
150 return;
151 if (N + 1 > MAX_SUBTARGET_FEATURES)
152 PrintFatalError("Too many subtarget features! Bump MAX_SUBTARGET_FEATURES.");
153
154 OS << "namespace " << Target << " {\n";
155
156 // Open enumeration.
157 OS << "enum {\n";
158
159 // For each record
160 for (unsigned i = 0; i < N; ++i) {
161 // Next record
162 Record *Def = DefList[i];
163
164 // Get and emit name
165 OS << " " << Def->getName() << " = " << i << ",\n";
166
167 // Save the index for this feature.
168 FeatureMap[Def] = i;
169 }
170
171 OS << " "
172 << "NumSubtargetFeatures = " << N << "\n";
173
174 // Close enumeration and namespace
175 OS << "};\n";
176 OS << "} // end namespace " << Target << "\n";
177 }
178
printFeatureMask(raw_ostream & OS,RecVec & FeatureList,const DenseMap<Record *,unsigned> & FeatureMap)179 static void printFeatureMask(raw_ostream &OS, RecVec &FeatureList,
180 const DenseMap<Record *, unsigned> &FeatureMap) {
181 std::array<uint64_t, MAX_SUBTARGET_WORDS> Mask = {};
182 for (unsigned j = 0, M = FeatureList.size(); j < M; ++j) {
183 unsigned Bit = FeatureMap.lookup(FeatureList[j]);
184 Mask[Bit / 64] |= 1ULL << (Bit % 64);
185 }
186
187 OS << "{ { { ";
188 for (unsigned i = 0; i != Mask.size(); ++i) {
189 OS << "0x";
190 OS.write_hex(Mask[i]);
191 OS << "ULL, ";
192 }
193 OS << "} } }";
194 }
195
196 //
197 // FeatureKeyValues - Emit data of all the subtarget features. Used by the
198 // command line.
199 //
FeatureKeyValues(raw_ostream & OS,const DenseMap<Record *,unsigned> & FeatureMap)200 unsigned SubtargetEmitter::FeatureKeyValues(
201 raw_ostream &OS, const DenseMap<Record *, unsigned> &FeatureMap) {
202 // Gather and sort all the features
203 std::vector<Record*> FeatureList =
204 Records.getAllDerivedDefinitions("SubtargetFeature");
205
206 if (FeatureList.empty())
207 return 0;
208
209 llvm::sort(FeatureList, LessRecordFieldName());
210
211 // Begin feature table
212 OS << "// Sorted (by key) array of values for CPU features.\n"
213 << "extern const llvm::SubtargetFeatureKV " << Target
214 << "FeatureKV[] = {\n";
215
216 // For each feature
217 unsigned NumFeatures = 0;
218 for (unsigned i = 0, N = FeatureList.size(); i < N; ++i) {
219 // Next feature
220 Record *Feature = FeatureList[i];
221
222 StringRef Name = Feature->getName();
223 StringRef CommandLineName = Feature->getValueAsString("Name");
224 StringRef Desc = Feature->getValueAsString("Desc");
225
226 if (CommandLineName.empty()) continue;
227
228 // Emit as { "feature", "description", { featureEnum }, { i1 , i2 , ... , in } }
229 OS << " { "
230 << "\"" << CommandLineName << "\", "
231 << "\"" << Desc << "\", "
232 << Target << "::" << Name << ", ";
233
234 RecVec ImpliesList = Feature->getValueAsListOfDefs("Implies");
235
236 printFeatureMask(OS, ImpliesList, FeatureMap);
237
238 OS << " },\n";
239 ++NumFeatures;
240 }
241
242 // End feature table
243 OS << "};\n";
244
245 return NumFeatures;
246 }
247
248 //
249 // CPUKeyValues - Emit data of all the subtarget processors. Used by command
250 // line.
251 //
252 unsigned
CPUKeyValues(raw_ostream & OS,const DenseMap<Record *,unsigned> & FeatureMap)253 SubtargetEmitter::CPUKeyValues(raw_ostream &OS,
254 const DenseMap<Record *, unsigned> &FeatureMap) {
255 // Gather and sort processor information
256 std::vector<Record*> ProcessorList =
257 Records.getAllDerivedDefinitions("Processor");
258 llvm::sort(ProcessorList, LessRecordFieldName());
259
260 // Begin processor table
261 OS << "// Sorted (by key) array of values for CPU subtype.\n"
262 << "extern const llvm::SubtargetSubTypeKV " << Target
263 << "SubTypeKV[] = {\n";
264
265 // For each processor
266 for (Record *Processor : ProcessorList) {
267 StringRef Name = Processor->getValueAsString("Name");
268 RecVec FeatureList = Processor->getValueAsListOfDefs("Features");
269 RecVec TuneFeatureList = Processor->getValueAsListOfDefs("TuneFeatures");
270
271 // Emit as { "cpu", "description", 0, { f1 , f2 , ... fn } },
272 OS << " { "
273 << "\"" << Name << "\", ";
274
275 printFeatureMask(OS, FeatureList, FeatureMap);
276 OS << ", ";
277 printFeatureMask(OS, TuneFeatureList, FeatureMap);
278
279 // Emit the scheduler model pointer.
280 const std::string &ProcModelName =
281 SchedModels.getModelForProc(Processor).ModelName;
282 OS << ", &" << ProcModelName << " },\n";
283 }
284
285 // End processor table
286 OS << "};\n";
287
288 return ProcessorList.size();
289 }
290
291 //
292 // FormItineraryStageString - Compose a string containing the stage
293 // data initialization for the specified itinerary. N is the number
294 // of stages.
295 //
FormItineraryStageString(const std::string & Name,Record * ItinData,std::string & ItinString,unsigned & NStages)296 void SubtargetEmitter::FormItineraryStageString(const std::string &Name,
297 Record *ItinData,
298 std::string &ItinString,
299 unsigned &NStages) {
300 // Get states list
301 RecVec StageList = ItinData->getValueAsListOfDefs("Stages");
302
303 // For each stage
304 unsigned N = NStages = StageList.size();
305 for (unsigned i = 0; i < N;) {
306 // Next stage
307 const Record *Stage = StageList[i];
308
309 // Form string as ,{ cycles, u1 | u2 | ... | un, timeinc, kind }
310 int Cycles = Stage->getValueAsInt("Cycles");
311 ItinString += " { " + itostr(Cycles) + ", ";
312
313 // Get unit list
314 RecVec UnitList = Stage->getValueAsListOfDefs("Units");
315
316 // For each unit
317 for (unsigned j = 0, M = UnitList.size(); j < M;) {
318 // Add name and bitwise or
319 ItinString += Name + "FU::" + UnitList[j]->getName().str();
320 if (++j < M) ItinString += " | ";
321 }
322
323 int TimeInc = Stage->getValueAsInt("TimeInc");
324 ItinString += ", " + itostr(TimeInc);
325
326 int Kind = Stage->getValueAsInt("Kind");
327 ItinString += ", (llvm::InstrStage::ReservationKinds)" + itostr(Kind);
328
329 // Close off stage
330 ItinString += " }";
331 if (++i < N) ItinString += ", ";
332 }
333 }
334
335 //
336 // FormItineraryOperandCycleString - Compose a string containing the
337 // operand cycle initialization for the specified itinerary. N is the
338 // number of operands that has cycles specified.
339 //
FormItineraryOperandCycleString(Record * ItinData,std::string & ItinString,unsigned & NOperandCycles)340 void SubtargetEmitter::FormItineraryOperandCycleString(Record *ItinData,
341 std::string &ItinString, unsigned &NOperandCycles) {
342 // Get operand cycle list
343 std::vector<int64_t> OperandCycleList =
344 ItinData->getValueAsListOfInts("OperandCycles");
345
346 // For each operand cycle
347 unsigned N = NOperandCycles = OperandCycleList.size();
348 for (unsigned i = 0; i < N;) {
349 // Next operand cycle
350 const int OCycle = OperandCycleList[i];
351
352 ItinString += " " + itostr(OCycle);
353 if (++i < N) ItinString += ", ";
354 }
355 }
356
FormItineraryBypassString(const std::string & Name,Record * ItinData,std::string & ItinString,unsigned NOperandCycles)357 void SubtargetEmitter::FormItineraryBypassString(const std::string &Name,
358 Record *ItinData,
359 std::string &ItinString,
360 unsigned NOperandCycles) {
361 RecVec BypassList = ItinData->getValueAsListOfDefs("Bypasses");
362 unsigned N = BypassList.size();
363 unsigned i = 0;
364 for (; i < N;) {
365 ItinString += Name + "Bypass::" + BypassList[i]->getName().str();
366 if (++i < NOperandCycles) ItinString += ", ";
367 }
368 for (; i < NOperandCycles;) {
369 ItinString += " 0";
370 if (++i < NOperandCycles) ItinString += ", ";
371 }
372 }
373
374 //
375 // EmitStageAndOperandCycleData - Generate unique itinerary stages and operand
376 // cycle tables. Create a list of InstrItinerary objects (ProcItinLists) indexed
377 // by CodeGenSchedClass::Index.
378 //
379 void SubtargetEmitter::
EmitStageAndOperandCycleData(raw_ostream & OS,std::vector<std::vector<InstrItinerary>> & ProcItinLists)380 EmitStageAndOperandCycleData(raw_ostream &OS,
381 std::vector<std::vector<InstrItinerary>>
382 &ProcItinLists) {
383 // Multiple processor models may share an itinerary record. Emit it once.
384 SmallPtrSet<Record*, 8> ItinsDefSet;
385
386 // Emit functional units for all the itineraries.
387 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) {
388
389 if (!ItinsDefSet.insert(ProcModel.ItinsDef).second)
390 continue;
391
392 RecVec FUs = ProcModel.ItinsDef->getValueAsListOfDefs("FU");
393 if (FUs.empty())
394 continue;
395
396 StringRef Name = ProcModel.ItinsDef->getName();
397 OS << "\n// Functional units for \"" << Name << "\"\n"
398 << "namespace " << Name << "FU {\n";
399
400 for (unsigned j = 0, FUN = FUs.size(); j < FUN; ++j)
401 OS << " const InstrStage::FuncUnits " << FUs[j]->getName()
402 << " = 1ULL << " << j << ";\n";
403
404 OS << "} // end namespace " << Name << "FU\n";
405
406 RecVec BPs = ProcModel.ItinsDef->getValueAsListOfDefs("BP");
407 if (!BPs.empty()) {
408 OS << "\n// Pipeline forwarding paths for itineraries \"" << Name
409 << "\"\n" << "namespace " << Name << "Bypass {\n";
410
411 OS << " const unsigned NoBypass = 0;\n";
412 for (unsigned j = 0, BPN = BPs.size(); j < BPN; ++j)
413 OS << " const unsigned " << BPs[j]->getName()
414 << " = 1 << " << j << ";\n";
415
416 OS << "} // end namespace " << Name << "Bypass\n";
417 }
418 }
419
420 // Begin stages table
421 std::string StageTable = "\nextern const llvm::InstrStage " + Target +
422 "Stages[] = {\n";
423 StageTable += " { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary\n";
424
425 // Begin operand cycle table
426 std::string OperandCycleTable = "extern const unsigned " + Target +
427 "OperandCycles[] = {\n";
428 OperandCycleTable += " 0, // No itinerary\n";
429
430 // Begin pipeline bypass table
431 std::string BypassTable = "extern const unsigned " + Target +
432 "ForwardingPaths[] = {\n";
433 BypassTable += " 0, // No itinerary\n";
434
435 // For each Itinerary across all processors, add a unique entry to the stages,
436 // operand cycles, and pipeline bypass tables. Then add the new Itinerary
437 // object with computed offsets to the ProcItinLists result.
438 unsigned StageCount = 1, OperandCycleCount = 1;
439 std::map<std::string, unsigned> ItinStageMap, ItinOperandMap;
440 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) {
441 // Add process itinerary to the list.
442 ProcItinLists.resize(ProcItinLists.size()+1);
443
444 // If this processor defines no itineraries, then leave the itinerary list
445 // empty.
446 std::vector<InstrItinerary> &ItinList = ProcItinLists.back();
447 if (!ProcModel.hasItineraries())
448 continue;
449
450 StringRef Name = ProcModel.ItinsDef->getName();
451
452 ItinList.resize(SchedModels.numInstrSchedClasses());
453 assert(ProcModel.ItinDefList.size() == ItinList.size() && "bad Itins");
454
455 for (unsigned SchedClassIdx = 0, SchedClassEnd = ItinList.size();
456 SchedClassIdx < SchedClassEnd; ++SchedClassIdx) {
457
458 // Next itinerary data
459 Record *ItinData = ProcModel.ItinDefList[SchedClassIdx];
460
461 // Get string and stage count
462 std::string ItinStageString;
463 unsigned NStages = 0;
464 if (ItinData)
465 FormItineraryStageString(std::string(Name), ItinData, ItinStageString,
466 NStages);
467
468 // Get string and operand cycle count
469 std::string ItinOperandCycleString;
470 unsigned NOperandCycles = 0;
471 std::string ItinBypassString;
472 if (ItinData) {
473 FormItineraryOperandCycleString(ItinData, ItinOperandCycleString,
474 NOperandCycles);
475
476 FormItineraryBypassString(std::string(Name), ItinData, ItinBypassString,
477 NOperandCycles);
478 }
479
480 // Check to see if stage already exists and create if it doesn't
481 uint16_t FindStage = 0;
482 if (NStages > 0) {
483 FindStage = ItinStageMap[ItinStageString];
484 if (FindStage == 0) {
485 // Emit as { cycles, u1 | u2 | ... | un, timeinc }, // indices
486 StageTable += ItinStageString + ", // " + itostr(StageCount);
487 if (NStages > 1)
488 StageTable += "-" + itostr(StageCount + NStages - 1);
489 StageTable += "\n";
490 // Record Itin class number.
491 ItinStageMap[ItinStageString] = FindStage = StageCount;
492 StageCount += NStages;
493 }
494 }
495
496 // Check to see if operand cycle already exists and create if it doesn't
497 uint16_t FindOperandCycle = 0;
498 if (NOperandCycles > 0) {
499 std::string ItinOperandString = ItinOperandCycleString+ItinBypassString;
500 FindOperandCycle = ItinOperandMap[ItinOperandString];
501 if (FindOperandCycle == 0) {
502 // Emit as cycle, // index
503 OperandCycleTable += ItinOperandCycleString + ", // ";
504 std::string OperandIdxComment = itostr(OperandCycleCount);
505 if (NOperandCycles > 1)
506 OperandIdxComment += "-"
507 + itostr(OperandCycleCount + NOperandCycles - 1);
508 OperandCycleTable += OperandIdxComment + "\n";
509 // Record Itin class number.
510 ItinOperandMap[ItinOperandCycleString] =
511 FindOperandCycle = OperandCycleCount;
512 // Emit as bypass, // index
513 BypassTable += ItinBypassString + ", // " + OperandIdxComment + "\n";
514 OperandCycleCount += NOperandCycles;
515 }
516 }
517
518 // Set up itinerary as location and location + stage count
519 int16_t NumUOps = ItinData ? ItinData->getValueAsInt("NumMicroOps") : 0;
520 InstrItinerary Intinerary = {
521 NumUOps,
522 FindStage,
523 uint16_t(FindStage + NStages),
524 FindOperandCycle,
525 uint16_t(FindOperandCycle + NOperandCycles),
526 };
527
528 // Inject - empty slots will be 0, 0
529 ItinList[SchedClassIdx] = Intinerary;
530 }
531 }
532
533 // Closing stage
534 StageTable += " { 0, 0, 0, llvm::InstrStage::Required } // End stages\n";
535 StageTable += "};\n";
536
537 // Closing operand cycles
538 OperandCycleTable += " 0 // End operand cycles\n";
539 OperandCycleTable += "};\n";
540
541 BypassTable += " 0 // End bypass tables\n";
542 BypassTable += "};\n";
543
544 // Emit tables.
545 OS << StageTable;
546 OS << OperandCycleTable;
547 OS << BypassTable;
548 }
549
550 //
551 // EmitProcessorData - Generate data for processor itineraries that were
552 // computed during EmitStageAndOperandCycleData(). ProcItinLists lists all
553 // Itineraries for each processor. The Itinerary lists are indexed on
554 // CodeGenSchedClass::Index.
555 //
556 void SubtargetEmitter::
EmitItineraries(raw_ostream & OS,std::vector<std::vector<InstrItinerary>> & ProcItinLists)557 EmitItineraries(raw_ostream &OS,
558 std::vector<std::vector<InstrItinerary>> &ProcItinLists) {
559 // Multiple processor models may share an itinerary record. Emit it once.
560 SmallPtrSet<Record*, 8> ItinsDefSet;
561
562 // For each processor's machine model
563 std::vector<std::vector<InstrItinerary>>::iterator
564 ProcItinListsIter = ProcItinLists.begin();
565 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
566 PE = SchedModels.procModelEnd(); PI != PE; ++PI, ++ProcItinListsIter) {
567
568 Record *ItinsDef = PI->ItinsDef;
569 if (!ItinsDefSet.insert(ItinsDef).second)
570 continue;
571
572 // Get the itinerary list for the processor.
573 assert(ProcItinListsIter != ProcItinLists.end() && "bad iterator");
574 std::vector<InstrItinerary> &ItinList = *ProcItinListsIter;
575
576 // Empty itineraries aren't referenced anywhere in the tablegen output
577 // so don't emit them.
578 if (ItinList.empty())
579 continue;
580
581 OS << "\n";
582 OS << "static const llvm::InstrItinerary ";
583
584 // Begin processor itinerary table
585 OS << ItinsDef->getName() << "[] = {\n";
586
587 // For each itinerary class in CodeGenSchedClass::Index order.
588 for (unsigned j = 0, M = ItinList.size(); j < M; ++j) {
589 InstrItinerary &Intinerary = ItinList[j];
590
591 // Emit Itinerary in the form of
592 // { firstStage, lastStage, firstCycle, lastCycle } // index
593 OS << " { " <<
594 Intinerary.NumMicroOps << ", " <<
595 Intinerary.FirstStage << ", " <<
596 Intinerary.LastStage << ", " <<
597 Intinerary.FirstOperandCycle << ", " <<
598 Intinerary.LastOperandCycle << " }" <<
599 ", // " << j << " " << SchedModels.getSchedClass(j).Name << "\n";
600 }
601 // End processor itinerary table
602 OS << " { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }"
603 "// end marker\n";
604 OS << "};\n";
605 }
606 }
607
608 // Emit either the value defined in the TableGen Record, or the default
609 // value defined in the C++ header. The Record is null if the processor does not
610 // define a model.
EmitProcessorProp(raw_ostream & OS,const Record * R,StringRef Name,char Separator)611 void SubtargetEmitter::EmitProcessorProp(raw_ostream &OS, const Record *R,
612 StringRef Name, char Separator) {
613 OS << " ";
614 int V = R ? R->getValueAsInt(Name) : -1;
615 if (V >= 0)
616 OS << V << Separator << " // " << Name;
617 else
618 OS << "MCSchedModel::Default" << Name << Separator;
619 OS << '\n';
620 }
621
EmitProcessorResourceSubUnits(const CodeGenProcModel & ProcModel,raw_ostream & OS)622 void SubtargetEmitter::EmitProcessorResourceSubUnits(
623 const CodeGenProcModel &ProcModel, raw_ostream &OS) {
624 OS << "\nstatic const unsigned " << ProcModel.ModelName
625 << "ProcResourceSubUnits[] = {\n"
626 << " 0, // Invalid\n";
627
628 for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) {
629 Record *PRDef = ProcModel.ProcResourceDefs[i];
630 if (!PRDef->isSubClassOf("ProcResGroup"))
631 continue;
632 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources");
633 for (Record *RUDef : ResUnits) {
634 Record *const RU =
635 SchedModels.findProcResUnits(RUDef, ProcModel, PRDef->getLoc());
636 for (unsigned J = 0; J < RU->getValueAsInt("NumUnits"); ++J) {
637 OS << " " << ProcModel.getProcResourceIdx(RU) << ", ";
638 }
639 }
640 OS << " // " << PRDef->getName() << "\n";
641 }
642 OS << "};\n";
643 }
644
EmitRetireControlUnitInfo(const CodeGenProcModel & ProcModel,raw_ostream & OS)645 static void EmitRetireControlUnitInfo(const CodeGenProcModel &ProcModel,
646 raw_ostream &OS) {
647 int64_t ReorderBufferSize = 0, MaxRetirePerCycle = 0;
648 if (Record *RCU = ProcModel.RetireControlUnit) {
649 ReorderBufferSize =
650 std::max(ReorderBufferSize, RCU->getValueAsInt("ReorderBufferSize"));
651 MaxRetirePerCycle =
652 std::max(MaxRetirePerCycle, RCU->getValueAsInt("MaxRetirePerCycle"));
653 }
654
655 OS << ReorderBufferSize << ", // ReorderBufferSize\n ";
656 OS << MaxRetirePerCycle << ", // MaxRetirePerCycle\n ";
657 }
658
EmitRegisterFileInfo(const CodeGenProcModel & ProcModel,unsigned NumRegisterFiles,unsigned NumCostEntries,raw_ostream & OS)659 static void EmitRegisterFileInfo(const CodeGenProcModel &ProcModel,
660 unsigned NumRegisterFiles,
661 unsigned NumCostEntries, raw_ostream &OS) {
662 if (NumRegisterFiles)
663 OS << ProcModel.ModelName << "RegisterFiles,\n " << (1 + NumRegisterFiles);
664 else
665 OS << "nullptr,\n 0";
666
667 OS << ", // Number of register files.\n ";
668 if (NumCostEntries)
669 OS << ProcModel.ModelName << "RegisterCosts,\n ";
670 else
671 OS << "nullptr,\n ";
672 OS << NumCostEntries << ", // Number of register cost entries.\n";
673 }
674
675 unsigned
EmitRegisterFileTables(const CodeGenProcModel & ProcModel,raw_ostream & OS)676 SubtargetEmitter::EmitRegisterFileTables(const CodeGenProcModel &ProcModel,
677 raw_ostream &OS) {
678 if (llvm::all_of(ProcModel.RegisterFiles, [](const CodeGenRegisterFile &RF) {
679 return RF.hasDefaultCosts();
680 }))
681 return 0;
682
683 // Print the RegisterCost table first.
684 OS << "\n// {RegisterClassID, Register Cost, AllowMoveElimination }\n";
685 OS << "static const llvm::MCRegisterCostEntry " << ProcModel.ModelName
686 << "RegisterCosts"
687 << "[] = {\n";
688
689 for (const CodeGenRegisterFile &RF : ProcModel.RegisterFiles) {
690 // Skip register files with a default cost table.
691 if (RF.hasDefaultCosts())
692 continue;
693 // Add entries to the cost table.
694 for (const CodeGenRegisterCost &RC : RF.Costs) {
695 OS << " { ";
696 Record *Rec = RC.RCDef;
697 if (Rec->getValue("Namespace"))
698 OS << Rec->getValueAsString("Namespace") << "::";
699 OS << Rec->getName() << "RegClassID, " << RC.Cost << ", "
700 << RC.AllowMoveElimination << "},\n";
701 }
702 }
703 OS << "};\n";
704
705 // Now generate a table with register file info.
706 OS << "\n // {Name, #PhysRegs, #CostEntries, IndexToCostTbl, "
707 << "MaxMovesEliminatedPerCycle, AllowZeroMoveEliminationOnly }\n";
708 OS << "static const llvm::MCRegisterFileDesc " << ProcModel.ModelName
709 << "RegisterFiles"
710 << "[] = {\n"
711 << " { \"InvalidRegisterFile\", 0, 0, 0, 0, 0 },\n";
712 unsigned CostTblIndex = 0;
713
714 for (const CodeGenRegisterFile &RD : ProcModel.RegisterFiles) {
715 OS << " { ";
716 OS << '"' << RD.Name << '"' << ", " << RD.NumPhysRegs << ", ";
717 unsigned NumCostEntries = RD.Costs.size();
718 OS << NumCostEntries << ", " << CostTblIndex << ", "
719 << RD.MaxMovesEliminatedPerCycle << ", "
720 << RD.AllowZeroMoveEliminationOnly << "},\n";
721 CostTblIndex += NumCostEntries;
722 }
723 OS << "};\n";
724
725 return CostTblIndex;
726 }
727
EmitLoadStoreQueueInfo(const CodeGenProcModel & ProcModel,raw_ostream & OS)728 void SubtargetEmitter::EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,
729 raw_ostream &OS) {
730 unsigned QueueID = 0;
731 if (ProcModel.LoadQueue) {
732 const Record *Queue = ProcModel.LoadQueue->getValueAsDef("QueueDescriptor");
733 QueueID = 1 + std::distance(ProcModel.ProcResourceDefs.begin(),
734 find(ProcModel.ProcResourceDefs, Queue));
735 }
736 OS << " " << QueueID << ", // Resource Descriptor for the Load Queue\n";
737
738 QueueID = 0;
739 if (ProcModel.StoreQueue) {
740 const Record *Queue =
741 ProcModel.StoreQueue->getValueAsDef("QueueDescriptor");
742 QueueID = 1 + std::distance(ProcModel.ProcResourceDefs.begin(),
743 find(ProcModel.ProcResourceDefs, Queue));
744 }
745 OS << " " << QueueID << ", // Resource Descriptor for the Store Queue\n";
746 }
747
EmitExtraProcessorInfo(const CodeGenProcModel & ProcModel,raw_ostream & OS)748 void SubtargetEmitter::EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel,
749 raw_ostream &OS) {
750 // Generate a table of register file descriptors (one entry per each user
751 // defined register file), and a table of register costs.
752 unsigned NumCostEntries = EmitRegisterFileTables(ProcModel, OS);
753
754 // Now generate a table for the extra processor info.
755 OS << "\nstatic const llvm::MCExtraProcessorInfo " << ProcModel.ModelName
756 << "ExtraInfo = {\n ";
757
758 // Add information related to the retire control unit.
759 EmitRetireControlUnitInfo(ProcModel, OS);
760
761 // Add information related to the register files (i.e. where to find register
762 // file descriptors and register costs).
763 EmitRegisterFileInfo(ProcModel, ProcModel.RegisterFiles.size(),
764 NumCostEntries, OS);
765
766 // Add information about load/store queues.
767 EmitLoadStoreQueueInfo(ProcModel, OS);
768
769 OS << "};\n";
770 }
771
EmitProcessorResources(const CodeGenProcModel & ProcModel,raw_ostream & OS)772 void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel,
773 raw_ostream &OS) {
774 EmitProcessorResourceSubUnits(ProcModel, OS);
775
776 OS << "\n// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}\n";
777 OS << "static const llvm::MCProcResourceDesc " << ProcModel.ModelName
778 << "ProcResources"
779 << "[] = {\n"
780 << " {\"InvalidUnit\", 0, 0, 0, 0},\n";
781
782 unsigned SubUnitsOffset = 1;
783 for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) {
784 Record *PRDef = ProcModel.ProcResourceDefs[i];
785
786 Record *SuperDef = nullptr;
787 unsigned SuperIdx = 0;
788 unsigned NumUnits = 0;
789 const unsigned SubUnitsBeginOffset = SubUnitsOffset;
790 int BufferSize = PRDef->getValueAsInt("BufferSize");
791 if (PRDef->isSubClassOf("ProcResGroup")) {
792 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources");
793 for (Record *RU : ResUnits) {
794 NumUnits += RU->getValueAsInt("NumUnits");
795 SubUnitsOffset += RU->getValueAsInt("NumUnits");
796 }
797 }
798 else {
799 // Find the SuperIdx
800 if (PRDef->getValueInit("Super")->isComplete()) {
801 SuperDef =
802 SchedModels.findProcResUnits(PRDef->getValueAsDef("Super"),
803 ProcModel, PRDef->getLoc());
804 SuperIdx = ProcModel.getProcResourceIdx(SuperDef);
805 }
806 NumUnits = PRDef->getValueAsInt("NumUnits");
807 }
808 // Emit the ProcResourceDesc
809 OS << " {\"" << PRDef->getName() << "\", ";
810 if (PRDef->getName().size() < 15)
811 OS.indent(15 - PRDef->getName().size());
812 OS << NumUnits << ", " << SuperIdx << ", " << BufferSize << ", ";
813 if (SubUnitsBeginOffset != SubUnitsOffset) {
814 OS << ProcModel.ModelName << "ProcResourceSubUnits + "
815 << SubUnitsBeginOffset;
816 } else {
817 OS << "nullptr";
818 }
819 OS << "}, // #" << i+1;
820 if (SuperDef)
821 OS << ", Super=" << SuperDef->getName();
822 OS << "\n";
823 }
824 OS << "};\n";
825 }
826
827 // Find the WriteRes Record that defines processor resources for this
828 // SchedWrite.
FindWriteResources(const CodeGenSchedRW & SchedWrite,const CodeGenProcModel & ProcModel)829 Record *SubtargetEmitter::FindWriteResources(
830 const CodeGenSchedRW &SchedWrite, const CodeGenProcModel &ProcModel) {
831
832 // Check if the SchedWrite is already subtarget-specific and directly
833 // specifies a set of processor resources.
834 if (SchedWrite.TheDef->isSubClassOf("SchedWriteRes"))
835 return SchedWrite.TheDef;
836
837 Record *AliasDef = nullptr;
838 for (Record *A : SchedWrite.Aliases) {
839 const CodeGenSchedRW &AliasRW =
840 SchedModels.getSchedRW(A->getValueAsDef("AliasRW"));
841 if (AliasRW.TheDef->getValueInit("SchedModel")->isComplete()) {
842 Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");
843 if (&SchedModels.getProcModel(ModelDef) != &ProcModel)
844 continue;
845 }
846 if (AliasDef)
847 PrintFatalError(AliasRW.TheDef->getLoc(), "Multiple aliases "
848 "defined for processor " + ProcModel.ModelName +
849 " Ensure only one SchedAlias exists per RW.");
850 AliasDef = AliasRW.TheDef;
851 }
852 if (AliasDef && AliasDef->isSubClassOf("SchedWriteRes"))
853 return AliasDef;
854
855 // Check this processor's list of write resources.
856 Record *ResDef = nullptr;
857 for (Record *WR : ProcModel.WriteResDefs) {
858 if (!WR->isSubClassOf("WriteRes"))
859 continue;
860 if (AliasDef == WR->getValueAsDef("WriteType")
861 || SchedWrite.TheDef == WR->getValueAsDef("WriteType")) {
862 if (ResDef) {
863 PrintFatalError(WR->getLoc(), "Resources are defined for both "
864 "SchedWrite and its alias on processor " +
865 ProcModel.ModelName);
866 }
867 ResDef = WR;
868 }
869 }
870 // TODO: If ProcModel has a base model (previous generation processor),
871 // then call FindWriteResources recursively with that model here.
872 if (!ResDef) {
873 PrintFatalError(ProcModel.ModelDef->getLoc(),
874 Twine("Processor does not define resources for ") +
875 SchedWrite.TheDef->getName());
876 }
877 return ResDef;
878 }
879
880 /// Find the ReadAdvance record for the given SchedRead on this processor or
881 /// return NULL.
FindReadAdvance(const CodeGenSchedRW & SchedRead,const CodeGenProcModel & ProcModel)882 Record *SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead,
883 const CodeGenProcModel &ProcModel) {
884 // Check for SchedReads that directly specify a ReadAdvance.
885 if (SchedRead.TheDef->isSubClassOf("SchedReadAdvance"))
886 return SchedRead.TheDef;
887
888 // Check this processor's list of aliases for SchedRead.
889 Record *AliasDef = nullptr;
890 for (Record *A : SchedRead.Aliases) {
891 const CodeGenSchedRW &AliasRW =
892 SchedModels.getSchedRW(A->getValueAsDef("AliasRW"));
893 if (AliasRW.TheDef->getValueInit("SchedModel")->isComplete()) {
894 Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");
895 if (&SchedModels.getProcModel(ModelDef) != &ProcModel)
896 continue;
897 }
898 if (AliasDef)
899 PrintFatalError(AliasRW.TheDef->getLoc(), "Multiple aliases "
900 "defined for processor " + ProcModel.ModelName +
901 " Ensure only one SchedAlias exists per RW.");
902 AliasDef = AliasRW.TheDef;
903 }
904 if (AliasDef && AliasDef->isSubClassOf("SchedReadAdvance"))
905 return AliasDef;
906
907 // Check this processor's ReadAdvanceList.
908 Record *ResDef = nullptr;
909 for (Record *RA : ProcModel.ReadAdvanceDefs) {
910 if (!RA->isSubClassOf("ReadAdvance"))
911 continue;
912 if (AliasDef == RA->getValueAsDef("ReadType")
913 || SchedRead.TheDef == RA->getValueAsDef("ReadType")) {
914 if (ResDef) {
915 PrintFatalError(RA->getLoc(), "Resources are defined for both "
916 "SchedRead and its alias on processor " +
917 ProcModel.ModelName);
918 }
919 ResDef = RA;
920 }
921 }
922 // TODO: If ProcModel has a base model (previous generation processor),
923 // then call FindReadAdvance recursively with that model here.
924 if (!ResDef && SchedRead.TheDef->getName() != "ReadDefault") {
925 PrintFatalError(ProcModel.ModelDef->getLoc(),
926 Twine("Processor does not define resources for ") +
927 SchedRead.TheDef->getName());
928 }
929 return ResDef;
930 }
931
932 // Expand an explicit list of processor resources into a full list of implied
933 // resource groups and super resources that cover them.
ExpandProcResources(RecVec & PRVec,std::vector<int64_t> & Cycles,const CodeGenProcModel & PM)934 void SubtargetEmitter::ExpandProcResources(RecVec &PRVec,
935 std::vector<int64_t> &Cycles,
936 const CodeGenProcModel &PM) {
937 assert(PRVec.size() == Cycles.size() && "failed precondition");
938 for (unsigned i = 0, e = PRVec.size(); i != e; ++i) {
939 Record *PRDef = PRVec[i];
940 RecVec SubResources;
941 if (PRDef->isSubClassOf("ProcResGroup"))
942 SubResources = PRDef->getValueAsListOfDefs("Resources");
943 else {
944 SubResources.push_back(PRDef);
945 PRDef = SchedModels.findProcResUnits(PRDef, PM, PRDef->getLoc());
946 for (Record *SubDef = PRDef;
947 SubDef->getValueInit("Super")->isComplete();) {
948 if (SubDef->isSubClassOf("ProcResGroup")) {
949 // Disallow this for simplicitly.
950 PrintFatalError(SubDef->getLoc(), "Processor resource group "
951 " cannot be a super resources.");
952 }
953 Record *SuperDef =
954 SchedModels.findProcResUnits(SubDef->getValueAsDef("Super"), PM,
955 SubDef->getLoc());
956 PRVec.push_back(SuperDef);
957 Cycles.push_back(Cycles[i]);
958 SubDef = SuperDef;
959 }
960 }
961 for (Record *PR : PM.ProcResourceDefs) {
962 if (PR == PRDef || !PR->isSubClassOf("ProcResGroup"))
963 continue;
964 RecVec SuperResources = PR->getValueAsListOfDefs("Resources");
965 RecIter SubI = SubResources.begin(), SubE = SubResources.end();
966 for( ; SubI != SubE; ++SubI) {
967 if (!is_contained(SuperResources, *SubI)) {
968 break;
969 }
970 }
971 if (SubI == SubE) {
972 PRVec.push_back(PR);
973 Cycles.push_back(Cycles[i]);
974 }
975 }
976 }
977 }
978
979 // Generate the SchedClass table for this processor and update global
980 // tables. Must be called for each processor in order.
GenSchedClassTables(const CodeGenProcModel & ProcModel,SchedClassTables & SchedTables)981 void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
982 SchedClassTables &SchedTables) {
983 SchedTables.ProcSchedClasses.resize(SchedTables.ProcSchedClasses.size() + 1);
984 if (!ProcModel.hasInstrSchedModel())
985 return;
986
987 std::vector<MCSchedClassDesc> &SCTab = SchedTables.ProcSchedClasses.back();
988 LLVM_DEBUG(dbgs() << "\n+++ SCHED CLASSES (GenSchedClassTables) +++\n");
989 for (const CodeGenSchedClass &SC : SchedModels.schedClasses()) {
990 LLVM_DEBUG(SC.dump(&SchedModels));
991
992 SCTab.resize(SCTab.size() + 1);
993 MCSchedClassDesc &SCDesc = SCTab.back();
994 // SCDesc.Name is guarded by NDEBUG
995 SCDesc.NumMicroOps = 0;
996 SCDesc.BeginGroup = false;
997 SCDesc.EndGroup = false;
998 SCDesc.WriteProcResIdx = 0;
999 SCDesc.WriteLatencyIdx = 0;
1000 SCDesc.ReadAdvanceIdx = 0;
1001
1002 // A Variant SchedClass has no resources of its own.
1003 bool HasVariants = false;
1004 for (const CodeGenSchedTransition &CGT :
1005 make_range(SC.Transitions.begin(), SC.Transitions.end())) {
1006 if (CGT.ProcIndex == ProcModel.Index) {
1007 HasVariants = true;
1008 break;
1009 }
1010 }
1011 if (HasVariants) {
1012 SCDesc.NumMicroOps = MCSchedClassDesc::VariantNumMicroOps;
1013 continue;
1014 }
1015
1016 // Determine if the SchedClass is actually reachable on this processor. If
1017 // not don't try to locate the processor resources, it will fail.
1018 // If ProcIndices contains 0, this class applies to all processors.
1019 assert(!SC.ProcIndices.empty() && "expect at least one procidx");
1020 if (SC.ProcIndices[0] != 0) {
1021 if (!is_contained(SC.ProcIndices, ProcModel.Index))
1022 continue;
1023 }
1024 IdxVec Writes = SC.Writes;
1025 IdxVec Reads = SC.Reads;
1026 if (!SC.InstRWs.empty()) {
1027 // This class has a default ReadWrite list which can be overridden by
1028 // InstRW definitions.
1029 Record *RWDef = nullptr;
1030 for (Record *RW : SC.InstRWs) {
1031 Record *RWModelDef = RW->getValueAsDef("SchedModel");
1032 if (&ProcModel == &SchedModels.getProcModel(RWModelDef)) {
1033 RWDef = RW;
1034 break;
1035 }
1036 }
1037 if (RWDef) {
1038 Writes.clear();
1039 Reads.clear();
1040 SchedModels.findRWs(RWDef->getValueAsListOfDefs("OperandReadWrites"),
1041 Writes, Reads);
1042 }
1043 }
1044 if (Writes.empty()) {
1045 // Check this processor's itinerary class resources.
1046 for (Record *I : ProcModel.ItinRWDefs) {
1047 RecVec Matched = I->getValueAsListOfDefs("MatchedItinClasses");
1048 if (is_contained(Matched, SC.ItinClassDef)) {
1049 SchedModels.findRWs(I->getValueAsListOfDefs("OperandReadWrites"),
1050 Writes, Reads);
1051 break;
1052 }
1053 }
1054 if (Writes.empty()) {
1055 LLVM_DEBUG(dbgs() << ProcModel.ModelName
1056 << " does not have resources for class " << SC.Name
1057 << '\n');
1058 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps;
1059 }
1060 }
1061 // Sum resources across all operand writes.
1062 std::vector<MCWriteProcResEntry> WriteProcResources;
1063 std::vector<MCWriteLatencyEntry> WriteLatencies;
1064 std::vector<std::string> WriterNames;
1065 std::vector<MCReadAdvanceEntry> ReadAdvanceEntries;
1066 for (unsigned W : Writes) {
1067 IdxVec WriteSeq;
1068 SchedModels.expandRWSeqForProc(W, WriteSeq, /*IsRead=*/false,
1069 ProcModel);
1070
1071 // For each operand, create a latency entry.
1072 MCWriteLatencyEntry WLEntry;
1073 WLEntry.Cycles = 0;
1074 unsigned WriteID = WriteSeq.back();
1075 WriterNames.push_back(SchedModels.getSchedWrite(WriteID).Name);
1076 // If this Write is not referenced by a ReadAdvance, don't distinguish it
1077 // from other WriteLatency entries.
1078 if (!SchedModels.hasReadOfWrite(
1079 SchedModels.getSchedWrite(WriteID).TheDef)) {
1080 WriteID = 0;
1081 }
1082 WLEntry.WriteResourceID = WriteID;
1083
1084 for (unsigned WS : WriteSeq) {
1085
1086 Record *WriteRes =
1087 FindWriteResources(SchedModels.getSchedWrite(WS), ProcModel);
1088
1089 // Mark the parent class as invalid for unsupported write types.
1090 if (WriteRes->getValueAsBit("Unsupported")) {
1091 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps;
1092 break;
1093 }
1094 WLEntry.Cycles += WriteRes->getValueAsInt("Latency");
1095 SCDesc.NumMicroOps += WriteRes->getValueAsInt("NumMicroOps");
1096 SCDesc.BeginGroup |= WriteRes->getValueAsBit("BeginGroup");
1097 SCDesc.EndGroup |= WriteRes->getValueAsBit("EndGroup");
1098 SCDesc.BeginGroup |= WriteRes->getValueAsBit("SingleIssue");
1099 SCDesc.EndGroup |= WriteRes->getValueAsBit("SingleIssue");
1100
1101 // Create an entry for each ProcResource listed in WriteRes.
1102 RecVec PRVec = WriteRes->getValueAsListOfDefs("ProcResources");
1103 std::vector<int64_t> Cycles =
1104 WriteRes->getValueAsListOfInts("ResourceCycles");
1105
1106 if (Cycles.empty()) {
1107 // If ResourceCycles is not provided, default to one cycle per
1108 // resource.
1109 Cycles.resize(PRVec.size(), 1);
1110 } else if (Cycles.size() != PRVec.size()) {
1111 // If ResourceCycles is provided, check consistency.
1112 PrintFatalError(
1113 WriteRes->getLoc(),
1114 Twine("Inconsistent resource cycles: !size(ResourceCycles) != "
1115 "!size(ProcResources): ")
1116 .concat(Twine(PRVec.size()))
1117 .concat(" vs ")
1118 .concat(Twine(Cycles.size())));
1119 }
1120
1121 ExpandProcResources(PRVec, Cycles, ProcModel);
1122
1123 for (unsigned PRIdx = 0, PREnd = PRVec.size();
1124 PRIdx != PREnd; ++PRIdx) {
1125 MCWriteProcResEntry WPREntry;
1126 WPREntry.ProcResourceIdx = ProcModel.getProcResourceIdx(PRVec[PRIdx]);
1127 assert(WPREntry.ProcResourceIdx && "Bad ProcResourceIdx");
1128 WPREntry.Cycles = Cycles[PRIdx];
1129 // If this resource is already used in this sequence, add the current
1130 // entry's cycles so that the same resource appears to be used
1131 // serially, rather than multiple parallel uses. This is important for
1132 // in-order machine where the resource consumption is a hazard.
1133 unsigned WPRIdx = 0, WPREnd = WriteProcResources.size();
1134 for( ; WPRIdx != WPREnd; ++WPRIdx) {
1135 if (WriteProcResources[WPRIdx].ProcResourceIdx
1136 == WPREntry.ProcResourceIdx) {
1137 WriteProcResources[WPRIdx].Cycles += WPREntry.Cycles;
1138 break;
1139 }
1140 }
1141 if (WPRIdx == WPREnd)
1142 WriteProcResources.push_back(WPREntry);
1143 }
1144 }
1145 WriteLatencies.push_back(WLEntry);
1146 }
1147 // Create an entry for each operand Read in this SchedClass.
1148 // Entries must be sorted first by UseIdx then by WriteResourceID.
1149 for (unsigned UseIdx = 0, EndIdx = Reads.size();
1150 UseIdx != EndIdx; ++UseIdx) {
1151 Record *ReadAdvance =
1152 FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel);
1153 if (!ReadAdvance)
1154 continue;
1155
1156 // Mark the parent class as invalid for unsupported write types.
1157 if (ReadAdvance->getValueAsBit("Unsupported")) {
1158 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps;
1159 break;
1160 }
1161 RecVec ValidWrites = ReadAdvance->getValueAsListOfDefs("ValidWrites");
1162 IdxVec WriteIDs;
1163 if (ValidWrites.empty())
1164 WriteIDs.push_back(0);
1165 else {
1166 for (Record *VW : ValidWrites) {
1167 WriteIDs.push_back(SchedModels.getSchedRWIdx(VW, /*IsRead=*/false));
1168 }
1169 }
1170 llvm::sort(WriteIDs);
1171 for(unsigned W : WriteIDs) {
1172 MCReadAdvanceEntry RAEntry;
1173 RAEntry.UseIdx = UseIdx;
1174 RAEntry.WriteResourceID = W;
1175 RAEntry.Cycles = ReadAdvance->getValueAsInt("Cycles");
1176 ReadAdvanceEntries.push_back(RAEntry);
1177 }
1178 }
1179 if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) {
1180 WriteProcResources.clear();
1181 WriteLatencies.clear();
1182 ReadAdvanceEntries.clear();
1183 }
1184 // Add the information for this SchedClass to the global tables using basic
1185 // compression.
1186 //
1187 // WritePrecRes entries are sorted by ProcResIdx.
1188 llvm::sort(WriteProcResources, LessWriteProcResources());
1189
1190 SCDesc.NumWriteProcResEntries = WriteProcResources.size();
1191 std::vector<MCWriteProcResEntry>::iterator WPRPos =
1192 std::search(SchedTables.WriteProcResources.begin(),
1193 SchedTables.WriteProcResources.end(),
1194 WriteProcResources.begin(), WriteProcResources.end());
1195 if (WPRPos != SchedTables.WriteProcResources.end())
1196 SCDesc.WriteProcResIdx = WPRPos - SchedTables.WriteProcResources.begin();
1197 else {
1198 SCDesc.WriteProcResIdx = SchedTables.WriteProcResources.size();
1199 SchedTables.WriteProcResources.insert(WPRPos, WriteProcResources.begin(),
1200 WriteProcResources.end());
1201 }
1202 // Latency entries must remain in operand order.
1203 SCDesc.NumWriteLatencyEntries = WriteLatencies.size();
1204 std::vector<MCWriteLatencyEntry>::iterator WLPos =
1205 std::search(SchedTables.WriteLatencies.begin(),
1206 SchedTables.WriteLatencies.end(),
1207 WriteLatencies.begin(), WriteLatencies.end());
1208 if (WLPos != SchedTables.WriteLatencies.end()) {
1209 unsigned idx = WLPos - SchedTables.WriteLatencies.begin();
1210 SCDesc.WriteLatencyIdx = idx;
1211 for (unsigned i = 0, e = WriteLatencies.size(); i < e; ++i)
1212 if (SchedTables.WriterNames[idx + i].find(WriterNames[i]) ==
1213 std::string::npos) {
1214 SchedTables.WriterNames[idx + i] += std::string("_") + WriterNames[i];
1215 }
1216 }
1217 else {
1218 SCDesc.WriteLatencyIdx = SchedTables.WriteLatencies.size();
1219 llvm::append_range(SchedTables.WriteLatencies, WriteLatencies);
1220 llvm::append_range(SchedTables.WriterNames, WriterNames);
1221 }
1222 // ReadAdvanceEntries must remain in operand order.
1223 SCDesc.NumReadAdvanceEntries = ReadAdvanceEntries.size();
1224 std::vector<MCReadAdvanceEntry>::iterator RAPos =
1225 std::search(SchedTables.ReadAdvanceEntries.begin(),
1226 SchedTables.ReadAdvanceEntries.end(),
1227 ReadAdvanceEntries.begin(), ReadAdvanceEntries.end());
1228 if (RAPos != SchedTables.ReadAdvanceEntries.end())
1229 SCDesc.ReadAdvanceIdx = RAPos - SchedTables.ReadAdvanceEntries.begin();
1230 else {
1231 SCDesc.ReadAdvanceIdx = SchedTables.ReadAdvanceEntries.size();
1232 llvm::append_range(SchedTables.ReadAdvanceEntries, ReadAdvanceEntries);
1233 }
1234 }
1235 }
1236
1237 // Emit SchedClass tables for all processors and associated global tables.
EmitSchedClassTables(SchedClassTables & SchedTables,raw_ostream & OS)1238 void SubtargetEmitter::EmitSchedClassTables(SchedClassTables &SchedTables,
1239 raw_ostream &OS) {
1240 // Emit global WriteProcResTable.
1241 OS << "\n// {ProcResourceIdx, Cycles}\n"
1242 << "extern const llvm::MCWriteProcResEntry "
1243 << Target << "WriteProcResTable[] = {\n"
1244 << " { 0, 0}, // Invalid\n";
1245 for (unsigned WPRIdx = 1, WPREnd = SchedTables.WriteProcResources.size();
1246 WPRIdx != WPREnd; ++WPRIdx) {
1247 MCWriteProcResEntry &WPREntry = SchedTables.WriteProcResources[WPRIdx];
1248 OS << " {" << format("%2d", WPREntry.ProcResourceIdx) << ", "
1249 << format("%2d", WPREntry.Cycles) << "}";
1250 if (WPRIdx + 1 < WPREnd)
1251 OS << ',';
1252 OS << " // #" << WPRIdx << '\n';
1253 }
1254 OS << "}; // " << Target << "WriteProcResTable\n";
1255
1256 // Emit global WriteLatencyTable.
1257 OS << "\n// {Cycles, WriteResourceID}\n"
1258 << "extern const llvm::MCWriteLatencyEntry "
1259 << Target << "WriteLatencyTable[] = {\n"
1260 << " { 0, 0}, // Invalid\n";
1261 for (unsigned WLIdx = 1, WLEnd = SchedTables.WriteLatencies.size();
1262 WLIdx != WLEnd; ++WLIdx) {
1263 MCWriteLatencyEntry &WLEntry = SchedTables.WriteLatencies[WLIdx];
1264 OS << " {" << format("%2d", WLEntry.Cycles) << ", "
1265 << format("%2d", WLEntry.WriteResourceID) << "}";
1266 if (WLIdx + 1 < WLEnd)
1267 OS << ',';
1268 OS << " // #" << WLIdx << " " << SchedTables.WriterNames[WLIdx] << '\n';
1269 }
1270 OS << "}; // " << Target << "WriteLatencyTable\n";
1271
1272 // Emit global ReadAdvanceTable.
1273 OS << "\n// {UseIdx, WriteResourceID, Cycles}\n"
1274 << "extern const llvm::MCReadAdvanceEntry "
1275 << Target << "ReadAdvanceTable[] = {\n"
1276 << " {0, 0, 0}, // Invalid\n";
1277 for (unsigned RAIdx = 1, RAEnd = SchedTables.ReadAdvanceEntries.size();
1278 RAIdx != RAEnd; ++RAIdx) {
1279 MCReadAdvanceEntry &RAEntry = SchedTables.ReadAdvanceEntries[RAIdx];
1280 OS << " {" << RAEntry.UseIdx << ", "
1281 << format("%2d", RAEntry.WriteResourceID) << ", "
1282 << format("%2d", RAEntry.Cycles) << "}";
1283 if (RAIdx + 1 < RAEnd)
1284 OS << ',';
1285 OS << " // #" << RAIdx << '\n';
1286 }
1287 OS << "}; // " << Target << "ReadAdvanceTable\n";
1288
1289 // Emit a SchedClass table for each processor.
1290 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
1291 PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
1292 if (!PI->hasInstrSchedModel())
1293 continue;
1294
1295 std::vector<MCSchedClassDesc> &SCTab =
1296 SchedTables.ProcSchedClasses[1 + (PI - SchedModels.procModelBegin())];
1297
1298 OS << "\n// {Name, NumMicroOps, BeginGroup, EndGroup,"
1299 << " WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}\n";
1300 OS << "static const llvm::MCSchedClassDesc "
1301 << PI->ModelName << "SchedClasses[] = {\n";
1302
1303 // The first class is always invalid. We no way to distinguish it except by
1304 // name and position.
1305 assert(SchedModels.getSchedClass(0).Name == "NoInstrModel"
1306 && "invalid class not first");
1307 OS << " {DBGFIELD(\"InvalidSchedClass\") "
1308 << MCSchedClassDesc::InvalidNumMicroOps
1309 << ", false, false, 0, 0, 0, 0, 0, 0},\n";
1310
1311 for (unsigned SCIdx = 1, SCEnd = SCTab.size(); SCIdx != SCEnd; ++SCIdx) {
1312 MCSchedClassDesc &MCDesc = SCTab[SCIdx];
1313 const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx);
1314 OS << " {DBGFIELD(\"" << SchedClass.Name << "\") ";
1315 if (SchedClass.Name.size() < 18)
1316 OS.indent(18 - SchedClass.Name.size());
1317 OS << MCDesc.NumMicroOps
1318 << ", " << ( MCDesc.BeginGroup ? "true" : "false" )
1319 << ", " << ( MCDesc.EndGroup ? "true" : "false" )
1320 << ", " << format("%2d", MCDesc.WriteProcResIdx)
1321 << ", " << MCDesc.NumWriteProcResEntries
1322 << ", " << format("%2d", MCDesc.WriteLatencyIdx)
1323 << ", " << MCDesc.NumWriteLatencyEntries
1324 << ", " << format("%2d", MCDesc.ReadAdvanceIdx)
1325 << ", " << MCDesc.NumReadAdvanceEntries
1326 << "}, // #" << SCIdx << '\n';
1327 }
1328 OS << "}; // " << PI->ModelName << "SchedClasses\n";
1329 }
1330 }
1331
EmitProcessorModels(raw_ostream & OS)1332 void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) {
1333 // For each processor model.
1334 for (const CodeGenProcModel &PM : SchedModels.procModels()) {
1335 // Emit extra processor info if available.
1336 if (PM.hasExtraProcessorInfo())
1337 EmitExtraProcessorInfo(PM, OS);
1338 // Emit processor resource table.
1339 if (PM.hasInstrSchedModel())
1340 EmitProcessorResources(PM, OS);
1341 else if(!PM.ProcResourceDefs.empty())
1342 PrintFatalError(PM.ModelDef->getLoc(), "SchedMachineModel defines "
1343 "ProcResources without defining WriteRes SchedWriteRes");
1344
1345 // Begin processor itinerary properties
1346 OS << "\n";
1347 OS << "static const llvm::MCSchedModel " << PM.ModelName << " = {\n";
1348 EmitProcessorProp(OS, PM.ModelDef, "IssueWidth", ',');
1349 EmitProcessorProp(OS, PM.ModelDef, "MicroOpBufferSize", ',');
1350 EmitProcessorProp(OS, PM.ModelDef, "LoopMicroOpBufferSize", ',');
1351 EmitProcessorProp(OS, PM.ModelDef, "LoadLatency", ',');
1352 EmitProcessorProp(OS, PM.ModelDef, "HighLatency", ',');
1353 EmitProcessorProp(OS, PM.ModelDef, "MispredictPenalty", ',');
1354
1355 bool PostRAScheduler =
1356 (PM.ModelDef ? PM.ModelDef->getValueAsBit("PostRAScheduler") : false);
1357
1358 OS << " " << (PostRAScheduler ? "true" : "false") << ", // "
1359 << "PostRAScheduler\n";
1360
1361 bool CompleteModel =
1362 (PM.ModelDef ? PM.ModelDef->getValueAsBit("CompleteModel") : false);
1363
1364 OS << " " << (CompleteModel ? "true" : "false") << ", // "
1365 << "CompleteModel\n";
1366
1367 OS << " " << PM.Index << ", // Processor ID\n";
1368 if (PM.hasInstrSchedModel())
1369 OS << " " << PM.ModelName << "ProcResources" << ",\n"
1370 << " " << PM.ModelName << "SchedClasses" << ",\n"
1371 << " " << PM.ProcResourceDefs.size()+1 << ",\n"
1372 << " " << (SchedModels.schedClassEnd()
1373 - SchedModels.schedClassBegin()) << ",\n";
1374 else
1375 OS << " nullptr, nullptr, 0, 0,"
1376 << " // No instruction-level machine model.\n";
1377 if (PM.hasItineraries())
1378 OS << " " << PM.ItinsDef->getName() << ",\n";
1379 else
1380 OS << " nullptr, // No Itinerary\n";
1381 if (PM.hasExtraProcessorInfo())
1382 OS << " &" << PM.ModelName << "ExtraInfo,\n";
1383 else
1384 OS << " nullptr // No extra processor descriptor\n";
1385 OS << "};\n";
1386 }
1387 }
1388
1389 //
1390 // EmitSchedModel - Emits all scheduling model tables, folding common patterns.
1391 //
EmitSchedModel(raw_ostream & OS)1392 void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) {
1393 OS << "#ifdef DBGFIELD\n"
1394 << "#error \"<target>GenSubtargetInfo.inc requires a DBGFIELD macro\"\n"
1395 << "#endif\n"
1396 << "#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)\n"
1397 << "#define DBGFIELD(x) x,\n"
1398 << "#else\n"
1399 << "#define DBGFIELD(x)\n"
1400 << "#endif\n";
1401
1402 if (SchedModels.hasItineraries()) {
1403 std::vector<std::vector<InstrItinerary>> ProcItinLists;
1404 // Emit the stage data
1405 EmitStageAndOperandCycleData(OS, ProcItinLists);
1406 EmitItineraries(OS, ProcItinLists);
1407 }
1408 OS << "\n// ===============================================================\n"
1409 << "// Data tables for the new per-operand machine model.\n";
1410
1411 SchedClassTables SchedTables;
1412 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) {
1413 GenSchedClassTables(ProcModel, SchedTables);
1414 }
1415 EmitSchedClassTables(SchedTables, OS);
1416
1417 OS << "\n#undef DBGFIELD\n";
1418
1419 // Emit the processor machine model
1420 EmitProcessorModels(OS);
1421 }
1422
emitPredicateProlog(const RecordKeeper & Records,raw_ostream & OS)1423 static void emitPredicateProlog(const RecordKeeper &Records, raw_ostream &OS) {
1424 std::string Buffer;
1425 raw_string_ostream Stream(Buffer);
1426
1427 // Collect all the PredicateProlog records and print them to the output
1428 // stream.
1429 std::vector<Record *> Prologs =
1430 Records.getAllDerivedDefinitions("PredicateProlog");
1431 llvm::sort(Prologs, LessRecord());
1432 for (Record *P : Prologs)
1433 Stream << P->getValueAsString("Code") << '\n';
1434
1435 Stream.flush();
1436 OS << Buffer;
1437 }
1438
isTruePredicate(const Record * Rec)1439 static bool isTruePredicate(const Record *Rec) {
1440 return Rec->isSubClassOf("MCSchedPredicate") &&
1441 Rec->getValueAsDef("Pred")->isSubClassOf("MCTrue");
1442 }
1443
emitPredicates(const CodeGenSchedTransition & T,const CodeGenSchedClass & SC,PredicateExpander & PE,raw_ostream & OS)1444 static void emitPredicates(const CodeGenSchedTransition &T,
1445 const CodeGenSchedClass &SC, PredicateExpander &PE,
1446 raw_ostream &OS) {
1447 std::string Buffer;
1448 raw_string_ostream SS(Buffer);
1449
1450 // If not all predicates are MCTrue, then we need an if-stmt.
1451 unsigned NumNonTruePreds =
1452 T.PredTerm.size() - count_if(T.PredTerm, isTruePredicate);
1453
1454 SS.indent(PE.getIndentLevel() * 2);
1455
1456 if (NumNonTruePreds) {
1457 bool FirstNonTruePredicate = true;
1458 SS << "if (";
1459
1460 PE.setIndentLevel(PE.getIndentLevel() + 2);
1461
1462 for (const Record *Rec : T.PredTerm) {
1463 // Skip predicates that evaluate to "true".
1464 if (isTruePredicate(Rec))
1465 continue;
1466
1467 if (FirstNonTruePredicate) {
1468 FirstNonTruePredicate = false;
1469 } else {
1470 SS << "\n";
1471 SS.indent(PE.getIndentLevel() * 2);
1472 SS << "&& ";
1473 }
1474
1475 if (Rec->isSubClassOf("MCSchedPredicate")) {
1476 PE.expandPredicate(SS, Rec->getValueAsDef("Pred"));
1477 continue;
1478 }
1479
1480 // Expand this legacy predicate and wrap it around braces if there is more
1481 // than one predicate to expand.
1482 SS << ((NumNonTruePreds > 1) ? "(" : "")
1483 << Rec->getValueAsString("Predicate")
1484 << ((NumNonTruePreds > 1) ? ")" : "");
1485 }
1486
1487 SS << ")\n"; // end of if-stmt
1488 PE.decreaseIndentLevel();
1489 SS.indent(PE.getIndentLevel() * 2);
1490 PE.decreaseIndentLevel();
1491 }
1492
1493 SS << "return " << T.ToClassIdx << "; // " << SC.Name << '\n';
1494 SS.flush();
1495 OS << Buffer;
1496 }
1497
1498 // Used by method `SubtargetEmitter::emitSchedModelHelpersImpl()` to generate
1499 // epilogue code for the auto-generated helper.
emitSchedModelHelperEpilogue(raw_ostream & OS,bool ShouldReturnZero)1500 static void emitSchedModelHelperEpilogue(raw_ostream &OS,
1501 bool ShouldReturnZero) {
1502 if (ShouldReturnZero) {
1503 OS << " // Don't know how to resolve this scheduling class.\n"
1504 << " return 0;\n";
1505 return;
1506 }
1507
1508 OS << " report_fatal_error(\"Expected a variant SchedClass\");\n";
1509 }
1510
hasMCSchedPredicates(const CodeGenSchedTransition & T)1511 static bool hasMCSchedPredicates(const CodeGenSchedTransition &T) {
1512 return all_of(T.PredTerm, [](const Record *Rec) {
1513 return Rec->isSubClassOf("MCSchedPredicate");
1514 });
1515 }
1516
collectVariantClasses(const CodeGenSchedModels & SchedModels,IdxVec & VariantClasses,bool OnlyExpandMCInstPredicates)1517 static void collectVariantClasses(const CodeGenSchedModels &SchedModels,
1518 IdxVec &VariantClasses,
1519 bool OnlyExpandMCInstPredicates) {
1520 for (const CodeGenSchedClass &SC : SchedModels.schedClasses()) {
1521 // Ignore non-variant scheduling classes.
1522 if (SC.Transitions.empty())
1523 continue;
1524
1525 if (OnlyExpandMCInstPredicates) {
1526 // Ignore this variant scheduling class no transitions use any meaningful
1527 // MCSchedPredicate definitions.
1528 if (!any_of(SC.Transitions, [](const CodeGenSchedTransition &T) {
1529 return hasMCSchedPredicates(T);
1530 }))
1531 continue;
1532 }
1533
1534 VariantClasses.push_back(SC.Index);
1535 }
1536 }
1537
collectProcessorIndices(const CodeGenSchedClass & SC,IdxVec & ProcIndices)1538 static void collectProcessorIndices(const CodeGenSchedClass &SC,
1539 IdxVec &ProcIndices) {
1540 // A variant scheduling class may define transitions for multiple
1541 // processors. This function identifies wich processors are associated with
1542 // transition rules specified by variant class `SC`.
1543 for (const CodeGenSchedTransition &T : SC.Transitions) {
1544 IdxVec PI;
1545 std::set_union(&T.ProcIndex, &T.ProcIndex + 1, ProcIndices.begin(),
1546 ProcIndices.end(), std::back_inserter(PI));
1547 ProcIndices.swap(PI);
1548 }
1549 }
1550
isAlwaysTrue(const CodeGenSchedTransition & T)1551 static bool isAlwaysTrue(const CodeGenSchedTransition &T) {
1552 return llvm::all_of(T.PredTerm,
1553 [](const Record *R) { return isTruePredicate(R); });
1554 }
1555
emitSchedModelHelpersImpl(raw_ostream & OS,bool OnlyExpandMCInstPredicates)1556 void SubtargetEmitter::emitSchedModelHelpersImpl(
1557 raw_ostream &OS, bool OnlyExpandMCInstPredicates) {
1558 IdxVec VariantClasses;
1559 collectVariantClasses(SchedModels, VariantClasses,
1560 OnlyExpandMCInstPredicates);
1561
1562 if (VariantClasses.empty()) {
1563 emitSchedModelHelperEpilogue(OS, OnlyExpandMCInstPredicates);
1564 return;
1565 }
1566
1567 // Construct a switch statement where the condition is a check on the
1568 // scheduling class identifier. There is a `case` for every variant class
1569 // defined by the processor models of this target.
1570 // Each `case` implements a number of rules to resolve (i.e. to transition from)
1571 // a variant scheduling class to another scheduling class. Rules are
1572 // described by instances of CodeGenSchedTransition. Note that transitions may
1573 // not be valid for all processors.
1574 OS << " switch (SchedClass) {\n";
1575 for (unsigned VC : VariantClasses) {
1576 IdxVec ProcIndices;
1577 const CodeGenSchedClass &SC = SchedModels.getSchedClass(VC);
1578 collectProcessorIndices(SC, ProcIndices);
1579
1580 OS << " case " << VC << ": // " << SC.Name << '\n';
1581
1582 PredicateExpander PE(Target);
1583 PE.setByRef(false);
1584 PE.setExpandForMC(OnlyExpandMCInstPredicates);
1585 for (unsigned PI : ProcIndices) {
1586 OS << " ";
1587
1588 // Emit a guard on the processor ID.
1589 if (PI != 0) {
1590 OS << (OnlyExpandMCInstPredicates
1591 ? "if (CPUID == "
1592 : "if (SchedModel->getProcessorID() == ");
1593 OS << PI << ") ";
1594 OS << "{ // " << (SchedModels.procModelBegin() + PI)->ModelName << '\n';
1595 }
1596
1597 // Now emit transitions associated with processor PI.
1598 const CodeGenSchedTransition *FinalT = nullptr;
1599 for (const CodeGenSchedTransition &T : SC.Transitions) {
1600 if (PI != 0 && T.ProcIndex != PI)
1601 continue;
1602
1603 // Emit only transitions based on MCSchedPredicate, if it's the case.
1604 // At least the transition specified by NoSchedPred is emitted,
1605 // which becomes the default transition for those variants otherwise
1606 // not based on MCSchedPredicate.
1607 // FIXME: preferably, llvm-mca should instead assume a reasonable
1608 // default when a variant transition is not based on MCSchedPredicate
1609 // for a given processor.
1610 if (OnlyExpandMCInstPredicates && !hasMCSchedPredicates(T))
1611 continue;
1612
1613 // If transition is folded to 'return X' it should be the last one.
1614 if (isAlwaysTrue(T)) {
1615 FinalT = &T;
1616 continue;
1617 }
1618 PE.setIndentLevel(3);
1619 emitPredicates(T, SchedModels.getSchedClass(T.ToClassIdx), PE, OS);
1620 }
1621 if (FinalT)
1622 emitPredicates(*FinalT, SchedModels.getSchedClass(FinalT->ToClassIdx),
1623 PE, OS);
1624
1625 OS << " }\n";
1626
1627 if (PI == 0)
1628 break;
1629 }
1630
1631 if (SC.isInferred())
1632 OS << " return " << SC.Index << ";\n";
1633 OS << " break;\n";
1634 }
1635
1636 OS << " };\n";
1637
1638 emitSchedModelHelperEpilogue(OS, OnlyExpandMCInstPredicates);
1639 }
1640
EmitSchedModelHelpers(const std::string & ClassName,raw_ostream & OS)1641 void SubtargetEmitter::EmitSchedModelHelpers(const std::string &ClassName,
1642 raw_ostream &OS) {
1643 OS << "unsigned " << ClassName
1644 << "\n::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI,"
1645 << " const TargetSchedModel *SchedModel) const {\n";
1646
1647 // Emit the predicate prolog code.
1648 emitPredicateProlog(Records, OS);
1649
1650 // Emit target predicates.
1651 emitSchedModelHelpersImpl(OS);
1652
1653 OS << "} // " << ClassName << "::resolveSchedClass\n\n";
1654
1655 OS << "unsigned " << ClassName
1656 << "\n::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI,"
1657 << " const MCInstrInfo *MCII, unsigned CPUID) const {\n"
1658 << " return " << Target << "_MC"
1659 << "::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);\n"
1660 << "} // " << ClassName << "::resolveVariantSchedClass\n\n";
1661
1662 STIPredicateExpander PE(Target);
1663 PE.setClassPrefix(ClassName);
1664 PE.setExpandDefinition(true);
1665 PE.setByRef(false);
1666 PE.setIndentLevel(0);
1667
1668 for (const STIPredicateFunction &Fn : SchedModels.getSTIPredicates())
1669 PE.expandSTIPredicate(OS, Fn);
1670 }
1671
EmitHwModeCheck(const std::string & ClassName,raw_ostream & OS)1672 void SubtargetEmitter::EmitHwModeCheck(const std::string &ClassName,
1673 raw_ostream &OS) {
1674 const CodeGenHwModes &CGH = TGT.getHwModes();
1675 assert(CGH.getNumModeIds() > 0);
1676 if (CGH.getNumModeIds() == 1)
1677 return;
1678
1679 OS << "unsigned " << ClassName << "::getHwMode() const {\n";
1680 for (unsigned M = 1, NumModes = CGH.getNumModeIds(); M != NumModes; ++M) {
1681 const HwMode &HM = CGH.getMode(M);
1682 OS << " if (checkFeatures(\"" << HM.Features
1683 << "\")) return " << M << ";\n";
1684 }
1685 OS << " return 0;\n}\n";
1686 }
1687
1688 //
1689 // ParseFeaturesFunction - Produces a subtarget specific function for parsing
1690 // the subtarget features string.
1691 //
ParseFeaturesFunction(raw_ostream & OS,unsigned NumFeatures,unsigned NumProcs)1692 void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS,
1693 unsigned NumFeatures,
1694 unsigned NumProcs) {
1695 std::vector<Record*> Features =
1696 Records.getAllDerivedDefinitions("SubtargetFeature");
1697 llvm::sort(Features, LessRecord());
1698
1699 OS << "// ParseSubtargetFeatures - Parses features string setting specified\n"
1700 << "// subtarget options.\n"
1701 << "void llvm::";
1702 OS << Target;
1703 OS << "Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, "
1704 << "StringRef FS) {\n"
1705 << " LLVM_DEBUG(dbgs() << \"\\nFeatures:\" << FS);\n"
1706 << " LLVM_DEBUG(dbgs() << \"\\nCPU:\" << CPU);\n"
1707 << " LLVM_DEBUG(dbgs() << \"\\nTuneCPU:\" << TuneCPU << \"\\n\\n\");\n";
1708
1709 if (Features.empty()) {
1710 OS << "}\n";
1711 return;
1712 }
1713
1714 OS << " InitMCProcessorInfo(CPU, TuneCPU, FS);\n"
1715 << " const FeatureBitset &Bits = getFeatureBits();\n";
1716
1717 for (Record *R : Features) {
1718 // Next record
1719 StringRef Instance = R->getName();
1720 StringRef Value = R->getValueAsString("Value");
1721 StringRef Attribute = R->getValueAsString("Attribute");
1722
1723 if (Value=="true" || Value=="false")
1724 OS << " if (Bits[" << Target << "::"
1725 << Instance << "]) "
1726 << Attribute << " = " << Value << ";\n";
1727 else
1728 OS << " if (Bits[" << Target << "::"
1729 << Instance << "] && "
1730 << Attribute << " < " << Value << ") "
1731 << Attribute << " = " << Value << ";\n";
1732 }
1733
1734 OS << "}\n";
1735 }
1736
emitGenMCSubtargetInfo(raw_ostream & OS)1737 void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) {
1738 OS << "namespace " << Target << "_MC {\n"
1739 << "unsigned resolveVariantSchedClassImpl(unsigned SchedClass,\n"
1740 << " const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {\n";
1741 emitSchedModelHelpersImpl(OS, /* OnlyExpandMCPredicates */ true);
1742 OS << "}\n";
1743 OS << "} // end namespace " << Target << "_MC\n\n";
1744
1745 OS << "struct " << Target
1746 << "GenMCSubtargetInfo : public MCSubtargetInfo {\n";
1747 OS << " " << Target << "GenMCSubtargetInfo(const Triple &TT,\n"
1748 << " StringRef CPU, StringRef TuneCPU, StringRef FS,\n"
1749 << " ArrayRef<SubtargetFeatureKV> PF,\n"
1750 << " ArrayRef<SubtargetSubTypeKV> PD,\n"
1751 << " const MCWriteProcResEntry *WPR,\n"
1752 << " const MCWriteLatencyEntry *WL,\n"
1753 << " const MCReadAdvanceEntry *RA, const InstrStage *IS,\n"
1754 << " const unsigned *OC, const unsigned *FP) :\n"
1755 << " MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD,\n"
1756 << " WPR, WL, RA, IS, OC, FP) { }\n\n"
1757 << " unsigned resolveVariantSchedClass(unsigned SchedClass,\n"
1758 << " const MCInst *MI, const MCInstrInfo *MCII,\n"
1759 << " unsigned CPUID) const override {\n"
1760 << " return " << Target << "_MC"
1761 << "::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);\n";
1762 OS << " }\n";
1763 if (TGT.getHwModes().getNumModeIds() > 1)
1764 OS << " unsigned getHwMode() const override;\n";
1765 OS << "};\n";
1766 EmitHwModeCheck(Target + "GenMCSubtargetInfo", OS);
1767 }
1768
EmitMCInstrAnalysisPredicateFunctions(raw_ostream & OS)1769 void SubtargetEmitter::EmitMCInstrAnalysisPredicateFunctions(raw_ostream &OS) {
1770 OS << "\n#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS\n";
1771 OS << "#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS\n\n";
1772
1773 STIPredicateExpander PE(Target);
1774 PE.setExpandForMC(true);
1775 PE.setByRef(true);
1776 for (const STIPredicateFunction &Fn : SchedModels.getSTIPredicates())
1777 PE.expandSTIPredicate(OS, Fn);
1778
1779 OS << "#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS\n\n";
1780
1781 OS << "\n#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS\n";
1782 OS << "#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS\n\n";
1783
1784 std::string ClassPrefix = Target + "MCInstrAnalysis";
1785 PE.setExpandDefinition(true);
1786 PE.setClassPrefix(ClassPrefix);
1787 PE.setIndentLevel(0);
1788 for (const STIPredicateFunction &Fn : SchedModels.getSTIPredicates())
1789 PE.expandSTIPredicate(OS, Fn);
1790
1791 OS << "#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS\n\n";
1792 }
1793
1794 //
1795 // SubtargetEmitter::run - Main subtarget enumeration emitter.
1796 //
run(raw_ostream & OS)1797 void SubtargetEmitter::run(raw_ostream &OS) {
1798 emitSourceFileHeader("Subtarget Enumeration Source Fragment", OS);
1799
1800 OS << "\n#ifdef GET_SUBTARGETINFO_ENUM\n";
1801 OS << "#undef GET_SUBTARGETINFO_ENUM\n\n";
1802
1803 DenseMap<Record *, unsigned> FeatureMap;
1804
1805 OS << "namespace llvm {\n";
1806 Enumeration(OS, FeatureMap);
1807 OS << "} // end namespace llvm\n\n";
1808 OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n";
1809
1810 OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n";
1811 OS << "#undef GET_SUBTARGETINFO_MC_DESC\n\n";
1812
1813 OS << "namespace llvm {\n";
1814 #if 0
1815 OS << "namespace {\n";
1816 #endif
1817 unsigned NumFeatures = FeatureKeyValues(OS, FeatureMap);
1818 OS << "\n";
1819 EmitSchedModel(OS);
1820 OS << "\n";
1821 unsigned NumProcs = CPUKeyValues(OS, FeatureMap);
1822 OS << "\n";
1823 #if 0
1824 OS << "} // end anonymous namespace\n\n";
1825 #endif
1826
1827 // MCInstrInfo initialization routine.
1828 emitGenMCSubtargetInfo(OS);
1829
1830 OS << "\nstatic inline MCSubtargetInfo *create" << Target
1831 << "MCSubtargetInfoImpl("
1832 << "const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {\n";
1833 OS << " return new " << Target
1834 << "GenMCSubtargetInfo(TT, CPU, TuneCPU, FS, ";
1835 if (NumFeatures)
1836 OS << Target << "FeatureKV, ";
1837 else
1838 OS << "None, ";
1839 if (NumProcs)
1840 OS << Target << "SubTypeKV, ";
1841 else
1842 OS << "None, ";
1843 OS << '\n'; OS.indent(22);
1844 OS << Target << "WriteProcResTable, "
1845 << Target << "WriteLatencyTable, "
1846 << Target << "ReadAdvanceTable, ";
1847 OS << '\n'; OS.indent(22);
1848 if (SchedModels.hasItineraries()) {
1849 OS << Target << "Stages, "
1850 << Target << "OperandCycles, "
1851 << Target << "ForwardingPaths";
1852 } else
1853 OS << "nullptr, nullptr, nullptr";
1854 OS << ");\n}\n\n";
1855
1856 OS << "} // end namespace llvm\n\n";
1857
1858 OS << "#endif // GET_SUBTARGETINFO_MC_DESC\n\n";
1859
1860 OS << "\n#ifdef GET_SUBTARGETINFO_TARGET_DESC\n";
1861 OS << "#undef GET_SUBTARGETINFO_TARGET_DESC\n\n";
1862
1863 OS << "#include \"llvm/Support/Debug.h\"\n";
1864 OS << "#include \"llvm/Support/raw_ostream.h\"\n\n";
1865 ParseFeaturesFunction(OS, NumFeatures, NumProcs);
1866
1867 OS << "#endif // GET_SUBTARGETINFO_TARGET_DESC\n\n";
1868
1869 // Create a TargetSubtargetInfo subclass to hide the MC layer initialization.
1870 OS << "\n#ifdef GET_SUBTARGETINFO_HEADER\n";
1871 OS << "#undef GET_SUBTARGETINFO_HEADER\n\n";
1872
1873 std::string ClassName = Target + "GenSubtargetInfo";
1874 OS << "namespace llvm {\n";
1875 OS << "class DFAPacketizer;\n";
1876 OS << "namespace " << Target << "_MC {\n"
1877 << "unsigned resolveVariantSchedClassImpl(unsigned SchedClass,"
1878 << " const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);\n"
1879 << "} // end namespace " << Target << "_MC\n\n";
1880 OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"
1881 << " explicit " << ClassName << "(const Triple &TT, StringRef CPU, "
1882 << "StringRef TuneCPU, StringRef FS);\n"
1883 << "public:\n"
1884 << " unsigned resolveSchedClass(unsigned SchedClass, "
1885 << " const MachineInstr *DefMI,"
1886 << " const TargetSchedModel *SchedModel) const override;\n"
1887 << " unsigned resolveVariantSchedClass(unsigned SchedClass,"
1888 << " const MCInst *MI, const MCInstrInfo *MCII,"
1889 << " unsigned CPUID) const override;\n"
1890 << " DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID)"
1891 << " const;\n";
1892 if (TGT.getHwModes().getNumModeIds() > 1)
1893 OS << " unsigned getHwMode() const override;\n";
1894
1895 STIPredicateExpander PE(Target);
1896 PE.setByRef(false);
1897 for (const STIPredicateFunction &Fn : SchedModels.getSTIPredicates())
1898 PE.expandSTIPredicate(OS, Fn);
1899
1900 OS << "};\n"
1901 << "} // end namespace llvm\n\n";
1902
1903 OS << "#endif // GET_SUBTARGETINFO_HEADER\n\n";
1904
1905 OS << "\n#ifdef GET_SUBTARGETINFO_CTOR\n";
1906 OS << "#undef GET_SUBTARGETINFO_CTOR\n\n";
1907
1908 OS << "#include \"llvm/CodeGen/TargetSchedule.h\"\n\n";
1909 OS << "namespace llvm {\n";
1910 OS << "extern const llvm::SubtargetFeatureKV " << Target << "FeatureKV[];\n";
1911 OS << "extern const llvm::SubtargetSubTypeKV " << Target << "SubTypeKV[];\n";
1912 OS << "extern const llvm::MCWriteProcResEntry "
1913 << Target << "WriteProcResTable[];\n";
1914 OS << "extern const llvm::MCWriteLatencyEntry "
1915 << Target << "WriteLatencyTable[];\n";
1916 OS << "extern const llvm::MCReadAdvanceEntry "
1917 << Target << "ReadAdvanceTable[];\n";
1918
1919 if (SchedModels.hasItineraries()) {
1920 OS << "extern const llvm::InstrStage " << Target << "Stages[];\n";
1921 OS << "extern const unsigned " << Target << "OperandCycles[];\n";
1922 OS << "extern const unsigned " << Target << "ForwardingPaths[];\n";
1923 }
1924
1925 OS << ClassName << "::" << ClassName << "(const Triple &TT, StringRef CPU, "
1926 << "StringRef TuneCPU, StringRef FS)\n"
1927 << " : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ";
1928 if (NumFeatures)
1929 OS << "makeArrayRef(" << Target << "FeatureKV, " << NumFeatures << "), ";
1930 else
1931 OS << "None, ";
1932 if (NumProcs)
1933 OS << "makeArrayRef(" << Target << "SubTypeKV, " << NumProcs << "), ";
1934 else
1935 OS << "None, ";
1936 OS << '\n'; OS.indent(24);
1937 OS << Target << "WriteProcResTable, "
1938 << Target << "WriteLatencyTable, "
1939 << Target << "ReadAdvanceTable, ";
1940 OS << '\n'; OS.indent(24);
1941 if (SchedModels.hasItineraries()) {
1942 OS << Target << "Stages, "
1943 << Target << "OperandCycles, "
1944 << Target << "ForwardingPaths";
1945 } else
1946 OS << "nullptr, nullptr, nullptr";
1947 OS << ") {}\n\n";
1948
1949 EmitSchedModelHelpers(ClassName, OS);
1950 EmitHwModeCheck(ClassName, OS);
1951
1952 OS << "} // end namespace llvm\n\n";
1953
1954 OS << "#endif // GET_SUBTARGETINFO_CTOR\n\n";
1955
1956 EmitMCInstrAnalysisPredicateFunctions(OS);
1957 }
1958
1959 namespace llvm {
1960
EmitSubtarget(RecordKeeper & RK,raw_ostream & OS)1961 void EmitSubtarget(RecordKeeper &RK, raw_ostream &OS) {
1962 CodeGenTarget CGTarget(RK);
1963 SubtargetEmitter(RK, CGTarget).run(OS);
1964 }
1965
1966 } // end namespace llvm
1967