1 //===-- clear_cache.c - Implement __clear_cache ---------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "int_lib.h"
10 #if defined(__linux__)
11 #include <assert.h>
12 #endif
13 #include <stddef.h>
14
15 #if __APPLE__
16 #include <libkern/OSCacheControl.h>
17 #endif
18
19 #if defined(_WIN32)
20 // Forward declare Win32 APIs since the GCC mode driver does not handle the
21 // newer SDKs as well as needed.
22 uint32_t FlushInstructionCache(uintptr_t hProcess, void *lpBaseAddress,
23 uintptr_t dwSize);
24 uintptr_t GetCurrentProcess(void);
25 #endif
26
27 #if defined(__FreeBSD__) && defined(__arm__)
28 // clang-format off
29 #include <sys/types.h>
30 #include <machine/sysarch.h>
31 // clang-format on
32 #endif
33
34 #if defined(__NetBSD__) && defined(__arm__)
35 #include <machine/sysarch.h>
36 #endif
37
38 #if defined(__OpenBSD__) && (defined(__arm__) || defined(__mips__) || defined(__riscv))
39 // clang-format off
40 #include <sys/types.h>
41 #include <machine/sysarch.h>
42 // clang-format on
43 #endif
44
45 #if defined(__linux__) && defined(__mips__)
46 #include <sys/cachectl.h>
47 #include <sys/syscall.h>
48 #include <unistd.h>
49 #endif
50
51 #if defined(__linux__) && defined(__riscv)
52 // to get platform-specific syscall definitions
53 #include <linux/unistd.h>
54 #endif
55
56 // The compiler generates calls to __clear_cache() when creating
57 // trampoline functions on the stack for use with nested functions.
58 // It is expected to invalidate the instruction cache for the
59 // specified range.
60
__clear_cache(void * start,void * end)61 void __clear_cache(void *start, void *end) {
62 #if __i386__ || __x86_64__ || defined(_M_IX86) || defined(_M_X64)
63 // Intel processors have a unified instruction and data cache
64 // so there is nothing to do
65 #elif defined(_WIN32) && (defined(__arm__) || defined(__aarch64__))
66 FlushInstructionCache(GetCurrentProcess(), start, end - start);
67 #elif defined(__arm__) && !defined(__APPLE__)
68 #if defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__)
69 struct arm_sync_icache_args arg;
70
71 arg.addr = (uintptr_t)start;
72 arg.len = (uintptr_t)end - (uintptr_t)start;
73
74 sysarch(ARM_SYNC_ICACHE, &arg);
75 #elif defined(__linux__)
76 // We used to include asm/unistd.h for the __ARM_NR_cacheflush define, but
77 // it also brought many other unused defines, as well as a dependency on
78 // kernel headers to be installed.
79 //
80 // This value is stable at least since Linux 3.13 and should remain so for
81 // compatibility reasons, warranting it's re-definition here.
82 #define __ARM_NR_cacheflush 0x0f0002
83 register int start_reg __asm("r0") = (int)(intptr_t)start;
84 const register int end_reg __asm("r1") = (int)(intptr_t)end;
85 const register int flags __asm("r2") = 0;
86 const register int syscall_nr __asm("r7") = __ARM_NR_cacheflush;
87 __asm __volatile("svc 0x0"
88 : "=r"(start_reg)
89 : "r"(syscall_nr), "r"(start_reg), "r"(end_reg), "r"(flags));
90 assert(start_reg == 0 && "Cache flush syscall failed.");
91 #else
92 compilerrt_abort();
93 #endif
94 #elif defined(__linux__) && defined(__mips__)
95 const uintptr_t start_int = (uintptr_t)start;
96 const uintptr_t end_int = (uintptr_t)end;
97 syscall(__NR_cacheflush, start, (end_int - start_int), BCACHE);
98 #elif defined(__mips__) && defined(__OpenBSD__)
99 cacheflush(start, (uintptr_t)end - (uintptr_t)start, BCACHE);
100 #elif defined(__aarch64__) && !defined(__APPLE__)
101 uint64_t xstart = (uint64_t)(uintptr_t)start;
102 uint64_t xend = (uint64_t)(uintptr_t)end;
103
104 // Get Cache Type Info.
105 static uint64_t ctr_el0 = 0;
106 if (ctr_el0 == 0)
107 __asm __volatile("mrs %0, ctr_el0" : "=r"(ctr_el0));
108
109 // The DC and IC instructions must use 64-bit registers so we don't use
110 // uintptr_t in case this runs in an IPL32 environment.
111 uint64_t addr;
112
113 // If CTR_EL0.IDC is set, data cache cleaning to the point of unification
114 // is not required for instruction to data coherence.
115 if (((ctr_el0 >> 28) & 0x1) == 0x0) {
116 const size_t dcache_line_size = 4 << ((ctr_el0 >> 16) & 15);
117 for (addr = xstart & ~(dcache_line_size - 1); addr < xend;
118 addr += dcache_line_size)
119 __asm __volatile("dc cvau, %0" ::"r"(addr));
120 }
121 __asm __volatile("dsb ish");
122
123 // If CTR_EL0.DIC is set, instruction cache invalidation to the point of
124 // unification is not required for instruction to data coherence.
125 if (((ctr_el0 >> 29) & 0x1) == 0x0) {
126 const size_t icache_line_size = 4 << ((ctr_el0 >> 0) & 15);
127 for (addr = xstart & ~(icache_line_size - 1); addr < xend;
128 addr += icache_line_size)
129 __asm __volatile("ic ivau, %0" ::"r"(addr));
130 __asm __volatile("dsb ish");
131 }
132 __asm __volatile("isb sy");
133 #elif defined(__powerpc64__)
134 const size_t line_size = 32;
135 const size_t len = (uintptr_t)end - (uintptr_t)start;
136
137 const uintptr_t mask = ~(line_size - 1);
138 const uintptr_t start_line = ((uintptr_t)start) & mask;
139 const uintptr_t end_line = ((uintptr_t)start + len + line_size - 1) & mask;
140
141 for (uintptr_t line = start_line; line < end_line; line += line_size)
142 __asm__ volatile("dcbf 0, %0" : : "r"(line));
143 __asm__ volatile("sync");
144
145 for (uintptr_t line = start_line; line < end_line; line += line_size)
146 __asm__ volatile("icbi 0, %0" : : "r"(line));
147 __asm__ volatile("isync");
148 #elif defined(__sparc__)
149 const size_t dword_size = 8;
150 const size_t len = (uintptr_t)end - (uintptr_t)start;
151
152 const uintptr_t mask = ~(dword_size - 1);
153 const uintptr_t start_dword = ((uintptr_t)start) & mask;
154 const uintptr_t end_dword = ((uintptr_t)start + len + dword_size - 1) & mask;
155
156 for (uintptr_t dword = start_dword; dword < end_dword; dword += dword_size)
157 __asm__ volatile("flush %0" : : "r"(dword));
158 #elif defined(__riscv) && defined(__linux__)
159 // See: arch/riscv/include/asm/cacheflush.h, arch/riscv/kernel/sys_riscv.c
160 register void *start_reg __asm("a0") = start;
161 const register void *end_reg __asm("a1") = end;
162 // "0" means that we clear cache for all threads (SYS_RISCV_FLUSH_ICACHE_ALL)
163 const register long flags __asm("a2") = 0;
164 const register long syscall_nr __asm("a7") = __NR_riscv_flush_icache;
165 __asm __volatile("ecall"
166 : "=r"(start_reg)
167 : "r"(start_reg), "r"(end_reg), "r"(flags), "r"(syscall_nr));
168 assert(start_reg == 0 && "Cache flush syscall failed.");
169 #elif defined(__riscv) && defined(__OpenBSD__)
170 struct riscv_sync_icache_args arg;
171
172 arg.addr = (uintptr_t)start;
173 arg.len = (uintptr_t)end - (uintptr_t)start;
174
175 sysarch(RISCV_SYNC_ICACHE, &arg);
176 #else
177 #if __APPLE__
178 // On Darwin, sys_icache_invalidate() provides this functionality
179 sys_icache_invalidate(start, end - start);
180 #elif defined(__ve__)
181 __asm__ volatile("fencec 2");
182 #else
183 compilerrt_abort();
184 #endif
185 #endif
186 }
187