1 //===-- Passes.h - Target independent code generation passes ----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines interfaces to access the target independent code generation 10 // passes provided by the LLVM backend. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_CODEGEN_PASSES_H 15 #define LLVM_CODEGEN_PASSES_H 16 17 #include "llvm/Support/CodeGen.h" 18 #include "llvm/Support/Discriminator.h" 19 #include "llvm/CodeGen/RegAllocCommon.h" 20 21 #include <functional> 22 #include <string> 23 24 namespace llvm { 25 26 class FunctionPass; 27 class MachineFunction; 28 class MachineFunctionPass; 29 class MemoryBuffer; 30 class ModulePass; 31 class Pass; 32 class TargetMachine; 33 class TargetRegisterClass; 34 class raw_ostream; 35 36 } // End llvm namespace 37 38 // List of target independent CodeGen pass IDs. 39 namespace llvm { 40 FunctionPass *createAtomicExpandPass(); 41 42 /// createUnreachableBlockEliminationPass - The LLVM code generator does not 43 /// work well with unreachable basic blocks (what live ranges make sense for a 44 /// block that cannot be reached?). As such, a code generator should either 45 /// not instruction select unreachable blocks, or run this pass as its 46 /// last LLVM modifying pass to clean up blocks that are not reachable from 47 /// the entry block. 48 FunctionPass *createUnreachableBlockEliminationPass(); 49 50 /// createBasicBlockSections Pass - This pass assigns sections to machine 51 /// basic blocks and is enabled with -fbasic-block-sections. Buf is a memory 52 /// buffer that contains the list of functions and basic block ids to 53 /// selectively enable basic block sections. 54 MachineFunctionPass *createBasicBlockSectionsPass(const MemoryBuffer *Buf); 55 56 /// createMachineFunctionSplitterPass - This pass splits machine functions 57 /// using profile information. 58 MachineFunctionPass *createMachineFunctionSplitterPass(); 59 60 /// MachineFunctionPrinter pass - This pass prints out the machine function to 61 /// the given stream as a debugging tool. 62 MachineFunctionPass * 63 createMachineFunctionPrinterPass(raw_ostream &OS, 64 const std::string &Banner =""); 65 66 /// MIRPrinting pass - this pass prints out the LLVM IR into the given stream 67 /// using the MIR serialization format. 68 MachineFunctionPass *createPrintMIRPass(raw_ostream &OS); 69 70 /// This pass resets a MachineFunction when it has the FailedISel property 71 /// as if it was just created. 72 /// If EmitFallbackDiag is true, the pass will emit a 73 /// DiagnosticInfoISelFallback for every MachineFunction it resets. 74 /// If AbortOnFailedISel is true, abort compilation instead of resetting. 75 MachineFunctionPass *createResetMachineFunctionPass(bool EmitFallbackDiag, 76 bool AbortOnFailedISel); 77 78 /// createCodeGenPreparePass - Transform the code to expose more pattern 79 /// matching during instruction selection. 80 FunctionPass *createCodeGenPreparePass(); 81 82 /// AtomicExpandID -- Lowers atomic operations in terms of either cmpxchg 83 /// load-linked/store-conditional loops. 84 extern char &AtomicExpandID; 85 86 /// MachineLoopInfo - This pass is a loop analysis pass. 87 extern char &MachineLoopInfoID; 88 89 /// MachineDominators - This pass is a machine dominators analysis pass. 90 extern char &MachineDominatorsID; 91 92 /// MachineDominanaceFrontier - This pass is a machine dominators analysis. 93 extern char &MachineDominanceFrontierID; 94 95 /// MachineRegionInfo - This pass computes SESE regions for machine functions. 96 extern char &MachineRegionInfoPassID; 97 98 /// EdgeBundles analysis - Bundle machine CFG edges. 99 extern char &EdgeBundlesID; 100 101 /// LiveVariables pass - This pass computes the set of blocks in which each 102 /// variable is life and sets machine operand kill flags. 103 extern char &LiveVariablesID; 104 105 /// PHIElimination - This pass eliminates machine instruction PHI nodes 106 /// by inserting copy instructions. This destroys SSA information, but is the 107 /// desired input for some register allocators. This pass is "required" by 108 /// these register allocator like this: AU.addRequiredID(PHIEliminationID); 109 extern char &PHIEliminationID; 110 111 /// LiveIntervals - This analysis keeps track of the live ranges of virtual 112 /// and physical registers. 113 extern char &LiveIntervalsID; 114 115 /// LiveStacks pass. An analysis keeping track of the liveness of stack slots. 116 extern char &LiveStacksID; 117 118 /// TwoAddressInstruction - This pass reduces two-address instructions to 119 /// use two operands. This destroys SSA information but it is desired by 120 /// register allocators. 121 extern char &TwoAddressInstructionPassID; 122 123 /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs. 124 extern char &ProcessImplicitDefsID; 125 126 /// RegisterCoalescer - This pass merges live ranges to eliminate copies. 127 extern char &RegisterCoalescerID; 128 129 /// MachineScheduler - This pass schedules machine instructions. 130 extern char &MachineSchedulerID; 131 132 /// PostMachineScheduler - This pass schedules machine instructions postRA. 133 extern char &PostMachineSchedulerID; 134 135 /// SpillPlacement analysis. Suggest optimal placement of spill code between 136 /// basic blocks. 137 extern char &SpillPlacementID; 138 139 /// ShrinkWrap pass. Look for the best place to insert save and restore 140 // instruction and update the MachineFunctionInfo with that information. 141 extern char &ShrinkWrapID; 142 143 /// LiveRangeShrink pass. Move instruction close to its definition to shrink 144 /// the definition's live range. 145 extern char &LiveRangeShrinkID; 146 147 /// Greedy register allocator. 148 extern char &RAGreedyID; 149 150 /// Basic register allocator. 151 extern char &RABasicID; 152 153 /// VirtRegRewriter pass. Rewrite virtual registers to physical registers as 154 /// assigned in VirtRegMap. 155 extern char &VirtRegRewriterID; 156 FunctionPass *createVirtRegRewriter(bool ClearVirtRegs = true); 157 158 /// UnreachableMachineBlockElimination - This pass removes unreachable 159 /// machine basic blocks. 160 extern char &UnreachableMachineBlockElimID; 161 162 /// DeadMachineInstructionElim - This pass removes dead machine instructions. 163 extern char &DeadMachineInstructionElimID; 164 165 /// This pass adds dead/undef flags after analyzing subregister lanes. 166 extern char &DetectDeadLanesID; 167 168 /// This pass perform post-ra machine sink for COPY instructions. 169 extern char &PostRAMachineSinkingID; 170 171 /// This pass adds flow sensitive discriminators. 172 extern char &MIRAddFSDiscriminatorsID; 173 174 /// FastRegisterAllocation Pass - This pass register allocates as fast as 175 /// possible. It is best suited for debug code where live ranges are short. 176 /// 177 FunctionPass *createFastRegisterAllocator(); 178 FunctionPass *createFastRegisterAllocator(RegClassFilterFunc F, 179 bool ClearVirtRegs); 180 181 /// BasicRegisterAllocation Pass - This pass implements a degenerate global 182 /// register allocator using the basic regalloc framework. 183 /// 184 FunctionPass *createBasicRegisterAllocator(); 185 FunctionPass *createBasicRegisterAllocator(RegClassFilterFunc F); 186 187 /// Greedy register allocation pass - This pass implements a global register 188 /// allocator for optimized builds. 189 /// 190 FunctionPass *createGreedyRegisterAllocator(); 191 FunctionPass *createGreedyRegisterAllocator(RegClassFilterFunc F); 192 193 /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean 194 /// Quadratic Prograaming (PBQP) based register allocator. 195 /// 196 FunctionPass *createDefaultPBQPRegisterAllocator(); 197 198 /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code, 199 /// and eliminates abstract frame references. 200 extern char &PrologEpilogCodeInserterID; 201 MachineFunctionPass *createPrologEpilogInserterPass(); 202 203 /// ExpandPostRAPseudos - This pass expands pseudo instructions after 204 /// register allocation. 205 extern char &ExpandPostRAPseudosID; 206 207 /// PostRAHazardRecognizer - This pass runs the post-ra hazard 208 /// recognizer. 209 extern char &PostRAHazardRecognizerID; 210 211 /// PostRAScheduler - This pass performs post register allocation 212 /// scheduling. 213 extern char &PostRASchedulerID; 214 215 /// BranchFolding - This pass performs machine code CFG based 216 /// optimizations to delete branches to branches, eliminate branches to 217 /// successor blocks (creating fall throughs), and eliminating branches over 218 /// branches. 219 extern char &BranchFolderPassID; 220 221 /// BranchRelaxation - This pass replaces branches that need to jump further 222 /// than is supported by a branch instruction. 223 extern char &BranchRelaxationPassID; 224 225 /// MachineFunctionPrinterPass - This pass prints out MachineInstr's. 226 extern char &MachineFunctionPrinterPassID; 227 228 /// MIRPrintingPass - this pass prints out the LLVM IR using the MIR 229 /// serialization format. 230 extern char &MIRPrintingPassID; 231 232 /// TailDuplicate - Duplicate blocks with unconditional branches 233 /// into tails of their predecessors. 234 extern char &TailDuplicateID; 235 236 /// Duplicate blocks with unconditional branches into tails of their 237 /// predecessors. Variant that works before register allocation. 238 extern char &EarlyTailDuplicateID; 239 240 /// MachineTraceMetrics - This pass computes critical path and CPU resource 241 /// usage in an ensemble of traces. 242 extern char &MachineTraceMetricsID; 243 244 /// EarlyIfConverter - This pass performs if-conversion on SSA form by 245 /// inserting cmov instructions. 246 extern char &EarlyIfConverterID; 247 248 /// EarlyIfPredicator - This pass performs if-conversion on SSA form by 249 /// predicating if/else block and insert select at the join point. 250 extern char &EarlyIfPredicatorID; 251 252 /// This pass performs instruction combining using trace metrics to estimate 253 /// critical-path and resource depth. 254 extern char &MachineCombinerID; 255 256 /// StackSlotColoring - This pass performs stack coloring and merging. 257 /// It merges disjoint allocas to reduce the stack size. 258 extern char &StackColoringID; 259 260 /// IfConverter - This pass performs machine code if conversion. 261 extern char &IfConverterID; 262 263 FunctionPass *createIfConverter( 264 std::function<bool(const MachineFunction &)> Ftor); 265 266 /// MachineBlockPlacement - This pass places basic blocks based on branch 267 /// probabilities. 268 extern char &MachineBlockPlacementID; 269 270 /// MachineBlockPlacementStats - This pass collects statistics about the 271 /// basic block placement using branch probabilities and block frequency 272 /// information. 273 extern char &MachineBlockPlacementStatsID; 274 275 /// GCLowering Pass - Used by gc.root to perform its default lowering 276 /// operations. 277 FunctionPass *createGCLoweringPass(); 278 279 /// GCLowering Pass - Used by gc.root to perform its default lowering 280 /// operations. 281 extern char &GCLoweringID; 282 283 /// ShadowStackGCLowering - Implements the custom lowering mechanism 284 /// used by the shadow stack GC. Only runs on functions which opt in to 285 /// the shadow stack collector. 286 FunctionPass *createShadowStackGCLoweringPass(); 287 288 /// ShadowStackGCLowering - Implements the custom lowering mechanism 289 /// used by the shadow stack GC. 290 extern char &ShadowStackGCLoweringID; 291 292 /// GCMachineCodeAnalysis - Target-independent pass to mark safe points 293 /// in machine code. Must be added very late during code generation, just 294 /// prior to output, and importantly after all CFG transformations (such as 295 /// branch folding). 296 extern char &GCMachineCodeAnalysisID; 297 298 /// Creates a pass to print GC metadata. 299 /// 300 FunctionPass *createGCInfoPrinter(raw_ostream &OS); 301 302 /// MachineCSE - This pass performs global CSE on machine instructions. 303 extern char &MachineCSEID; 304 305 /// MIRCanonicalizer - This pass canonicalizes MIR by renaming vregs 306 /// according to the semantics of the instruction as well as hoists 307 /// code. 308 extern char &MIRCanonicalizerID; 309 310 /// ImplicitNullChecks - This pass folds null pointer checks into nearby 311 /// memory operations. 312 extern char &ImplicitNullChecksID; 313 314 /// This pass performs loop invariant code motion on machine instructions. 315 extern char &MachineLICMID; 316 317 /// This pass performs loop invariant code motion on machine instructions. 318 /// This variant works before register allocation. \see MachineLICMID. 319 extern char &EarlyMachineLICMID; 320 321 /// MachineSinking - This pass performs sinking on machine instructions. 322 extern char &MachineSinkingID; 323 324 /// MachineCopyPropagation - This pass performs copy propagation on 325 /// machine instructions. 326 extern char &MachineCopyPropagationID; 327 328 /// PeepholeOptimizer - This pass performs peephole optimizations - 329 /// like extension and comparison eliminations. 330 extern char &PeepholeOptimizerID; 331 332 /// OptimizePHIs - This pass optimizes machine instruction PHIs 333 /// to take advantage of opportunities created during DAG legalization. 334 extern char &OptimizePHIsID; 335 336 /// StackSlotColoring - This pass performs stack slot coloring. 337 extern char &StackSlotColoringID; 338 339 /// This pass lays out funclets contiguously. 340 extern char &FuncletLayoutID; 341 342 /// This pass inserts the XRay instrumentation sleds if they are supported by 343 /// the target platform. 344 extern char &XRayInstrumentationID; 345 346 /// This pass inserts FEntry calls 347 extern char &FEntryInserterID; 348 349 /// This pass implements the "patchable-function" attribute. 350 extern char &PatchableFunctionID; 351 352 /// createStackProtectorPass - This pass adds stack protectors to functions. 353 /// 354 FunctionPass *createStackProtectorPass(); 355 356 /// createMachineVerifierPass - This pass verifies cenerated machine code 357 /// instructions for correctness. 358 /// 359 FunctionPass *createMachineVerifierPass(const std::string& Banner); 360 361 /// createDwarfEHPass - This pass mulches exception handling code into a form 362 /// adapted to code generation. Required if using dwarf exception handling. 363 FunctionPass *createDwarfEHPass(CodeGenOpt::Level OptLevel); 364 365 /// createWinEHPass - Prepares personality functions used by MSVC on Windows, 366 /// in addition to the Itanium LSDA based personalities. 367 FunctionPass *createWinEHPass(bool DemoteCatchSwitchPHIOnly = false); 368 369 /// createSjLjEHPreparePass - This pass adapts exception handling code to use 370 /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow. 371 /// 372 FunctionPass *createSjLjEHPreparePass(const TargetMachine *TM); 373 374 /// createWasmEHPass - This pass adapts exception handling code to use 375 /// WebAssembly's exception handling scheme. 376 FunctionPass *createWasmEHPass(); 377 378 /// LocalStackSlotAllocation - This pass assigns local frame indices to stack 379 /// slots relative to one another and allocates base registers to access them 380 /// when it is estimated by the target to be out of range of normal frame 381 /// pointer or stack pointer index addressing. 382 extern char &LocalStackSlotAllocationID; 383 384 /// This pass expands pseudo-instructions, reserves registers and adjusts 385 /// machine frame information. 386 extern char &FinalizeISelID; 387 388 /// UnpackMachineBundles - This pass unpack machine instruction bundles. 389 extern char &UnpackMachineBundlesID; 390 391 FunctionPass * 392 createUnpackMachineBundles(std::function<bool(const MachineFunction &)> Ftor); 393 394 /// FinalizeMachineBundles - This pass finalize machine instruction 395 /// bundles (created earlier, e.g. during pre-RA scheduling). 396 extern char &FinalizeMachineBundlesID; 397 398 /// StackMapLiveness - This pass analyses the register live-out set of 399 /// stackmap/patchpoint intrinsics and attaches the calculated information to 400 /// the intrinsic for later emission to the StackMap. 401 extern char &StackMapLivenessID; 402 403 /// RemoveRedundantDebugValues pass. 404 extern char &RemoveRedundantDebugValuesID; 405 406 /// LiveDebugValues pass 407 extern char &LiveDebugValuesID; 408 409 /// createJumpInstrTables - This pass creates jump-instruction tables. 410 ModulePass *createJumpInstrTablesPass(); 411 412 /// InterleavedAccess Pass - This pass identifies and matches interleaved 413 /// memory accesses to target specific intrinsics. 414 /// 415 FunctionPass *createInterleavedAccessPass(); 416 417 /// InterleavedLoadCombines Pass - This pass identifies interleaved loads and 418 /// combines them into wide loads detectable by InterleavedAccessPass 419 /// 420 FunctionPass *createInterleavedLoadCombinePass(); 421 422 /// LowerEmuTLS - This pass generates __emutls_[vt].xyz variables for all 423 /// TLS variables for the emulated TLS model. 424 /// 425 ModulePass *createLowerEmuTLSPass(); 426 427 /// This pass lowers the \@llvm.load.relative and \@llvm.objc.* intrinsics to 428 /// instructions. This is unsafe to do earlier because a pass may combine the 429 /// constant initializer into the load, which may result in an overflowing 430 /// evaluation. 431 ModulePass *createPreISelIntrinsicLoweringPass(); 432 433 /// GlobalMerge - This pass merges internal (by default) globals into structs 434 /// to enable reuse of a base pointer by indexed addressing modes. 435 /// It can also be configured to focus on size optimizations only. 436 /// 437 Pass *createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, 438 bool OnlyOptimizeForSize = false, 439 bool MergeExternalByDefault = false); 440 441 /// This pass splits the stack into a safe stack and an unsafe stack to 442 /// protect against stack-based overflow vulnerabilities. 443 FunctionPass *createSafeStackPass(); 444 445 /// This pass detects subregister lanes in a virtual register that are used 446 /// independently of other lanes and splits them into separate virtual 447 /// registers. 448 extern char &RenameIndependentSubregsID; 449 450 /// This pass is executed POST-RA to collect which physical registers are 451 /// preserved by given machine function. 452 FunctionPass *createRegUsageInfoCollector(); 453 454 /// Return a MachineFunction pass that identifies call sites 455 /// and propagates register usage information of callee to caller 456 /// if available with PysicalRegisterUsageInfo pass. 457 FunctionPass *createRegUsageInfoPropPass(); 458 459 /// This pass performs software pipelining on machine instructions. 460 extern char &MachinePipelinerID; 461 462 /// This pass frees the memory occupied by the MachineFunction. 463 FunctionPass *createFreeMachineFunctionPass(); 464 465 /// This pass performs outlining on machine instructions directly before 466 /// printing assembly. 467 ModulePass *createMachineOutlinerPass(bool RunOnAllFunctions = true); 468 469 /// This pass expands the experimental reduction intrinsics into sequences of 470 /// shuffles. 471 FunctionPass *createExpandReductionsPass(); 472 473 // This pass replaces intrinsics operating on vector operands with calls to 474 // the corresponding function in a vector library (e.g., SVML, libmvec). 475 FunctionPass *createReplaceWithVeclibLegacyPass(); 476 477 /// This pass expands the vector predication intrinsics into unpredicated 478 /// instructions with selects or just the explicit vector length into the 479 /// predicate mask. 480 FunctionPass *createExpandVectorPredicationPass(); 481 482 // This pass expands memcmp() to load/stores. 483 FunctionPass *createExpandMemCmpPass(); 484 485 /// Creates Break False Dependencies pass. \see BreakFalseDeps.cpp 486 FunctionPass *createBreakFalseDeps(); 487 488 // This pass expands indirectbr instructions. 489 FunctionPass *createIndirectBrExpandPass(); 490 491 /// Creates CFI Instruction Inserter pass. \see CFIInstrInserter.cpp 492 FunctionPass *createCFIInstrInserter(); 493 494 /// Creates CFGuard longjmp target identification pass. 495 /// \see CFGuardLongjmp.cpp 496 FunctionPass *createCFGuardLongjmpPass(); 497 498 /// Creates EHContGuard catchret target identification pass. 499 /// \see EHContGuardCatchret.cpp 500 FunctionPass *createEHContGuardCatchretPass(); 501 502 /// Create Hardware Loop pass. \see HardwareLoops.cpp 503 FunctionPass *createHardwareLoopsPass(); 504 505 /// This pass inserts pseudo probe annotation for callsite profiling. 506 FunctionPass *createPseudoProbeInserter(); 507 508 /// Create IR Type Promotion pass. \see TypePromotion.cpp 509 FunctionPass *createTypePromotionPass(); 510 511 /// Add Flow Sensitive Discriminators. PassNum specifies the 512 /// sequence number of this pass (starting from 1). 513 FunctionPass * 514 createMIRAddFSDiscriminatorsPass(sampleprof::FSDiscriminatorPass P); 515 516 /// Creates MIR Debugify pass. \see MachineDebugify.cpp 517 ModulePass *createDebugifyMachineModulePass(); 518 519 /// Creates MIR Strip Debug pass. \see MachineStripDebug.cpp 520 /// If OnlyDebugified is true then it will only strip debug info if it was 521 /// added by a Debugify pass. The module will be left unchanged if the debug 522 /// info was generated by another source such as clang. 523 ModulePass *createStripDebugMachineModulePass(bool OnlyDebugified); 524 525 /// Creates MIR Check Debug pass. \see MachineCheckDebugify.cpp 526 ModulePass *createCheckDebugMachineModulePass(); 527 528 /// The pass fixups statepoint machine instruction to replace usage of 529 /// caller saved registers with stack slots. 530 extern char &FixupStatepointCallerSavedID; 531 532 /// The pass transforms load/store <256 x i32> to AMX load/store intrinsics 533 /// or split the data to two <128 x i32>. 534 FunctionPass *createX86LowerAMXTypePass(); 535 536 /// The pass insert tile config intrinsics for AMX fast register allocation. 537 FunctionPass *createX86PreAMXConfigPass(); 538 539 /// The pass transforms amx intrinsics to scalar operation if the function has 540 /// optnone attribute or it is O0. 541 FunctionPass *createX86LowerAMXIntrinsicsPass(); 542 } // End llvm namespace 543 544 #endif 545