1//=-HexagonScheduleV60.td - HexagonV60 Scheduling Definitions *- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9
10// There are four SLOTS (four parallel pipelines) in Hexagon V60 machine.
11// This file describes that machine information.
12//
13//    |===========|==================================================|
14//    | PIPELINE  |              Instruction Classes                 |
15//    |===========|==================================================|
16//    | SLOT0     |  LD       ST    ALU32     MEMOP     NV    SYSTEM |
17//    |-----------|--------------------------------------------------|
18//    | SLOT1     |  LD       ST    ALU32                            |
19//    |-----------|--------------------------------------------------|
20//    | SLOT2     |  XTYPE          ALU32     J         JR           |
21//    |-----------|--------------------------------------------------|
22//    | SLOT3     |  XTYPE          ALU32     J         CR           |
23//    |===========|==================================================|
24//
25//
26// In addition to using the above SLOTS, there are also six vector pipelines
27// in the CVI co-processor in the Hexagon V60 machine.
28//
29//      |=========| |=========| |=========| |=========| |=========| |=========|
30// SLOT | CVI_LD  | |CVI_MPY3 | |CVI_MPY2 | |CVI_SHIFT| |CVI_XLANE| | CVI_ST  |
31// ==== |=========| |=========| |=========| |=========| |=========| |=========|
32// S0-3 |         | | CVI_VA  | | CVI_VA  | | CVI_VA  | | CVI_VA  | |         |
33// S2-3 |         | | CVI_VX  | | CVI_VX  | |         | |         | |         |
34// S0-3 |         | |         | |         | |         | | CVI_VP  | |         |
35// S0-3 |         | |         | |         | | CVI_VS  | |         | |         |
36// S0-1 |(CVI_LD) | | CVI_LD  | | CVI_LD  | | CVI_LD  | | CVI_LD  | |         |
37// S0-1 |(C*TMP_LD) |         | |         | |         | |         | |         |
38// S01  |(C*_LDU) | |         | |         | |         | | C*_LDU  | |         |
39// S0   |         | | CVI_ST  | | CVI_ST  | | CVI_ST  | | CVI_ST  | |(CVI_ST) |
40// S0   |         | |         | |         | |         | |         | |(C*TMP_ST)
41// S01  |         | |         | |         | |         | | VSTU    | |(C*_STU) |
42//      |=========| |=========| |=========| |=========| |=========| |=========|
43//                  |=====================| |=====================|
44//                  | CVI_MPY2 & CVI_MPY3 | |CVI_XLANE & CVI_SHIFT|
45//                  |=====================| |=====================|
46// S0-3             | CVI_VA_DV           | | CVI_VA_DV           |
47// S0-3             |                     | | CVI_VP_DV           |
48// S2-3             | CVI_VX_DV           | |                     |
49//                  |=====================| |=====================|
50//      |=====================================================================|
51// S0-3 | CVI_HIST   Histogram                                                |
52// S0123| CVI_VA_EXT Extract                                                  |
53//      |=====================================================================|
54
55def HexagonV60ItinList : DepScalarItinV60, ScalarItin,
56                         DepHVXItinV60,
57                         HVXItin, PseudoItin {
58  list<InstrItinData> ItinList =
59    !listconcat(DepScalarItinV60_list, ScalarItin_list,
60                DepHVXItinV60_list, HVXItin_list, PseudoItin_list);
61}
62
63def HexagonItinerariesV60 :
64      ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
65                            CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
66                            CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL,
67                            CVI_ALL_NOMEM, CVI_ZW],
68                            [Hex_FWD, HVX_FWD], HexagonV60ItinList.ItinList>;
69
70def HexagonModelV60 : SchedMachineModel {
71  // Max issue per cycle == bundle width.
72  let IssueWidth = 4;
73  let Itineraries = HexagonItinerariesV60;
74  let LoadLatency = 1;
75  let CompleteModel = 0;
76}
77
78//===----------------------------------------------------------------------===//
79// Hexagon V60 Resource Definitions -
80//===----------------------------------------------------------------------===//
81