1 //===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Subclass of MipsDAGToDAGISel specialized for mips32/64.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsSEISelDAGToDAG.h"
14 #include "MCTargetDesc/MipsBaseInfo.h"
15 #include "Mips.h"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsRegisterInfo.h"
19 #include "llvm/CodeGen/MachineConstantPool.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/SelectionDAGNodes.h"
25 #include "llvm/IR/CFG.h"
26 #include "llvm/IR/Dominators.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/IntrinsicsMips.h"
31 #include "llvm/IR/Type.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetMachine.h"
36 using namespace llvm;
37 
38 #define DEBUG_TYPE "mips-isel"
39 
runOnMachineFunction(MachineFunction & MF)40 bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
41   Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
42   if (Subtarget->inMips16Mode())
43     return false;
44   return MipsDAGToDAGISel::runOnMachineFunction(MF);
45 }
46 
getAnalysisUsage(AnalysisUsage & AU) const47 void MipsSEDAGToDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
48   AU.addRequired<DominatorTreeWrapperPass>();
49   SelectionDAGISel::getAnalysisUsage(AU);
50 }
51 
addDSPCtrlRegOperands(bool IsDef,MachineInstr & MI,MachineFunction & MF)52 void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
53                                                MachineFunction &MF) {
54   MachineInstrBuilder MIB(MF, &MI);
55   unsigned Mask = MI.getOperand(1).getImm();
56   unsigned Flag =
57       IsDef ? RegState::ImplicitDefine : RegState::Implicit | RegState::Undef;
58 
59   if (Mask & 1)
60     MIB.addReg(Mips::DSPPos, Flag);
61 
62   if (Mask & 2)
63     MIB.addReg(Mips::DSPSCount, Flag);
64 
65   if (Mask & 4)
66     MIB.addReg(Mips::DSPCarry, Flag);
67 
68   if (Mask & 8)
69     MIB.addReg(Mips::DSPOutFlag, Flag);
70 
71   if (Mask & 16)
72     MIB.addReg(Mips::DSPCCond, Flag);
73 
74   if (Mask & 32)
75     MIB.addReg(Mips::DSPEFI, Flag);
76 }
77 
getMSACtrlReg(const SDValue RegIdx) const78 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
79   uint64_t RegNum = cast<ConstantSDNode>(RegIdx)->getZExtValue();
80   return Mips::MSACtrlRegClass.getRegister(RegNum);
81 }
82 
replaceUsesWithZeroReg(MachineRegisterInfo * MRI,const MachineInstr & MI)83 bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
84                                                 const MachineInstr& MI) {
85   unsigned DstReg = 0, ZeroReg = 0;
86 
87   // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
88   if ((MI.getOpcode() == Mips::ADDiu) &&
89       (MI.getOperand(1).getReg() == Mips::ZERO) &&
90       (MI.getOperand(2).isImm()) &&
91       (MI.getOperand(2).getImm() == 0)) {
92     DstReg = MI.getOperand(0).getReg();
93     ZeroReg = Mips::ZERO;
94   } else if ((MI.getOpcode() == Mips::DADDiu) &&
95              (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
96              (MI.getOperand(2).isImm()) &&
97              (MI.getOperand(2).getImm() == 0)) {
98     DstReg = MI.getOperand(0).getReg();
99     ZeroReg = Mips::ZERO_64;
100   }
101 
102   if (!DstReg)
103     return false;
104 
105   // Replace uses with ZeroReg.
106   for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
107        E = MRI->use_end(); U != E;) {
108     MachineOperand &MO = *U;
109     unsigned OpNo = U.getOperandNo();
110     MachineInstr *MI = MO.getParent();
111     ++U;
112 
113     // Do not replace if it is a phi's operand or is tied to def operand.
114     if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
115       continue;
116 
117     // Also, we have to check that the register class of the operand
118     // contains the zero register.
119     if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg))
120       continue;
121 
122     MO.setReg(ZeroReg);
123   }
124 
125   return true;
126 }
127 
emitMCountABI(MachineInstr & MI,MachineBasicBlock & MBB,MachineFunction & MF)128 void MipsSEDAGToDAGISel::emitMCountABI(MachineInstr &MI, MachineBasicBlock &MBB,
129                                        MachineFunction &MF) {
130   MachineInstrBuilder MIB(MF, &MI);
131   if (!Subtarget->isABI_O32()) { // N32, N64
132     // Save current return address.
133     BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Mips::OR64))
134         .addDef(Mips::AT_64)
135         .addUse(Mips::RA_64, RegState::Undef)
136         .addUse(Mips::ZERO_64);
137     // Stops instruction above from being removed later on.
138     MIB.addUse(Mips::AT_64, RegState::Implicit);
139   } else {  // O32
140     // Save current return address.
141     BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Mips::OR))
142         .addDef(Mips::AT)
143         .addUse(Mips::RA, RegState::Undef)
144         .addUse(Mips::ZERO);
145     // _mcount pops 2 words from stack.
146     BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Mips::ADDiu))
147         .addDef(Mips::SP)
148         .addUse(Mips::SP)
149         .addImm(-8);
150     // Stops first instruction above from being removed later on.
151     MIB.addUse(Mips::AT, RegState::Implicit);
152   }
153 }
154 
processFunctionAfterISel(MachineFunction & MF)155 void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
156   MF.getInfo<MipsFunctionInfo>()->initGlobalBaseReg(MF);
157 
158   MachineRegisterInfo *MRI = &MF.getRegInfo();
159 
160   for (auto &MBB: MF) {
161     for (auto &MI: MBB) {
162       switch (MI.getOpcode()) {
163       case Mips::RDDSP:
164         addDSPCtrlRegOperands(false, MI, MF);
165         break;
166       case Mips::WRDSP:
167         addDSPCtrlRegOperands(true, MI, MF);
168         break;
169       case Mips::BuildPairF64_64:
170       case Mips::ExtractElementF64_64:
171         if (!Subtarget->useOddSPReg()) {
172           MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
173           break;
174         }
175         LLVM_FALLTHROUGH;
176       case Mips::BuildPairF64:
177       case Mips::ExtractElementF64:
178         if (Subtarget->isABI_FPXX() && !Subtarget->hasMTHC1())
179           MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
180         break;
181       case Mips::JAL:
182       case Mips::JAL_MM:
183         if (MI.getOperand(0).isGlobal() &&
184             MI.getOperand(0).getGlobal()->getGlobalIdentifier() == "_mcount")
185           emitMCountABI(MI, MBB, MF);
186         break;
187       case Mips::JALRPseudo:
188       case Mips::JALR64Pseudo:
189       case Mips::JALR16_MM:
190         if (MI.getOperand(2).isMCSymbol() &&
191             MI.getOperand(2).getMCSymbol()->getName() == "_mcount")
192           emitMCountABI(MI, MBB, MF);
193         break;
194       case Mips::JALR:
195         if (MI.getOperand(3).isMCSymbol() &&
196             MI.getOperand(3).getMCSymbol()->getName() == "_mcount")
197           emitMCountABI(MI, MBB, MF);
198         break;
199       default:
200         replaceUsesWithZeroReg(MRI, MI);
201       }
202     }
203   }
204 }
205 
selectAddE(SDNode * Node,const SDLoc & DL) const206 void MipsSEDAGToDAGISel::selectAddE(SDNode *Node, const SDLoc &DL) const {
207   SDValue InFlag = Node->getOperand(2);
208   unsigned Opc = InFlag.getOpcode();
209   SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
210   EVT VT = LHS.getValueType();
211 
212   // In the base case, we can rely on the carry bit from the addsc
213   // instruction.
214   if (Opc == ISD::ADDC) {
215     SDValue Ops[3] = {LHS, RHS, InFlag};
216     CurDAG->SelectNodeTo(Node, Mips::ADDWC, VT, MVT::Glue, Ops);
217     return;
218   }
219 
220   assert(Opc == ISD::ADDE && "ISD::ADDE not in a chain of ADDE nodes!");
221 
222   // The more complex case is when there is a chain of ISD::ADDE nodes like:
223   // (adde (adde (adde (addc a b) c) d) e).
224   //
225   // The addwc instruction does not write to the carry bit, instead it writes
226   // to bit 20 of the dsp control register. To match this series of nodes, each
227   // intermediate adde node must be expanded to write the carry bit before the
228   // addition.
229 
230   // Start by reading the overflow field for addsc and moving the value to the
231   // carry field. The usage of 1 here with MipsISD::RDDSP / Mips::WRDSP
232   // corresponds to reading/writing the entire control register to/from a GPR.
233 
234   SDValue CstOne = CurDAG->getTargetConstant(1, DL, MVT::i32);
235 
236   SDValue OuFlag = CurDAG->getTargetConstant(20, DL, MVT::i32);
237 
238   SDNode *DSPCtrlField = CurDAG->getMachineNode(Mips::RDDSP, DL, MVT::i32,
239                                                 MVT::Glue, CstOne, InFlag);
240 
241   SDNode *Carry = CurDAG->getMachineNode(
242       Mips::EXT, DL, MVT::i32, SDValue(DSPCtrlField, 0), OuFlag, CstOne);
243 
244   SDValue Ops[4] = {SDValue(DSPCtrlField, 0),
245                     CurDAG->getTargetConstant(6, DL, MVT::i32), CstOne,
246                     SDValue(Carry, 0)};
247   SDNode *DSPCFWithCarry = CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, Ops);
248 
249   // My reading of the MIPS DSP 3.01 specification isn't as clear as I
250   // would like about whether bit 20 always gets overwritten by addwc.
251   // Hence take an extremely conservative view and presume it's sticky. We
252   // therefore need to clear it.
253 
254   SDValue Zero = CurDAG->getRegister(Mips::ZERO, MVT::i32);
255 
256   SDValue InsOps[4] = {Zero, OuFlag, CstOne, SDValue(DSPCFWithCarry, 0)};
257   SDNode *DSPCtrlFinal =
258       CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, InsOps);
259 
260   SDNode *WrDSP = CurDAG->getMachineNode(Mips::WRDSP, DL, MVT::Glue,
261                                          SDValue(DSPCtrlFinal, 0), CstOne);
262 
263   SDValue Operands[3] = {LHS, RHS, SDValue(WrDSP, 0)};
264   CurDAG->SelectNodeTo(Node, Mips::ADDWC, VT, MVT::Glue, Operands);
265 }
266 
267 /// Match frameindex
selectAddrFrameIndex(SDValue Addr,SDValue & Base,SDValue & Offset) const268 bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base,
269                                               SDValue &Offset) const {
270   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
271     EVT ValTy = Addr.getValueType();
272 
273     Base   = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
274     Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), ValTy);
275     return true;
276   }
277   return false;
278 }
279 
280 /// Match frameindex+offset and frameindex|offset
selectAddrFrameIndexOffset(SDValue Addr,SDValue & Base,SDValue & Offset,unsigned OffsetBits,unsigned ShiftAmount=0) const281 bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(
282     SDValue Addr, SDValue &Base, SDValue &Offset, unsigned OffsetBits,
283     unsigned ShiftAmount = 0) const {
284   if (CurDAG->isBaseWithConstantOffset(Addr)) {
285     ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
286     if (isIntN(OffsetBits + ShiftAmount, CN->getSExtValue())) {
287       EVT ValTy = Addr.getValueType();
288 
289       // If the first operand is a FI, get the TargetFI Node
290       if (FrameIndexSDNode *FIN =
291               dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
292         Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
293       else {
294         Base = Addr.getOperand(0);
295         // If base is a FI, additional offset calculation is done in
296         // eliminateFrameIndex, otherwise we need to check the alignment
297         const Align Alignment(1ULL << ShiftAmount);
298         if (!isAligned(Alignment, CN->getZExtValue()))
299           return false;
300       }
301 
302       Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr),
303                                          ValTy);
304       return true;
305     }
306   }
307   return false;
308 }
309 
310 /// ComplexPattern used on MipsInstrInfo
311 /// Used on Mips Load/Store instructions
selectAddrRegImm(SDValue Addr,SDValue & Base,SDValue & Offset) const312 bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
313                                           SDValue &Offset) const {
314   // if Address is FI, get the TargetFrameIndex.
315   if (selectAddrFrameIndex(Addr, Base, Offset))
316     return true;
317 
318   // on PIC code Load GA
319   if (Addr.getOpcode() == MipsISD::Wrapper) {
320     Base   = Addr.getOperand(0);
321     Offset = Addr.getOperand(1);
322     return true;
323   }
324 
325   if (!TM.isPositionIndependent()) {
326     if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
327         Addr.getOpcode() == ISD::TargetGlobalAddress))
328       return false;
329   }
330 
331   // Addresses of the form FI+const or FI|const
332   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
333     return true;
334 
335   // Operand is a result from an ADD.
336   if (Addr.getOpcode() == ISD::ADD) {
337     // When loading from constant pools, load the lower address part in
338     // the instruction itself. Example, instead of:
339     //  lui $2, %hi($CPI1_0)
340     //  addiu $2, $2, %lo($CPI1_0)
341     //  lwc1 $f0, 0($2)
342     // Generate:
343     //  lui $2, %hi($CPI1_0)
344     //  lwc1 $f0, %lo($CPI1_0)($2)
345     if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
346         Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
347       SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
348       if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
349           isa<JumpTableSDNode>(Opnd0)) {
350         Base = Addr.getOperand(0);
351         Offset = Opnd0;
352         return true;
353       }
354     }
355   }
356 
357   return false;
358 }
359 
360 /// ComplexPattern used on MipsInstrInfo
361 /// Used on Mips Load/Store instructions
selectAddrDefault(SDValue Addr,SDValue & Base,SDValue & Offset) const362 bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
363                                            SDValue &Offset) const {
364   Base = Addr;
365   Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), Addr.getValueType());
366   return true;
367 }
368 
selectIntAddr(SDValue Addr,SDValue & Base,SDValue & Offset) const369 bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
370                                        SDValue &Offset) const {
371   return selectAddrRegImm(Addr, Base, Offset) ||
372     selectAddrDefault(Addr, Base, Offset);
373 }
374 
selectAddrRegImm9(SDValue Addr,SDValue & Base,SDValue & Offset) const375 bool MipsSEDAGToDAGISel::selectAddrRegImm9(SDValue Addr, SDValue &Base,
376                                            SDValue &Offset) const {
377   if (selectAddrFrameIndex(Addr, Base, Offset))
378     return true;
379 
380   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 9))
381     return true;
382 
383   return false;
384 }
385 
386 /// Used on microMIPS LWC2, LDC2, SWC2 and SDC2 instructions (11-bit offset)
selectAddrRegImm11(SDValue Addr,SDValue & Base,SDValue & Offset) const387 bool MipsSEDAGToDAGISel::selectAddrRegImm11(SDValue Addr, SDValue &Base,
388                                             SDValue &Offset) const {
389   if (selectAddrFrameIndex(Addr, Base, Offset))
390     return true;
391 
392   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 11))
393     return true;
394 
395   return false;
396 }
397 
398 /// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
selectAddrRegImm12(SDValue Addr,SDValue & Base,SDValue & Offset) const399 bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
400                                             SDValue &Offset) const {
401   if (selectAddrFrameIndex(Addr, Base, Offset))
402     return true;
403 
404   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12))
405     return true;
406 
407   return false;
408 }
409 
selectAddrRegImm16(SDValue Addr,SDValue & Base,SDValue & Offset) const410 bool MipsSEDAGToDAGISel::selectAddrRegImm16(SDValue Addr, SDValue &Base,
411                                             SDValue &Offset) const {
412   if (selectAddrFrameIndex(Addr, Base, Offset))
413     return true;
414 
415   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
416     return true;
417 
418   return false;
419 }
420 
selectIntAddr11MM(SDValue Addr,SDValue & Base,SDValue & Offset) const421 bool MipsSEDAGToDAGISel::selectIntAddr11MM(SDValue Addr, SDValue &Base,
422                                          SDValue &Offset) const {
423   return selectAddrRegImm11(Addr, Base, Offset) ||
424     selectAddrDefault(Addr, Base, Offset);
425 }
426 
selectIntAddr12MM(SDValue Addr,SDValue & Base,SDValue & Offset) const427 bool MipsSEDAGToDAGISel::selectIntAddr12MM(SDValue Addr, SDValue &Base,
428                                          SDValue &Offset) const {
429   return selectAddrRegImm12(Addr, Base, Offset) ||
430     selectAddrDefault(Addr, Base, Offset);
431 }
432 
selectIntAddr16MM(SDValue Addr,SDValue & Base,SDValue & Offset) const433 bool MipsSEDAGToDAGISel::selectIntAddr16MM(SDValue Addr, SDValue &Base,
434                                          SDValue &Offset) const {
435   return selectAddrRegImm16(Addr, Base, Offset) ||
436     selectAddrDefault(Addr, Base, Offset);
437 }
438 
selectIntAddrLSL2MM(SDValue Addr,SDValue & Base,SDValue & Offset) const439 bool MipsSEDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
440                                              SDValue &Offset) const {
441   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 7)) {
442     if (isa<FrameIndexSDNode>(Base))
443       return false;
444 
445     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Offset)) {
446       unsigned CnstOff = CN->getZExtValue();
447       return (CnstOff == (CnstOff & 0x3c));
448     }
449 
450     return false;
451   }
452 
453   // For all other cases where "lw" would be selected, don't select "lw16"
454   // because it would result in additional instructions to prepare operands.
455   if (selectAddrRegImm(Addr, Base, Offset))
456     return false;
457 
458   return selectAddrDefault(Addr, Base, Offset);
459 }
460 
selectIntAddrSImm10(SDValue Addr,SDValue & Base,SDValue & Offset) const461 bool MipsSEDAGToDAGISel::selectIntAddrSImm10(SDValue Addr, SDValue &Base,
462                                              SDValue &Offset) const {
463 
464   if (selectAddrFrameIndex(Addr, Base, Offset))
465     return true;
466 
467   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
468     return true;
469 
470   return selectAddrDefault(Addr, Base, Offset);
471 }
472 
selectIntAddrSImm10Lsl1(SDValue Addr,SDValue & Base,SDValue & Offset) const473 bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base,
474                                                  SDValue &Offset) const {
475   if (selectAddrFrameIndex(Addr, Base, Offset))
476     return true;
477 
478   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 1))
479     return true;
480 
481   return selectAddrDefault(Addr, Base, Offset);
482 }
483 
selectIntAddrSImm10Lsl2(SDValue Addr,SDValue & Base,SDValue & Offset) const484 bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base,
485                                                  SDValue &Offset) const {
486   if (selectAddrFrameIndex(Addr, Base, Offset))
487     return true;
488 
489   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 2))
490     return true;
491 
492   return selectAddrDefault(Addr, Base, Offset);
493 }
494 
selectIntAddrSImm10Lsl3(SDValue Addr,SDValue & Base,SDValue & Offset) const495 bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base,
496                                                  SDValue &Offset) const {
497   if (selectAddrFrameIndex(Addr, Base, Offset))
498     return true;
499 
500   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 3))
501     return true;
502 
503   return selectAddrDefault(Addr, Base, Offset);
504 }
505 
506 // Select constant vector splats.
507 //
508 // Returns true and sets Imm if:
509 // * MSA is enabled
510 // * N is a ISD::BUILD_VECTOR representing a constant splat
selectVSplat(SDNode * N,APInt & Imm,unsigned MinSizeInBits) const511 bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm,
512                                       unsigned MinSizeInBits) const {
513   if (!Subtarget->hasMSA())
514     return false;
515 
516   BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N);
517 
518   if (!Node)
519     return false;
520 
521   APInt SplatValue, SplatUndef;
522   unsigned SplatBitSize;
523   bool HasAnyUndefs;
524 
525   if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
526                              MinSizeInBits, !Subtarget->isLittle()))
527     return false;
528 
529   Imm = SplatValue;
530 
531   return true;
532 }
533 
534 // Select constant vector splats.
535 //
536 // In addition to the requirements of selectVSplat(), this function returns
537 // true and sets Imm if:
538 // * The splat value is the same width as the elements of the vector
539 // * The splat value fits in an integer with the specified signed-ness and
540 //   width.
541 //
542 // This function looks through ISD::BITCAST nodes.
543 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
544 //       sometimes a shuffle in big-endian mode.
545 //
546 // It's worth noting that this function is not used as part of the selection
547 // of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd]
548 // instruction to achieve the desired bit pattern. ldi.[bhwd] is selected in
549 // MipsSEDAGToDAGISel::selectNode.
550 bool MipsSEDAGToDAGISel::
selectVSplatCommon(SDValue N,SDValue & Imm,bool Signed,unsigned ImmBitSize) const551 selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
552                    unsigned ImmBitSize) const {
553   APInt ImmValue;
554   EVT EltTy = N->getValueType(0).getVectorElementType();
555 
556   if (N->getOpcode() == ISD::BITCAST)
557     N = N->getOperand(0);
558 
559   if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
560       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
561 
562     if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) ||
563         (!Signed && ImmValue.isIntN(ImmBitSize))) {
564       Imm = CurDAG->getTargetConstant(ImmValue, SDLoc(N), EltTy);
565       return true;
566     }
567   }
568 
569   return false;
570 }
571 
572 // Select constant vector splats.
573 bool MipsSEDAGToDAGISel::
selectVSplatUimm1(SDValue N,SDValue & Imm) const574 selectVSplatUimm1(SDValue N, SDValue &Imm) const {
575   return selectVSplatCommon(N, Imm, false, 1);
576 }
577 
578 bool MipsSEDAGToDAGISel::
selectVSplatUimm2(SDValue N,SDValue & Imm) const579 selectVSplatUimm2(SDValue N, SDValue &Imm) const {
580   return selectVSplatCommon(N, Imm, false, 2);
581 }
582 
583 bool MipsSEDAGToDAGISel::
selectVSplatUimm3(SDValue N,SDValue & Imm) const584 selectVSplatUimm3(SDValue N, SDValue &Imm) const {
585   return selectVSplatCommon(N, Imm, false, 3);
586 }
587 
588 // Select constant vector splats.
589 bool MipsSEDAGToDAGISel::
selectVSplatUimm4(SDValue N,SDValue & Imm) const590 selectVSplatUimm4(SDValue N, SDValue &Imm) const {
591   return selectVSplatCommon(N, Imm, false, 4);
592 }
593 
594 // Select constant vector splats.
595 bool MipsSEDAGToDAGISel::
selectVSplatUimm5(SDValue N,SDValue & Imm) const596 selectVSplatUimm5(SDValue N, SDValue &Imm) const {
597   return selectVSplatCommon(N, Imm, false, 5);
598 }
599 
600 // Select constant vector splats.
601 bool MipsSEDAGToDAGISel::
selectVSplatUimm6(SDValue N,SDValue & Imm) const602 selectVSplatUimm6(SDValue N, SDValue &Imm) const {
603   return selectVSplatCommon(N, Imm, false, 6);
604 }
605 
606 // Select constant vector splats.
607 bool MipsSEDAGToDAGISel::
selectVSplatUimm8(SDValue N,SDValue & Imm) const608 selectVSplatUimm8(SDValue N, SDValue &Imm) const {
609   return selectVSplatCommon(N, Imm, false, 8);
610 }
611 
612 // Select constant vector splats.
613 bool MipsSEDAGToDAGISel::
selectVSplatSimm5(SDValue N,SDValue & Imm) const614 selectVSplatSimm5(SDValue N, SDValue &Imm) const {
615   return selectVSplatCommon(N, Imm, true, 5);
616 }
617 
618 // Select constant vector splats whose value is a power of 2.
619 //
620 // In addition to the requirements of selectVSplat(), this function returns
621 // true and sets Imm if:
622 // * The splat value is the same width as the elements of the vector
623 // * The splat value is a power of two.
624 //
625 // This function looks through ISD::BITCAST nodes.
626 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
627 //       sometimes a shuffle in big-endian mode.
selectVSplatUimmPow2(SDValue N,SDValue & Imm) const628 bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
629   APInt ImmValue;
630   EVT EltTy = N->getValueType(0).getVectorElementType();
631 
632   if (N->getOpcode() == ISD::BITCAST)
633     N = N->getOperand(0);
634 
635   if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
636       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
637     int32_t Log2 = ImmValue.exactLogBase2();
638 
639     if (Log2 != -1) {
640       Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy);
641       return true;
642     }
643   }
644 
645   return false;
646 }
647 
648 // Select constant vector splats whose value only has a consecutive sequence
649 // of left-most bits set (e.g. 0b11...1100...00).
650 //
651 // In addition to the requirements of selectVSplat(), this function returns
652 // true and sets Imm if:
653 // * The splat value is the same width as the elements of the vector
654 // * The splat value is a consecutive sequence of left-most bits.
655 //
656 // This function looks through ISD::BITCAST nodes.
657 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
658 //       sometimes a shuffle in big-endian mode.
selectVSplatMaskL(SDValue N,SDValue & Imm) const659 bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
660   APInt ImmValue;
661   EVT EltTy = N->getValueType(0).getVectorElementType();
662 
663   if (N->getOpcode() == ISD::BITCAST)
664     N = N->getOperand(0);
665 
666   if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
667       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
668     // Extract the run of set bits starting with bit zero from the bitwise
669     // inverse of ImmValue, and test that the inverse of this is the same
670     // as the original value.
671     if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
672 
673       Imm = CurDAG->getTargetConstant(ImmValue.countPopulation() - 1, SDLoc(N),
674                                       EltTy);
675       return true;
676     }
677   }
678 
679   return false;
680 }
681 
682 // Select constant vector splats whose value only has a consecutive sequence
683 // of right-most bits set (e.g. 0b00...0011...11).
684 //
685 // In addition to the requirements of selectVSplat(), this function returns
686 // true and sets Imm if:
687 // * The splat value is the same width as the elements of the vector
688 // * The splat value is a consecutive sequence of right-most bits.
689 //
690 // This function looks through ISD::BITCAST nodes.
691 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
692 //       sometimes a shuffle in big-endian mode.
selectVSplatMaskR(SDValue N,SDValue & Imm) const693 bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
694   APInt ImmValue;
695   EVT EltTy = N->getValueType(0).getVectorElementType();
696 
697   if (N->getOpcode() == ISD::BITCAST)
698     N = N->getOperand(0);
699 
700   if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
701       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
702     // Extract the run of set bits starting with bit zero, and test that the
703     // result is the same as the original value
704     if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
705       Imm = CurDAG->getTargetConstant(ImmValue.countPopulation() - 1, SDLoc(N),
706                                       EltTy);
707       return true;
708     }
709   }
710 
711   return false;
712 }
713 
selectVSplatUimmInvPow2(SDValue N,SDValue & Imm) const714 bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N,
715                                                  SDValue &Imm) const {
716   APInt ImmValue;
717   EVT EltTy = N->getValueType(0).getVectorElementType();
718 
719   if (N->getOpcode() == ISD::BITCAST)
720     N = N->getOperand(0);
721 
722   if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
723       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
724     int32_t Log2 = (~ImmValue).exactLogBase2();
725 
726     if (Log2 != -1) {
727       Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy);
728       return true;
729     }
730   }
731 
732   return false;
733 }
734 
trySelect(SDNode * Node)735 bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
736   unsigned Opcode = Node->getOpcode();
737   SDLoc DL(Node);
738 
739   ///
740   // Instruction Selection not handled by the auto-generated
741   // tablegen selection should be handled here.
742   ///
743   switch(Opcode) {
744   default: break;
745 
746   case Mips::PseudoD_SELECT_I:
747   case Mips::PseudoD_SELECT_I64: {
748     MVT VT = Subtarget->isGP64bit() ? MVT::i64 : MVT::i32;
749     SDValue cond = Node->getOperand(0);
750     SDValue Hi1 = Node->getOperand(1);
751     SDValue Lo1 = Node->getOperand(2);
752     SDValue Hi2 = Node->getOperand(3);
753     SDValue Lo2 = Node->getOperand(4);
754 
755     SDValue ops[] = {cond, Hi1, Lo1, Hi2, Lo2};
756     EVT NodeTys[] = {VT, VT};
757     ReplaceNode(Node, CurDAG->getMachineNode(Subtarget->isGP64bit()
758                                                  ? Mips::PseudoD_SELECT_I64
759                                                  : Mips::PseudoD_SELECT_I,
760                                              DL, NodeTys, ops));
761     return true;
762   }
763 
764   case ISD::ADDE: {
765     selectAddE(Node, DL);
766     return true;
767   }
768 
769   case ISD::ConstantFP: {
770     auto *CN = cast<ConstantFPSDNode>(Node);
771     if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
772       if (Subtarget->isGP64bit()) {
773         SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
774                                               Mips::ZERO_64, MVT::i64);
775         ReplaceNode(Node,
776                     CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero));
777       } else if (Subtarget->isFP64bit()) {
778         SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
779                                               Mips::ZERO, MVT::i32);
780         ReplaceNode(Node, CurDAG->getMachineNode(Mips::BuildPairF64_64, DL,
781                                                  MVT::f64, Zero, Zero));
782       } else {
783         SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
784                                               Mips::ZERO, MVT::i32);
785         ReplaceNode(Node, CurDAG->getMachineNode(Mips::BuildPairF64, DL,
786                                                  MVT::f64, Zero, Zero));
787       }
788       return true;
789     }
790     break;
791   }
792 
793   case ISD::Constant: {
794     auto *CN = cast<ConstantSDNode>(Node);
795     int64_t Imm = CN->getSExtValue();
796     unsigned Size = CN->getValueSizeInBits(0);
797 
798     if (isInt<32>(Imm))
799       break;
800 
801     MipsAnalyzeImmediate AnalyzeImm;
802 
803     const MipsAnalyzeImmediate::InstSeq &Seq =
804       AnalyzeImm.Analyze(Imm, Size, false);
805 
806     MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
807     SDLoc DL(CN);
808     SDNode *RegOpnd;
809     SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
810                                                 DL, MVT::i64);
811 
812     // The first instruction can be a LUi which is different from other
813     // instructions (ADDiu, ORI and SLL) in that it does not have a register
814     // operand.
815     if (Inst->Opc == Mips::LUi64)
816       RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
817     else
818       RegOpnd =
819         CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
820                                CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
821                                ImmOpnd);
822 
823     // The remaining instructions in the sequence are handled here.
824     for (++Inst; Inst != Seq.end(); ++Inst) {
825       ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd), DL,
826                                           MVT::i64);
827       RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
828                                        SDValue(RegOpnd, 0), ImmOpnd);
829     }
830 
831     ReplaceNode(Node, RegOpnd);
832     return true;
833   }
834 
835   case ISD::INTRINSIC_W_CHAIN: {
836     const unsigned IntrinsicOpcode =
837         cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
838     switch (IntrinsicOpcode) {
839     default:
840       break;
841 
842     case Intrinsic::mips_cfcmsa: {
843       SDValue ChainIn = Node->getOperand(0);
844       SDValue RegIdx = Node->getOperand(2);
845       SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL,
846                                            getMSACtrlReg(RegIdx), MVT::i32);
847       ReplaceNode(Node, Reg.getNode());
848       return true;
849     }
850     case Intrinsic::mips_ldr_d:
851     case Intrinsic::mips_ldr_w: {
852       unsigned Op = (IntrinsicOpcode == Intrinsic::mips_ldr_d) ? Mips::LDR_D
853                                                                : Mips::LDR_W;
854 
855       SDLoc DL(Node);
856       assert(Node->getNumOperands() == 4 && "Unexpected number of operands.");
857       const SDValue &Chain = Node->getOperand(0);
858       const SDValue &Intrinsic = Node->getOperand(1);
859       const SDValue &Pointer = Node->getOperand(2);
860       const SDValue &Constant = Node->getOperand(3);
861 
862       assert(Chain.getValueType() == MVT::Other);
863       (void)Intrinsic;
864       assert(Intrinsic.getOpcode() == ISD::TargetConstant &&
865              Constant.getOpcode() == ISD::Constant &&
866              "Invalid instruction operand.");
867 
868       // Convert Constant to TargetConstant.
869       const ConstantInt *Val =
870           cast<ConstantSDNode>(Constant)->getConstantIntValue();
871       SDValue Imm =
872           CurDAG->getTargetConstant(*Val, DL, Constant.getValueType());
873 
874       SmallVector<SDValue, 3> Ops{Pointer, Imm, Chain};
875 
876       assert(Node->getNumValues() == 2);
877       assert(Node->getValueType(0).is128BitVector());
878       assert(Node->getValueType(1) == MVT::Other);
879       SmallVector<EVT, 2> ResTys{Node->getValueType(0), Node->getValueType(1)};
880 
881       ReplaceNode(Node, CurDAG->getMachineNode(Op, DL, ResTys, Ops));
882 
883       return true;
884     }
885     }
886     break;
887   }
888 
889   case ISD::INTRINSIC_WO_CHAIN: {
890     switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) {
891     default:
892       break;
893 
894     case Intrinsic::mips_move_v:
895       // Like an assignment but will always produce a move.v even if
896       // unnecessary.
897       ReplaceNode(Node, CurDAG->getMachineNode(Mips::MOVE_V, DL,
898                                                Node->getValueType(0),
899                                                Node->getOperand(1)));
900       return true;
901     }
902     break;
903   }
904 
905   case ISD::INTRINSIC_VOID: {
906     const unsigned IntrinsicOpcode =
907         cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
908     switch (IntrinsicOpcode) {
909     default:
910       break;
911 
912     case Intrinsic::mips_ctcmsa: {
913       SDValue ChainIn = Node->getOperand(0);
914       SDValue RegIdx  = Node->getOperand(2);
915       SDValue Value   = Node->getOperand(3);
916       SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL,
917                                               getMSACtrlReg(RegIdx), Value);
918       ReplaceNode(Node, ChainOut.getNode());
919       return true;
920     }
921     case Intrinsic::mips_str_d:
922     case Intrinsic::mips_str_w: {
923       unsigned Op = (IntrinsicOpcode == Intrinsic::mips_str_d) ? Mips::STR_D
924                                                                : Mips::STR_W;
925 
926       SDLoc DL(Node);
927       assert(Node->getNumOperands() == 5 && "Unexpected number of operands.");
928       const SDValue &Chain = Node->getOperand(0);
929       const SDValue &Intrinsic = Node->getOperand(1);
930       const SDValue &Vec = Node->getOperand(2);
931       const SDValue &Pointer = Node->getOperand(3);
932       const SDValue &Constant = Node->getOperand(4);
933 
934       assert(Chain.getValueType() == MVT::Other);
935       (void)Intrinsic;
936       assert(Intrinsic.getOpcode() == ISD::TargetConstant &&
937              Constant.getOpcode() == ISD::Constant &&
938              "Invalid instruction operand.");
939 
940       // Convert Constant to TargetConstant.
941       const ConstantInt *Val =
942           cast<ConstantSDNode>(Constant)->getConstantIntValue();
943       SDValue Imm =
944           CurDAG->getTargetConstant(*Val, DL, Constant.getValueType());
945 
946       SmallVector<SDValue, 4> Ops{Vec, Pointer, Imm, Chain};
947 
948       assert(Node->getNumValues() == 1);
949       assert(Node->getValueType(0) == MVT::Other);
950       SmallVector<EVT, 1> ResTys{Node->getValueType(0)};
951 
952       ReplaceNode(Node, CurDAG->getMachineNode(Op, DL, ResTys, Ops));
953       return true;
954     }
955     }
956     break;
957   }
958 
959   // Manually match MipsISD::Ins nodes to get the correct instruction. It has
960   // to be done in this fashion so that we respect the differences between
961   // dins and dinsm, as the difference is that the size operand has the range
962   // 0 < size <= 32 for dins while dinsm has the range 2 <= size <= 64 which
963   // means SelectionDAGISel would have to test all the operands at once to
964   // match the instruction.
965   case MipsISD::Ins: {
966 
967     // Sanity checking for the node operands.
968     if (Node->getValueType(0) != MVT::i32 && Node->getValueType(0) != MVT::i64)
969       return false;
970 
971     if (Node->getNumOperands() != 4)
972       return false;
973 
974     if (Node->getOperand(1)->getOpcode() != ISD::Constant ||
975         Node->getOperand(2)->getOpcode() != ISD::Constant)
976       return false;
977 
978     MVT ResTy = Node->getSimpleValueType(0);
979     uint64_t Pos = Node->getConstantOperandVal(1);
980     uint64_t Size = Node->getConstantOperandVal(2);
981 
982     // Size has to be >0 for 'ins', 'dins' and 'dinsu'.
983     if (!Size)
984       return false;
985 
986     if (Pos + Size > 64)
987       return false;
988 
989     if (ResTy != MVT::i32 && ResTy != MVT::i64)
990       return false;
991 
992     unsigned Opcode = 0;
993     if (ResTy == MVT::i32) {
994       if (Pos + Size <= 32)
995         Opcode = Mips::INS;
996     } else {
997       if (Pos + Size <= 32)
998         Opcode = Mips::DINS;
999       else if (Pos < 32 && 1 < Size)
1000         Opcode = Mips::DINSM;
1001       else
1002         Opcode = Mips::DINSU;
1003     }
1004 
1005     if (Opcode) {
1006       SDValue Ops[4] = {
1007           Node->getOperand(0), CurDAG->getTargetConstant(Pos, DL, MVT::i32),
1008           CurDAG->getTargetConstant(Size, DL, MVT::i32), Node->getOperand(3)};
1009 
1010       ReplaceNode(Node, CurDAG->getMachineNode(Opcode, DL, ResTy, Ops));
1011       return true;
1012     }
1013 
1014     return false;
1015   }
1016 
1017   case MipsISD::ThreadPointer: {
1018     EVT PtrVT = getTargetLowering()->getPointerTy(CurDAG->getDataLayout());
1019     unsigned RdhwrOpc, DestReg;
1020 
1021     if (PtrVT == MVT::i32) {
1022       RdhwrOpc = Mips::RDHWR;
1023       DestReg = Mips::V1;
1024     } else {
1025       RdhwrOpc = Mips::RDHWR64;
1026       DestReg = Mips::V1_64;
1027     }
1028 
1029     SDNode *Rdhwr =
1030         CurDAG->getMachineNode(RdhwrOpc, DL, Node->getValueType(0), MVT::Glue,
1031                                CurDAG->getRegister(Mips::HWR29, MVT::i32),
1032                                CurDAG->getTargetConstant(0, DL, MVT::i32));
1033     SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
1034                                          SDValue(Rdhwr, 0), SDValue(Rdhwr, 1));
1035     SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT,
1036                                              Chain.getValue(1));
1037     ReplaceNode(Node, ResNode.getNode());
1038     return true;
1039   }
1040 
1041   case ISD::BUILD_VECTOR: {
1042     // Select appropriate ldi.[bhwd] instructions for constant splats of
1043     // 128-bit when MSA is enabled. Fixup any register class mismatches that
1044     // occur as a result.
1045     //
1046     // This allows the compiler to use a wider range of immediates than would
1047     // otherwise be allowed. If, for example, v4i32 could only use ldi.h then
1048     // it would not be possible to load { 0x01010101, 0x01010101, 0x01010101,
1049     // 0x01010101 } without using a constant pool. This would be sub-optimal
1050     // when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the
1051     // same set/ of registers. Similarly, ldi.h isn't capable of producing {
1052     // 0x00000000, 0x00000001, 0x00000000, 0x00000001 } but 'ldi.d wd, 1' can.
1053 
1054     const MipsABIInfo &ABI =
1055         static_cast<const MipsTargetMachine &>(TM).getABI();
1056 
1057     BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Node);
1058     APInt SplatValue, SplatUndef;
1059     unsigned SplatBitSize;
1060     bool HasAnyUndefs;
1061     unsigned LdiOp;
1062     EVT ResVecTy = BVN->getValueType(0);
1063     EVT ViaVecTy;
1064 
1065     if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector())
1066       return false;
1067 
1068     if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
1069                               HasAnyUndefs, 8,
1070                               !Subtarget->isLittle()))
1071       return false;
1072 
1073     switch (SplatBitSize) {
1074     default:
1075       return false;
1076     case 8:
1077       LdiOp = Mips::LDI_B;
1078       ViaVecTy = MVT::v16i8;
1079       break;
1080     case 16:
1081       LdiOp = Mips::LDI_H;
1082       ViaVecTy = MVT::v8i16;
1083       break;
1084     case 32:
1085       LdiOp = Mips::LDI_W;
1086       ViaVecTy = MVT::v4i32;
1087       break;
1088     case 64:
1089       LdiOp = Mips::LDI_D;
1090       ViaVecTy = MVT::v2i64;
1091       break;
1092     }
1093 
1094     SDNode *Res = nullptr;
1095 
1096     // If we have a signed 10 bit integer, we can splat it directly.
1097     //
1098     // If we have something bigger we can synthesize the value into a GPR and
1099     // splat from there.
1100     if (SplatValue.isSignedIntN(10)) {
1101       SDValue Imm = CurDAG->getTargetConstant(SplatValue, DL,
1102                                               ViaVecTy.getVectorElementType());
1103 
1104       Res = CurDAG->getMachineNode(LdiOp, DL, ViaVecTy, Imm);
1105     } else if (SplatValue.isSignedIntN(16) &&
1106                ((ABI.IsO32() && SplatBitSize < 64) ||
1107                 (ABI.IsN32() || ABI.IsN64()))) {
1108       // Only handle signed 16 bit values when the element size is GPR width.
1109       // MIPS64 can handle all the cases but MIPS32 would need to handle
1110       // negative cases specifically here. Instead, handle those cases as
1111       // 64bit values.
1112 
1113       bool Is32BitSplat = ABI.IsO32() || SplatBitSize < 64;
1114       const unsigned ADDiuOp = Is32BitSplat ? Mips::ADDiu : Mips::DADDiu;
1115       const MVT SplatMVT = Is32BitSplat ? MVT::i32 : MVT::i64;
1116       SDValue ZeroVal = CurDAG->getRegister(
1117           Is32BitSplat ? Mips::ZERO : Mips::ZERO_64, SplatMVT);
1118 
1119       const unsigned FILLOp =
1120           SplatBitSize == 16
1121               ? Mips::FILL_H
1122               : (SplatBitSize == 32 ? Mips::FILL_W
1123                                     : (SplatBitSize == 64 ? Mips::FILL_D : 0));
1124 
1125       assert(FILLOp != 0 && "Unknown FILL Op for splat synthesis!");
1126       assert((!ABI.IsO32() || (FILLOp != Mips::FILL_D)) &&
1127              "Attempting to use fill.d on MIPS32!");
1128 
1129       const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1130       SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, SplatMVT);
1131 
1132       Res = CurDAG->getMachineNode(ADDiuOp, DL, SplatMVT, ZeroVal, LoVal);
1133       Res = CurDAG->getMachineNode(FILLOp, DL, ViaVecTy, SDValue(Res, 0));
1134 
1135     } else if (SplatValue.isSignedIntN(32) && SplatBitSize == 32) {
1136       // Only handle the cases where the splat size agrees with the size
1137       // of the SplatValue here.
1138       const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1139       const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1140       SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1141 
1142       SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1143       SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1144 
1145       if (Hi)
1146         Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1147 
1148       if (Lo)
1149         Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1150                                      Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
1151 
1152       assert((Hi || Lo) && "Zero case reached 32 bit case splat synthesis!");
1153       Res =
1154           CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32, SDValue(Res, 0));
1155 
1156     } else if (SplatValue.isSignedIntN(32) && SplatBitSize == 64 &&
1157                (ABI.IsN32() || ABI.IsN64())) {
1158       // N32 and N64 can perform some tricks that O32 can't for signed 32 bit
1159       // integers due to having 64bit registers. lui will cause the necessary
1160       // zero/sign extension.
1161       const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1162       const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1163       SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1164 
1165       SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1166       SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1167 
1168       if (Hi)
1169         Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1170 
1171       if (Lo)
1172         Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1173                                      Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
1174 
1175       Res = CurDAG->getMachineNode(
1176               Mips::SUBREG_TO_REG, DL, MVT::i64,
1177               CurDAG->getTargetConstant(((Hi >> 15) & 0x1), DL, MVT::i64),
1178               SDValue(Res, 0),
1179               CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1180 
1181       Res =
1182           CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64, SDValue(Res, 0));
1183 
1184     } else if (SplatValue.isSignedIntN(64)) {
1185       // If we have a 64 bit Splat value, we perform a similar sequence to the
1186       // above:
1187       //
1188       // MIPS32:                            MIPS64:
1189       //   lui $res, %highest(val)            lui $res, %highest(val)
1190       //   ori $res, $res, %higher(val)       ori $res, $res, %higher(val)
1191       //   lui $res2, %hi(val)                lui $res2, %hi(val)
1192       //   ori $res2, %res2, %lo(val)         ori $res2, %res2, %lo(val)
1193       //   $res3 = fill $res2                 dinsu $res, $res2, 0, 32
1194       //   $res4 = insert.w $res3[1], $res    fill.d $res
1195       //   splat.d $res4, 0
1196       //
1197       // The ability to use dinsu is guaranteed as MSA requires MIPSR5.
1198       // This saves having to materialize the value by shifts and ors.
1199       //
1200       // FIXME: Implement the preferred sequence for MIPS64R6:
1201       //
1202       // MIPS64R6:
1203       //   ori $res, $zero, %lo(val)
1204       //   daui $res, $res, %hi(val)
1205       //   dahi $res, $res, %higher(val)
1206       //   dati $res, $res, %highest(cal)
1207       //   fill.d $res
1208       //
1209 
1210       const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1211       const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1212       const unsigned Higher = SplatValue.lshr(32).getLoBits(16).getZExtValue();
1213       const unsigned Highest = SplatValue.lshr(48).getLoBits(16).getZExtValue();
1214 
1215       SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1216       SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1217       SDValue HigherVal = CurDAG->getTargetConstant(Higher, DL, MVT::i32);
1218       SDValue HighestVal = CurDAG->getTargetConstant(Highest, DL, MVT::i32);
1219       SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1220 
1221       // Independent of whether we're targeting MIPS64 or not, the basic
1222       // operations are the same. Also, directly use the $zero register if
1223       // the 16 bit chunk is zero.
1224       //
1225       // For optimization purposes we always synthesize the splat value as
1226       // an i32 value, then if we're targetting MIPS64, use SUBREG_TO_REG
1227       // just before combining the values with dinsu to produce an i64. This
1228       // enables SelectionDAG to aggressively share components of splat values
1229       // where possible.
1230       //
1231       // FIXME: This is the general constant synthesis problem. This code
1232       //        should be factored out into a class shared between all the
1233       //        classes that need it. Specifically, for a splat size of 64
1234       //        bits that's a negative number we can do better than LUi/ORi
1235       //        for the upper 32bits.
1236 
1237       if (Hi)
1238         Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1239 
1240       if (Lo)
1241         Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1242                                      Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
1243 
1244       SDNode *HiRes;
1245       if (Highest)
1246         HiRes = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HighestVal);
1247 
1248       if (Higher)
1249         HiRes = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1250                                        Highest ? SDValue(HiRes, 0) : ZeroVal,
1251                                        HigherVal);
1252 
1253 
1254       if (ABI.IsO32()) {
1255         Res = CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32,
1256                                      (Hi || Lo) ? SDValue(Res, 0) : ZeroVal);
1257 
1258         Res = CurDAG->getMachineNode(
1259             Mips::INSERT_W, DL, MVT::v4i32, SDValue(Res, 0),
1260             (Highest || Higher) ? SDValue(HiRes, 0) : ZeroVal,
1261             CurDAG->getTargetConstant(1, DL, MVT::i32));
1262 
1263         const TargetLowering *TLI = getTargetLowering();
1264         const TargetRegisterClass *RC =
1265             TLI->getRegClassFor(ViaVecTy.getSimpleVT());
1266 
1267         Res = CurDAG->getMachineNode(
1268             Mips::COPY_TO_REGCLASS, DL, ViaVecTy, SDValue(Res, 0),
1269             CurDAG->getTargetConstant(RC->getID(), DL, MVT::i32));
1270 
1271         Res = CurDAG->getMachineNode(
1272             Mips::SPLATI_D, DL, MVT::v2i64, SDValue(Res, 0),
1273             CurDAG->getTargetConstant(0, DL, MVT::i32));
1274       } else if (ABI.IsN64() || ABI.IsN32()) {
1275 
1276         SDValue Zero64Val = CurDAG->getRegister(Mips::ZERO_64, MVT::i64);
1277         const bool HiResNonZero = Highest || Higher;
1278         const bool ResNonZero = Hi || Lo;
1279 
1280         if (HiResNonZero)
1281           HiRes = CurDAG->getMachineNode(
1282               Mips::SUBREG_TO_REG, DL, MVT::i64,
1283               CurDAG->getTargetConstant(((Highest >> 15) & 0x1), DL, MVT::i64),
1284               SDValue(HiRes, 0),
1285               CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1286 
1287         if (ResNonZero)
1288           Res = CurDAG->getMachineNode(
1289               Mips::SUBREG_TO_REG, DL, MVT::i64,
1290               CurDAG->getTargetConstant(((Hi >> 15) & 0x1), DL, MVT::i64),
1291               SDValue(Res, 0),
1292               CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1293 
1294         // We have 3 cases:
1295         //   The HiRes is nonzero but Res is $zero  => dsll32 HiRes, 0
1296         //   The Res is nonzero but HiRes is $zero  => dinsu Res, $zero, 32, 32
1297         //   Both are non zero                      => dinsu Res, HiRes, 32, 32
1298         //
1299         // The obvious "missing" case is when both are zero, but that case is
1300         // handled by the ldi case.
1301         if (ResNonZero) {
1302           IntegerType *Int32Ty =
1303               IntegerType::get(MF->getFunction().getContext(), 32);
1304           const ConstantInt *Const32 = ConstantInt::get(Int32Ty, 32);
1305           SDValue Ops[4] = {HiResNonZero ? SDValue(HiRes, 0) : Zero64Val,
1306                             CurDAG->getConstant(*Const32, DL, MVT::i32),
1307                             CurDAG->getConstant(*Const32, DL, MVT::i32),
1308                             SDValue(Res, 0)};
1309 
1310           Res = CurDAG->getMachineNode(Mips::DINSU, DL, MVT::i64, Ops);
1311         } else if (HiResNonZero) {
1312           Res = CurDAG->getMachineNode(
1313               Mips::DSLL32, DL, MVT::i64, SDValue(HiRes, 0),
1314               CurDAG->getTargetConstant(0, DL, MVT::i32));
1315         } else
1316           llvm_unreachable(
1317               "Zero splat value handled by non-zero 64bit splat synthesis!");
1318 
1319         Res = CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64,
1320                                      SDValue(Res, 0));
1321       } else
1322         llvm_unreachable("Unknown ABI in MipsISelDAGToDAG!");
1323 
1324     } else
1325       return false;
1326 
1327     if (ResVecTy != ViaVecTy) {
1328       // If LdiOp is writing to a different register class to ResVecTy, then
1329       // fix it up here. This COPY_TO_REGCLASS should never cause a move.v
1330       // since the source and destination register sets contain the same
1331       // registers.
1332       const TargetLowering *TLI = getTargetLowering();
1333       MVT ResVecTySimple = ResVecTy.getSimpleVT();
1334       const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
1335       Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, DL,
1336                                    ResVecTy, SDValue(Res, 0),
1337                                    CurDAG->getTargetConstant(RC->getID(), DL,
1338                                                              MVT::i32));
1339     }
1340 
1341     ReplaceNode(Node, Res);
1342     return true;
1343   }
1344 
1345   }
1346 
1347   return false;
1348 }
1349 
1350 bool MipsSEDAGToDAGISel::
SelectInlineAsmMemoryOperand(const SDValue & Op,unsigned ConstraintID,std::vector<SDValue> & OutOps)1351 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
1352                              std::vector<SDValue> &OutOps) {
1353   SDValue Base, Offset;
1354 
1355   switch(ConstraintID) {
1356   default:
1357     llvm_unreachable("Unexpected asm memory constraint");
1358   // All memory constraints can at least accept raw pointers.
1359   case InlineAsm::Constraint_m:
1360   case InlineAsm::Constraint_o:
1361     if (selectAddrRegImm16(Op, Base, Offset)) {
1362       OutOps.push_back(Base);
1363       OutOps.push_back(Offset);
1364       return false;
1365     }
1366     OutOps.push_back(Op);
1367     OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1368     return false;
1369   case InlineAsm::Constraint_R:
1370     // The 'R' constraint is supposed to be much more complicated than this.
1371     // However, it's becoming less useful due to architectural changes and
1372     // ought to be replaced by other constraints such as 'ZC'.
1373     // For now, support 9-bit signed offsets which is supportable by all
1374     // subtargets for all instructions.
1375     if (selectAddrRegImm9(Op, Base, Offset)) {
1376       OutOps.push_back(Base);
1377       OutOps.push_back(Offset);
1378       return false;
1379     }
1380     OutOps.push_back(Op);
1381     OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1382     return false;
1383   case InlineAsm::Constraint_ZC:
1384     // ZC matches whatever the pref, ll, and sc instructions can handle for the
1385     // given subtarget.
1386     if (Subtarget->inMicroMipsMode()) {
1387       // On microMIPS, they can handle 12-bit offsets.
1388       if (selectAddrRegImm12(Op, Base, Offset)) {
1389         OutOps.push_back(Base);
1390         OutOps.push_back(Offset);
1391         return false;
1392       }
1393     } else if (Subtarget->hasMips32r6()) {
1394       // On MIPS32r6/MIPS64r6, they can only handle 9-bit offsets.
1395       if (selectAddrRegImm9(Op, Base, Offset)) {
1396         OutOps.push_back(Base);
1397         OutOps.push_back(Offset);
1398         return false;
1399       }
1400     } else if (selectAddrRegImm16(Op, Base, Offset)) {
1401       // Prior to MIPS32r6/MIPS64r6, they can handle 16-bit offsets.
1402       OutOps.push_back(Base);
1403       OutOps.push_back(Offset);
1404       return false;
1405     }
1406     // In all cases, 0-bit offsets are acceptable.
1407     OutOps.push_back(Op);
1408     OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1409     return false;
1410   }
1411   return true;
1412 }
1413 
createMipsSEISelDag(MipsTargetMachine & TM,CodeGenOpt::Level OptLevel)1414 FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM,
1415                                         CodeGenOpt::Level OptLevel) {
1416   return new MipsSEDAGToDAGISel(TM, OptLevel);
1417 }
1418