1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3#
4# Verify folding operations into G_ICMP.
5#
6# E.g cmn/adds folding:
7#
8# x = G_SUB 0, y
9# G_ICMP intpred(something_safe) z, x
10#
11# Folds to:
12# adds z, y
13#
14# Where "something_safe" is ne or eq.
15#
16# ands/tst folding:
17#
18# z = G_AND x, y
19# G_ICMP z, 0
20#
21# Folds to:
22#
23# tst x, y
24#
25# When we have signed comparisons.
26#
27# Tests whose names start with cmn_ should use ADDS for the G_ICMP. Tests whose
28# names start with no_cmn should use SUBS. Similarly, tests whose names start
29# with TST should use ANDS for the G_ICMP.
30#
31
32...
33---
34name:            cmn_s32_rhs
35alignment:       4
36legalized:       true
37regBankSelected: true
38tracksRegLiveness: true
39body:             |
40  bb.0:
41    liveins: $w0, $w1
42
43    ; CHECK-LABEL: name: cmn_s32_rhs
44    ; CHECK: liveins: $w0, $w1
45    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
46    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
47    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
48    ; CHECK: [[ADDSWrr:%[0-9]+]]:gpr32 = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
49    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 0, implicit $nzcv
50    ; CHECK: $w0 = COPY [[CSINCWr]]
51    ; CHECK: RET_ReallyLR implicit $w0
52    %0:gpr(s32) = COPY $w0
53    %1:gpr(s32) = COPY $w1
54    %2:gpr(s32) = G_CONSTANT i32 0
55    %6:gpr(s32) = G_CONSTANT i32 1
56    %3:gpr(s32) = G_SUB %2, %1
57    %7:gpr(s32) = G_ICMP intpred(ne), %0(s32), %3
58    %4:gpr(s1) = G_TRUNC %7(s32)
59    %5:gpr(s32) = G_SELECT %4(s1), %6, %2
60    $w0 = COPY %5(s32)
61    RET_ReallyLR implicit $w0
62
63...
64---
65name:            cmn_s32_lhs
66alignment:       4
67legalized:       true
68regBankSelected: true
69tracksRegLiveness: true
70body:             |
71  bb.0:
72    liveins: $w0, $w1
73
74    ; CHECK-LABEL: name: cmn_s32_lhs
75    ; CHECK: liveins: $w0, $w1
76    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
77    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
78    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
79    ; CHECK: [[ADDSWrr:%[0-9]+]]:gpr32 = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
80    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 0, implicit $nzcv
81    ; CHECK: $w0 = COPY [[CSINCWr]]
82    ; CHECK: RET_ReallyLR implicit $w0
83    %0:gpr(s32) = COPY $w0
84    %1:gpr(s32) = COPY $w1
85    %2:gpr(s32) = G_CONSTANT i32 0
86    %6:gpr(s32) = G_CONSTANT i32 1
87    %3:gpr(s32) = G_SUB %2, %0
88    %7:gpr(s32) = G_ICMP intpred(ne), %3(s32), %1
89    %4:gpr(s1) = G_TRUNC %7(s32)
90    %5:gpr(s32) = G_SELECT %4(s1), %6, %2
91    $w0 = COPY %5(s32)
92    RET_ReallyLR implicit $w0
93
94...
95---
96name:            no_cmn_s32_rhs
97alignment:       4
98legalized:       true
99regBankSelected: true
100tracksRegLiveness: true
101body:             |
102  bb.0:
103    liveins: $w0, $w1
104
105    ; CHECK-LABEL: name: no_cmn_s32_rhs
106    ; CHECK: liveins: $w0, $w1
107    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
108    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
109    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
110    ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY2]], [[COPY1]], implicit-def $nzcv
111    ; CHECK: [[SUBSWrr1:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[SUBSWrr]], implicit-def $nzcv
112    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 10, implicit $nzcv
113    ; CHECK: $w0 = COPY [[CSINCWr]]
114    ; CHECK: RET_ReallyLR implicit $w0
115    %0:gpr(s32) = COPY $w0
116    %1:gpr(s32) = COPY $w1
117    %2:gpr(s32) = G_CONSTANT i32 0
118    %6:gpr(s32) = G_CONSTANT i32 1
119    %3:gpr(s32) = G_SUB %2, %1
120    %7:gpr(s32) = G_ICMP intpred(slt), %0(s32), %3
121    %4:gpr(s1) = G_TRUNC %7(s32)
122    %5:gpr(s32) = G_SELECT %4(s1), %6, %2
123    $w0 = COPY %5(s32)
124    RET_ReallyLR implicit $w0
125
126...
127---
128name:            no_cmn_s32_lhs
129alignment:       4
130legalized:       true
131regBankSelected: true
132tracksRegLiveness: true
133body:             |
134  bb.0:
135    liveins: $w0, $w1
136
137    ; CHECK-LABEL: name: no_cmn_s32_lhs
138    ; CHECK: liveins: $w0, $w1
139    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
140    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
141    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
142    ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY2]], [[COPY]], implicit-def $nzcv
143    ; CHECK: [[SUBSWrr1:%[0-9]+]]:gpr32 = SUBSWrr [[SUBSWrr]], [[COPY1]], implicit-def $nzcv
144    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 10, implicit $nzcv
145    ; CHECK: $w0 = COPY [[CSINCWr]]
146    ; CHECK: RET_ReallyLR implicit $w0
147    %0:gpr(s32) = COPY $w0
148    %1:gpr(s32) = COPY $w1
149    %2:gpr(s32) = G_CONSTANT i32 0
150    %6:gpr(s32) = G_CONSTANT i32 1
151    %3:gpr(s32) = G_SUB %2, %0
152    %7:gpr(s32) = G_ICMP intpred(slt), %3(s32), %1
153    %4:gpr(s1) = G_TRUNC %7(s32)
154    %5:gpr(s32) = G_SELECT %4(s1), %6, %2
155    $w0 = COPY %5(s32)
156    RET_ReallyLR implicit $w0
157
158...
159---
160name:            cmn_s64_rhs
161alignment:       4
162legalized:       true
163regBankSelected: true
164tracksRegLiveness: true
165body:             |
166  bb.0:
167    liveins: $x0, $x1
168
169    ; CHECK-LABEL: name: cmn_s64_rhs
170    ; CHECK: liveins: $x0, $x1
171    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
172    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
173    ; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr
174    ; CHECK: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
175    ; CHECK: [[CSINCXr:%[0-9]+]]:gpr64 = CSINCXr [[COPY2]], $xzr, 0, implicit $nzcv
176    ; CHECK: $x0 = COPY [[CSINCXr]]
177    ; CHECK: RET_ReallyLR implicit $x0
178    %0:gpr(s64) = COPY $x0
179    %1:gpr(s64) = COPY $x1
180    %2:gpr(s64) = G_CONSTANT i64 0
181    %6:gpr(s64) = G_CONSTANT i64 1
182    %3:gpr(s64) = G_SUB %2, %1
183    %7:gpr(s32) = G_ICMP intpred(ne), %0(s64), %3
184    %4:gpr(s1) = G_TRUNC %7(s32)
185    %5:gpr(s64) = G_SELECT %4(s1), %6, %2
186    $x0 = COPY %5(s64)
187    RET_ReallyLR implicit $x0
188
189...
190---
191name:            cmn_s64_lhs
192alignment:       4
193legalized:       true
194regBankSelected: true
195tracksRegLiveness: true
196body:             |
197  bb.0:
198    liveins: $x0, $x1
199
200    ; CHECK-LABEL: name: cmn_s64_lhs
201    ; CHECK: liveins: $x0, $x1
202    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
203    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
204    ; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr
205    ; CHECK: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
206    ; CHECK: [[CSINCXr:%[0-9]+]]:gpr64 = CSINCXr [[COPY2]], $xzr, 0, implicit $nzcv
207    ; CHECK: $x0 = COPY [[CSINCXr]]
208    ; CHECK: RET_ReallyLR implicit $x0
209    %0:gpr(s64) = COPY $x0
210    %1:gpr(s64) = COPY $x1
211    %2:gpr(s64) = G_CONSTANT i64 0
212    %6:gpr(s64) = G_CONSTANT i64 1
213    %3:gpr(s64) = G_SUB %2, %0
214    %7:gpr(s32) = G_ICMP intpred(ne), %3(s64), %1
215    %4:gpr(s1) = G_TRUNC %7(s32)
216    %5:gpr(s64) = G_SELECT %4(s1), %6, %2
217    $x0 = COPY %5(s64)
218    RET_ReallyLR implicit $x0
219
220...
221---
222name:            no_cmn_s64_rhs
223alignment:       4
224legalized:       true
225regBankSelected: true
226tracksRegLiveness: true
227body:             |
228  bb.0:
229    liveins: $x0, $x1
230
231    ; CHECK-LABEL: name: no_cmn_s64_rhs
232    ; CHECK: liveins: $x0, $x1
233    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
234    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
235    ; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr
236    ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY2]], [[COPY1]], implicit-def $nzcv
237    ; CHECK: [[SUBSXrr1:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[SUBSXrr]], implicit-def $nzcv
238    ; CHECK: [[CSINCXr:%[0-9]+]]:gpr64 = CSINCXr [[COPY2]], $xzr, 10, implicit $nzcv
239    ; CHECK: $x0 = COPY [[CSINCXr]]
240    ; CHECK: RET_ReallyLR implicit $x0
241    %0:gpr(s64) = COPY $x0
242    %1:gpr(s64) = COPY $x1
243    %2:gpr(s64) = G_CONSTANT i64 0
244    %6:gpr(s64) = G_CONSTANT i64 1
245    %3:gpr(s64) = G_SUB %2, %1
246    %7:gpr(s32) = G_ICMP intpred(slt), %0(s64), %3
247    %4:gpr(s1) = G_TRUNC %7(s32)
248    %5:gpr(s64) = G_SELECT %4(s1), %6, %2
249    $x0 = COPY %5(s64)
250    RET_ReallyLR implicit $x0
251
252...
253---
254name:            no_cmn_s64_lhs
255alignment:       4
256legalized:       true
257regBankSelected: true
258tracksRegLiveness: true
259body:             |
260  bb.0:
261    liveins: $x0, $x1
262
263    ; CHECK-LABEL: name: no_cmn_s64_lhs
264    ; CHECK: liveins: $x0, $x1
265    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
266    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
267    ; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr
268    ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY2]], [[COPY]], implicit-def $nzcv
269    ; CHECK: [[SUBSXrr1:%[0-9]+]]:gpr64 = SUBSXrr [[SUBSXrr]], [[COPY1]], implicit-def $nzcv
270    ; CHECK: [[CSINCXr:%[0-9]+]]:gpr64 = CSINCXr [[COPY2]], $xzr, 10, implicit $nzcv
271    ; CHECK: $x0 = COPY [[CSINCXr]]
272    ; CHECK: RET_ReallyLR implicit $x0
273    %0:gpr(s64) = COPY $x0
274    %1:gpr(s64) = COPY $x1
275    %2:gpr(s64) = G_CONSTANT i64 0
276    %6:gpr(s64) = G_CONSTANT i64 1
277    %3:gpr(s64) = G_SUB %2, %0
278    %7:gpr(s32) = G_ICMP intpred(slt), %3(s64), %1
279    %4:gpr(s1) = G_TRUNC %7(s32)
280    %5:gpr(s64) = G_SELECT %4(s1), %6, %2
281    $x0 = COPY %5(s64)
282    RET_ReallyLR implicit $x0
283
284...
285---
286name:            tst_s32
287alignment:       4
288legalized:       true
289regBankSelected: true
290tracksRegLiveness: true
291body:             |
292  bb.0:
293    liveins: $w0, $w1
294    ; CHECK-LABEL: name: tst_s32
295    ; CHECK: liveins: $w0, $w1
296    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
297    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr
298    ; CHECK: [[ANDSWrr:%[0-9]+]]:gpr32 = ANDSWrr [[COPY1]], [[COPY]], implicit-def $nzcv
299    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY1]], $wzr, 1, implicit $nzcv
300    ; CHECK: $w0 = COPY [[CSINCWr]]
301    ; CHECK: RET_ReallyLR implicit $w0
302    %0:gpr(s32) = COPY $w0
303    %1:gpr(s32) = COPY $w1
304    %2:gpr(s32) = G_CONSTANT i32 0
305    %6:gpr(s32) = G_CONSTANT i32 1
306    %3:gpr(s32) = G_AND %2, %1
307    %8:gpr(s32) = G_CONSTANT i32 0
308    %7:gpr(s32) = G_ICMP intpred(eq), %3(s32), %8
309    %4:gpr(s1) = G_TRUNC %7(s32)
310    %5:gpr(s32) = G_SELECT %4(s1), %6, %2
311    $w0 = COPY %5(s32)
312    RET_ReallyLR implicit $w0
313
314...
315---
316name:            tst_s64
317alignment:       4
318legalized:       true
319regBankSelected: true
320tracksRegLiveness: true
321body:             |
322  bb.0:
323    liveins: $x0, $x1
324    ; CHECK-LABEL: name: tst_s64
325    ; CHECK: liveins: $x0, $x1
326    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
327    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $xzr
328    ; CHECK: [[ANDSXrr:%[0-9]+]]:gpr64 = ANDSXrr [[COPY1]], [[COPY]], implicit-def $nzcv
329    ; CHECK: [[CSINCXr:%[0-9]+]]:gpr64 = CSINCXr [[COPY1]], $xzr, 1, implicit $nzcv
330    ; CHECK: $x0 = COPY [[CSINCXr]]
331    ; CHECK: RET_ReallyLR implicit $x0
332    %0:gpr(s64) = COPY $x0
333    %1:gpr(s64) = COPY $x1
334    %2:gpr(s64) = G_CONSTANT i64 0
335    %6:gpr(s64) = G_CONSTANT i64 1
336    %3:gpr(s64) = G_AND %2, %1
337    %8:gpr(s64) = G_CONSTANT i64 0
338    %7:gpr(s32) = G_ICMP intpred(eq), %3(s64), %8
339    %4:gpr(s1) = G_TRUNC %7(s32)
340    %5:gpr(s64) = G_SELECT %4(s1), %6, %2
341    $x0 = COPY %5(s64)
342    RET_ReallyLR implicit $x0
343
344...
345---
346name:            no_tst_unsigned_compare
347alignment:       4
348legalized:       true
349regBankSelected: true
350tracksRegLiveness: true
351body:             |
352  bb.0:
353    liveins: $w0, $w1
354    ; CHECK-LABEL: name: no_tst_unsigned_compare
355    ; CHECK: liveins: $w0, $w1
356    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
357    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr
358    ; CHECK: [[ANDWrr:%[0-9]+]]:gpr32common = ANDWrr [[COPY1]], [[COPY]]
359    ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[ANDWrr]], 0, 0, implicit-def $nzcv
360    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY1]], $wzr, 9, implicit $nzcv
361    ; CHECK: $w0 = COPY [[CSINCWr]]
362    ; CHECK: RET_ReallyLR implicit $w0
363    %0:gpr(s32) = COPY $w0
364    %1:gpr(s32) = COPY $w1
365    %2:gpr(s32) = G_CONSTANT i32 0
366    %6:gpr(s32) = G_CONSTANT i32 1
367    %3:gpr(s32) = G_AND %2, %1
368    %8:gpr(s32) = G_CONSTANT i32 0
369    %7:gpr(s32) = G_ICMP intpred(ugt), %3(s32), %8
370    %4:gpr(s1) = G_TRUNC %7(s32)
371    %5:gpr(s32) = G_SELECT %4(s1), %6, %2
372    $w0 = COPY %5(s32)
373    RET_ReallyLR implicit $w0
374
375...
376---
377name:            no_tst_nonzero
378alignment:       4
379legalized:       true
380regBankSelected: true
381tracksRegLiveness: true
382body:             |
383  bb.0:
384    liveins: $w0, $w1
385    ; CHECK-LABEL: name: no_tst_nonzero
386    ; CHECK: liveins: $w0, $w1
387    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
388    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr
389    ; CHECK: [[ANDWrr:%[0-9]+]]:gpr32common = ANDWrr [[COPY1]], [[COPY]]
390    ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[ANDWrr]], 42, 0, implicit-def $nzcv
391    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY1]], $wzr, 9, implicit $nzcv
392    ; CHECK: $w0 = COPY [[CSINCWr]]
393    ; CHECK: RET_ReallyLR implicit $w0
394    %0:gpr(s32) = COPY $w0
395    %1:gpr(s32) = COPY $w1
396    %2:gpr(s32) = G_CONSTANT i32 0
397    %6:gpr(s32) = G_CONSTANT i32 1
398    %3:gpr(s32) = G_AND %2, %1
399    %8:gpr(s32) = G_CONSTANT i32 42
400    %7:gpr(s32) = G_ICMP intpred(ugt), %3(s32), %8
401    %4:gpr(s1) = G_TRUNC %7(s32)
402    %5:gpr(s32) = G_SELECT %4(s1), %6, %2
403    $w0 = COPY %5(s32)
404    RET_ReallyLR implicit $w0
405
406...
407---
408name:            imm_tst
409alignment:       4
410legalized:       true
411regBankSelected: true
412tracksRegLiveness: true
413body:             |
414  bb.0:
415    liveins: $w0, $w1
416    ; CHECK-LABEL: name: imm_tst
417    ; CHECK: liveins: $w0, $w1
418    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
419    ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 1, implicit-def $nzcv
420    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
421    ; CHECK: $w0 = COPY [[CSINCWr]]
422    ; CHECK: RET_ReallyLR implicit $w0
423    %0:gpr(s32) = COPY $w0
424    %1:gpr(s32) = COPY $w1
425    %2:gpr(s32) = G_CONSTANT i32 0
426    %3:gpr(s32) = G_CONSTANT i32 1
427
428    ; This can be represented as a logical immediate, so we can pull it into
429    ; the ANDS. We should get ANDSWri.
430    %4:gpr(s32) = G_CONSTANT i32 3
431
432    %5:gpr(s32) = G_AND %1, %4
433    %6:gpr(s32) = G_ICMP intpred(eq), %5(s32), %2
434    $w0 = COPY %6(s32)
435    RET_ReallyLR implicit $w0
436
437
438...
439---
440name:            no_imm_tst_not_logical_imm
441alignment:       4
442legalized:       true
443regBankSelected: true
444tracksRegLiveness: true
445body:             |
446  bb.0:
447    liveins: $w0, $w1
448    ; CHECK-LABEL: name: no_imm_tst_not_logical_imm
449    ; CHECK: liveins: $w0, $w1
450    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
451    ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm -1
452    ; CHECK: [[ANDSWrr:%[0-9]+]]:gpr32 = ANDSWrr [[COPY]], [[MOVi32imm]], implicit-def $nzcv
453    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
454    ; CHECK: $w0 = COPY [[CSINCWr]]
455    ; CHECK: RET_ReallyLR implicit $w0
456    %0:gpr(s32) = COPY $w0
457    %1:gpr(s32) = COPY $w1
458    %2:gpr(s32) = G_CONSTANT i32 0
459    %3:gpr(s32) = G_CONSTANT i32 1
460
461    ; This immediate can't be represented as a logical immediate. We shouldn't
462    ; select ANDSWri.
463    %4:gpr(s32) = G_CONSTANT i32 -1
464
465    %5:gpr(s32) = G_AND %1, %4
466    %6:gpr(s32) = G_ICMP intpred(eq), %5(s32), %2
467    $w0 = COPY %6(s32)
468    RET_ReallyLR implicit $w0
469
470...
471---
472name:            test_physreg_copy
473alignment:       4
474legalized:       true
475regBankSelected: true
476tracksRegLiveness: true
477body:             |
478  bb.0:
479    liveins: $x0, $x1
480    ; CHECK-LABEL: name: test_physreg_copy
481    ; CHECK: liveins: $x0, $x1
482    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
483    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
484    ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
485    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
486    ; CHECK: $w0 = COPY [[CSINCWr]]
487    ; CHECK: RET_ReallyLR implicit $x0
488    %0:gpr(s64) = COPY $x0
489    %1:gpr(s64) = COPY $x1
490    ; When we find the defs of the LHS and RHS of the compare, we walk over
491    ; copies. Make sure that we don't crash when we hit a copy from a physical
492    ; register.
493    %7:gpr(s32) = G_ICMP intpred(eq), %0, %1
494    $w0 = COPY %7(s32)
495    RET_ReallyLR implicit $x0
496
497...
498---
499name:            tst_fold_shift_s64
500alignment:       4
501legalized:       true
502regBankSelected: true
503tracksRegLiveness: true
504body:             |
505  bb.0:
506    liveins: $x0, $x1
507    ; We should fold the G_SHL into the ANDS to get ANDSXrs.
508    ;
509    ; CHECK-LABEL: name: tst_fold_shift_s64
510    ; CHECK: liveins: $x0, $x1
511    ; CHECK: %copy:gpr64 = COPY $x1
512    ; CHECK: %zero:gpr64 = COPY $xzr
513    ; CHECK: [[ANDSXrs:%[0-9]+]]:gpr64 = ANDSXrs %zero, %copy, 16, implicit-def $nzcv
514    ; CHECK: %select:gpr64 = CSINCXr %zero, $xzr, 1, implicit $nzcv
515    ; CHECK: $x0 = COPY %select
516    ; CHECK: RET_ReallyLR implicit $x0
517    %copy:gpr(s64) = COPY $x1
518    %zero:gpr(s64) = G_CONSTANT i64 0
519    %one:gpr(s64) = G_CONSTANT i64 1
520    %cst:gpr(s64) = G_CONSTANT i64 16
521    %shift:gpr(s64) = G_SHL %copy(s64), %cst(s64)
522    %and:gpr(s64) = G_AND %zero, %shift
523    %cmp:gpr(s32) = G_ICMP intpred(eq), %and(s64), %zero
524    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
525    %select:gpr(s64) = G_SELECT %cmp_trunc(s1), %one, %zero
526    $x0 = COPY %select(s64)
527    RET_ReallyLR implicit $x0
528
529...
530---
531name:            tst_fold_shift_s32
532alignment:       4
533legalized:       true
534regBankSelected: true
535tracksRegLiveness: true
536body:             |
537  bb.0:
538    liveins: $w0, $w1
539    ; We should fold the G_SHL into the ANDS to get ANDSWrs.
540    ;
541    ; CHECK-LABEL: name: tst_fold_shift_s32
542    ; CHECK: liveins: $w0, $w1
543    ; CHECK: %copy:gpr32 = COPY $w1
544    ; CHECK: %zero:gpr32 = COPY $wzr
545    ; CHECK: [[ANDSWrs:%[0-9]+]]:gpr32 = ANDSWrs %zero, %copy, 16, implicit-def $nzcv
546    ; CHECK: %select:gpr32 = CSINCWr %zero, $wzr, 1, implicit $nzcv
547    ; CHECK: $w0 = COPY %select
548    ; CHECK: RET_ReallyLR implicit $w0
549    %copy:gpr(s32) = COPY $w1
550    %zero:gpr(s32) = G_CONSTANT i32 0
551    %one:gpr(s32) = G_CONSTANT i32 1
552    %cst:gpr(s32) = G_CONSTANT i32 16
553    %shift:gpr(s32) = G_SHL %copy(s32), %cst(s32)
554    %and:gpr(s32) = G_AND %zero, %shift
555    %cmp:gpr(s32) = G_ICMP intpred(eq), %and(s32), %zero
556    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
557    %select:gpr(s32) = G_SELECT %cmp_trunc(s1), %one, %zero
558    $w0 = COPY %select(s32)
559    RET_ReallyLR implicit $w0
560
561...
562---
563name:            cmn_s32_neg_imm
564alignment:       4
565legalized:       true
566regBankSelected: true
567tracksRegLiveness: true
568body:             |
569  bb.0:
570    liveins: $w0, $w1
571
572    ; CHECK-LABEL: name: cmn_s32_neg_imm
573    ; CHECK: liveins: $w0, $w1
574    ; CHECK: %reg0:gpr32sp = COPY $w0
575    ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %reg0, 1, 0, implicit-def $nzcv
576    ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
577    ; CHECK: $w0 = COPY %cmp
578    ; CHECK: RET_ReallyLR implicit $w0
579    %reg0:gpr(s32) = COPY $w0
580    %negative_one:gpr(s32) = G_CONSTANT i32 -1
581    %zero:gpr(s32) = G_CONSTANT i32 0
582    %sub:gpr(s32) = G_SUB %zero, %negative_one
583    %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %sub
584    $w0 = COPY %cmp(s32)
585    RET_ReallyLR implicit $w0
586
587...
588---
589name:            cmn_arith_extended_shl
590alignment:       4
591legalized:       true
592regBankSelected: true
593tracksRegLiveness: true
594body:             |
595  bb.0:
596    liveins: $w0, $x0, $x1
597    ; We should be able to fold away the extend + shift and select ADDSXrx.
598
599    ; CHECK-LABEL: name: cmn_arith_extended_shl
600    ; CHECK: liveins: $w0, $x0, $x1
601    ; CHECK: %reg0:gpr64sp = COPY $x0
602    ; CHECK: %reg1:gpr32 = COPY $w0
603    ; CHECK: [[ADDSXrx:%[0-9]+]]:gpr64 = ADDSXrx %reg0, %reg1, 50, implicit-def $nzcv
604    ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
605    ; CHECK: $w0 = COPY %cmp
606    ; CHECK: RET_ReallyLR implicit $w0
607    %reg0:gpr(s64) = COPY $x0
608    %zero:gpr(s64) = G_CONSTANT i64 0
609    %sub:gpr(s64) = G_SUB %zero, %reg0
610
611    %reg1:gpr(s32) = COPY $w0
612    %ext:gpr(s64) = G_SEXT %reg1(s32)
613    %cst:gpr(s64) = G_CONSTANT i64 2
614    %shift:gpr(s64) = G_SHL %ext, %cst(s64)
615
616    %cmp:gpr(s32) = G_ICMP intpred(ne), %sub(s64), %shift
617    $w0 = COPY %cmp(s32)
618    RET_ReallyLR implicit $w0
619