1; RUN: llc -aarch64-sve-vector-bits-min=128 -asm-verbose=0 < %s | FileCheck %s -check-prefix=NO_SVE 2; RUN: llc -aarch64-sve-vector-bits-min=256 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_EQ_256 3; RUN: llc -aarch64-sve-vector-bits-min=384 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK 4; RUN: llc -aarch64-sve-vector-bits-min=512 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512 5; RUN: llc -aarch64-sve-vector-bits-min=640 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512 6; RUN: llc -aarch64-sve-vector-bits-min=768 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512 7; RUN: llc -aarch64-sve-vector-bits-min=896 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512 8; RUN: llc -aarch64-sve-vector-bits-min=1024 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 9; RUN: llc -aarch64-sve-vector-bits-min=1152 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 10; RUN: llc -aarch64-sve-vector-bits-min=1280 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 11; RUN: llc -aarch64-sve-vector-bits-min=1408 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 12; RUN: llc -aarch64-sve-vector-bits-min=1536 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 13; RUN: llc -aarch64-sve-vector-bits-min=1664 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 14; RUN: llc -aarch64-sve-vector-bits-min=1792 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 15; RUN: llc -aarch64-sve-vector-bits-min=1920 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 16; RUN: llc -aarch64-sve-vector-bits-min=2048 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024,VBITS_GE_2048 17 18target triple = "aarch64-unknown-linux-gnu" 19 20; Don't use SVE when its registers are no bigger than NEON. 21; NO_SVE-NOT: ptrue 22 23; Don't use SVE for 64-bit vectors 24define <8 x i8> @shuffle_ext_byone_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 { 25; CHECK-LABEL: shuffle_ext_byone_v8i8 26; CHECK: ext v0.8b, v0.8b, v1.8b, #7 27; CHECK-NEXT: ret 28 %ret = shufflevector <8 x i8> %op1, <8 x i8> %op2, <8 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14> 29 ret <8 x i8> %ret 30} 31 32; Don't use SVE for 128-bit vectors 33define <16 x i8> @shuffle_ext_byone_v16i8(<16 x i8> %op1, <16 x i8> %op2) { 34; CHECK-LABEL: shuffle_ext_byone_v16i8 35; CHECK: ext v0.16b, v0.16b, v1.16b, #15 36; CHECK-NEXT: ret 37 %ret = shufflevector <16 x i8> %op1, <16 x i8> %op2, <16 x i32> <i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, 38 i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30> 39 ret <16 x i8> %ret 40} 41 42define void @shuffle_ext_byone_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 { 43; CHECK-LABEL: shuffle_ext_byone_v32i8 44; CHECK: ptrue [[PG:p[0-9]+]].b, vl32 45; CHECK-NEXT: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0] 46; CHECK-NEXT: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1] 47; CHECK-NEXT: mov z[[ELEM:[0-9]+]].b, [[OP1]].b[31] 48; CHECK-NEXT: fmov [[TMP:w[0-9]+]], s[[ELEM]] 49; CHECK-NEXT: insr [[OP2]].b, [[TMP]] 50; CHECK-NEXT: st1b { [[OP2]].b }, [[PG]], [x0] 51; CHECK-NEXT: ret 52 %op1 = load <32 x i8>, <32 x i8>* %a 53 %op2 = load <32 x i8>, <32 x i8>* %b 54 %ret = shufflevector <32 x i8> %op1, <32 x i8> %op2, <32 x i32> <i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, 55 i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, 56 i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, 57 i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62> 58 store <32 x i8> %ret, <32 x i8>* %a 59 ret void 60} 61 62define void @shuffle_ext_byone_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 { 63; CHECK-LABEL: shuffle_ext_byone_v64i8 64; VBITS_GE_512: ptrue [[PG:p[0-9]+]].b, vl64 65; VBITS_GE_512-NEXT: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0] 66; VBITS_GE_512-NEXT: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1] 67; VBITS_GE_512-NEXT: mov z[[ELEM:[0-9]+]].b, [[OP1]].b[63] 68; VBITS_GE_512-NEXT: fmov [[TMP:w[0-9]+]], s[[ELEM]] 69; VBITS_GE_512-NEXT: insr [[OP2]].b, [[TMP]] 70; VBITS_GE_512-NEXT: st1b { [[OP2]].b }, [[PG]], [x0] 71; VBITS_GE_512-NEXT: ret 72 73; Ensure sensible type legalisation. 74; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].b, vl32 75; VBITS_EQ_256-DAG: mov w[[NUMELTS:[0-9]+]], #32 76; VBITS_EQ_256-DAG: ld1b { [[OP1_HI:z[0-9]+]].b }, [[PG]]/z, [x0, x[[NUMELTS]]] 77; VBITS_EQ_256-DAG: ld1b { [[OP2_LO:z[0-9]+]].b }, [[PG]]/z, [x1] 78; VBITS_EQ_256-DAG: ld1b { [[OP2_HI:z[0-9]+]].b }, [[PG]]/z, [x1, x[[NUMELTS]]] 79; VBITS_EQ_256-DAG: mov z[[ELEM1:[0-9]+]].b, [[OP1_HI]].b[31] 80; VBITS_EQ_256-DAG: fmov [[TMP1:w[0-9]+]], s[[ELEM1]] 81; VBITS_EQ_256-DAG: mov z[[ELEM2:[0-9]+]].b, [[OP2_LO]].b[31] 82; VBITS_EQ_256-DAG: insr [[OP2_LO]].b, [[TMP1]] 83; VBITS_EQ_256-DAG: fmov [[TMP2:w[0-9]+]], s[[ELEM2]] 84; VBITS_EQ_256-DAG: insr [[OP2_HI]].b, [[TMP2]] 85; VBITS_EQ_256-DAG: st1b { [[OP2_LO]].b }, [[PG]], [x0] 86; VBITS_EQ_256-DAG: st1b { [[OP2_HI]].b }, [[PG]], [x0, x[[NUMELTS]]] 87; VBITS_EQ_256-NEXT: ret 88 %op1 = load <64 x i8>, <64 x i8>* %a 89 %op2 = load <64 x i8>, <64 x i8>* %b 90 %ret = shufflevector <64 x i8> %op1, <64 x i8> %op2, <64 x i32> <i32 63, i32 64, i32 65, i32 66, i32 67, i32 68, i32 69, i32 70, 91 i32 71, i32 72, i32 73, i32 74, i32 75, i32 76, i32 77, i32 78, 92 i32 79, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, 93 i32 87, i32 88, i32 89, i32 90, i32 91, i32 92, i32 93, i32 94, 94 i32 95, i32 96, i32 97, i32 98, i32 99, i32 100, i32 101, i32 102, 95 i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, 96 i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, 97 i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126> 98 store <64 x i8> %ret, <64 x i8>* %a 99 ret void 100} 101 102define void @shuffle_ext_byone_v128i8(<128 x i8>* %a, <128 x i8>* %b) #0 { 103; CHECK-LABEL: shuffle_ext_byone_v128i8 104; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].b, vl128 105; VBITS_GE_1024-NEXT: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0] 106; VBITS_GE_1024-NEXT: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1] 107; VBITS_GE_1024-NEXT: mov w[[TMP:[0-9]+]], #127 108; VBITS_GE_1024-NEXT: whilels [[WPG:p[0-9]+]].b, xzr, x[[TMP]] 109; VBITS_GE_1024-NEXT: lastb [[TMP2:w[0-9]+]], [[WPG]], [[OP1]].b 110; VBITS_GE_1024-NEXT: insr [[OP2]].b, [[TMP2]] 111; VBITS_GE_1024-NEXT: st1b { [[OP2]].b }, [[PG]], [x0] 112; VBITS_GE_1024-NEXT: ret 113 %op1 = load <128 x i8>, <128 x i8>* %a 114 %op2 = load <128 x i8>, <128 x i8>* %b 115 %ret = shufflevector <128 x i8> %op1, <128 x i8> %op2, <128 x i32> <i32 127, i32 128, i32 129, i32 130, i32 131, i32 132, i32 133, i32 134, 116 i32 135, i32 136, i32 137, i32 138, i32 139, i32 140, i32 141, i32 142, 117 i32 143, i32 144, i32 145, i32 146, i32 147, i32 148, i32 149, i32 150, 118 i32 151, i32 152, i32 153, i32 154, i32 155, i32 156, i32 157, i32 158, 119 i32 159, i32 160, i32 161, i32 162, i32 163, i32 164, i32 165, i32 166, 120 i32 167, i32 168, i32 169, i32 170, i32 171, i32 172, i32 173, i32 174, 121 i32 175, i32 176, i32 177, i32 178, i32 179, i32 180, i32 181, i32 182, 122 i32 183, i32 184, i32 185, i32 186, i32 187, i32 188, i32 189, i32 190, 123 i32 191, i32 192, i32 193, i32 194, i32 195, i32 196, i32 197, i32 198, 124 i32 199, i32 200, i32 201, i32 202, i32 203, i32 204, i32 205, i32 206, 125 i32 207, i32 208, i32 209, i32 210, i32 211, i32 212, i32 213, i32 214, 126 i32 215, i32 216, i32 217, i32 218, i32 219, i32 220, i32 221, i32 222, 127 i32 223, i32 224, i32 225, i32 226, i32 227, i32 228, i32 229, i32 230, 128 i32 231, i32 232, i32 233, i32 234, i32 235, i32 236, i32 237, i32 238, 129 i32 239, i32 240, i32 241, i32 242, i32 243, i32 244, i32 245, i32 246, 130 i32 247, i32 248, i32 249, i32 250, i32 251, i32 252, i32 253, i32 254> 131 store <128 x i8> %ret, <128 x i8>* %a 132 ret void 133} 134 135define void @shuffle_ext_byone_v256i8(<256 x i8>* %a, <256 x i8>* %b) #0 { 136; CHECK-LABEL: shuffle_ext_byone_v256i8 137; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].b, vl256 138; VBITS_GE_2048-NEXT: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0] 139; VBITS_GE_2048-NEXT: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1] 140; VBITS_GE_2048-NEXT: mov w[[TMP:[0-9]+]], #255 141; VBITS_GE_2048-NEXT: whilels [[WPG:p[0-9]+]].b, xzr, x[[TMP]] 142; VBITS_GE_2048-NEXT: lastb [[TMP2:w[0-9]+]], [[WPG]], [[OP1]].b 143; VBITS_GE_2048-NEXT: insr [[OP2]].b, [[TMP2]] 144; VBITS_GE_2048-NEXT: st1b { [[OP2]].b }, [[PG]], [x0] 145; VBITS_GE_2048-NEXT: ret 146 %op1 = load <256 x i8>, <256 x i8>* %a 147 %op2 = load <256 x i8>, <256 x i8>* %b 148 %ret = shufflevector <256 x i8> %op1, <256 x i8> %op2, <256 x i32> <i32 255, i32 256, i32 257, i32 258, i32 259, i32 260, i32 261, i32 262, 149 i32 263, i32 264, i32 265, i32 266, i32 267, i32 268, i32 269, i32 270, 150 i32 271, i32 272, i32 273, i32 274, i32 275, i32 276, i32 277, i32 278, 151 i32 279, i32 280, i32 281, i32 282, i32 283, i32 284, i32 285, i32 286, 152 i32 287, i32 288, i32 289, i32 290, i32 291, i32 292, i32 293, i32 294, 153 i32 295, i32 296, i32 297, i32 298, i32 299, i32 300, i32 301, i32 302, 154 i32 303, i32 304, i32 305, i32 306, i32 307, i32 308, i32 309, i32 310, 155 i32 311, i32 312, i32 313, i32 314, i32 315, i32 316, i32 317, i32 318, 156 i32 319, i32 320, i32 321, i32 322, i32 323, i32 324, i32 325, i32 326, 157 i32 327, i32 328, i32 329, i32 330, i32 331, i32 332, i32 333, i32 334, 158 i32 335, i32 336, i32 337, i32 338, i32 339, i32 340, i32 341, i32 342, 159 i32 343, i32 344, i32 345, i32 346, i32 347, i32 348, i32 349, i32 350, 160 i32 351, i32 352, i32 353, i32 354, i32 355, i32 356, i32 357, i32 358, 161 i32 359, i32 360, i32 361, i32 362, i32 363, i32 364, i32 365, i32 366, 162 i32 367, i32 368, i32 369, i32 370, i32 371, i32 372, i32 373, i32 374, 163 i32 375, i32 376, i32 377, i32 378, i32 379, i32 380, i32 381, i32 382, 164 i32 383, i32 384, i32 385, i32 386, i32 387, i32 388, i32 389, i32 390, 165 i32 391, i32 392, i32 393, i32 394, i32 395, i32 396, i32 397, i32 398, 166 i32 399, i32 400, i32 401, i32 402, i32 403, i32 404, i32 405, i32 406, 167 i32 407, i32 408, i32 409, i32 410, i32 411, i32 412, i32 413, i32 414, 168 i32 415, i32 416, i32 417, i32 418, i32 419, i32 420, i32 421, i32 422, 169 i32 423, i32 424, i32 425, i32 426, i32 427, i32 428, i32 429, i32 430, 170 i32 431, i32 432, i32 433, i32 434, i32 435, i32 436, i32 437, i32 438, 171 i32 439, i32 440, i32 441, i32 442, i32 443, i32 444, i32 445, i32 446, 172 i32 447, i32 448, i32 449, i32 450, i32 451, i32 452, i32 453, i32 454, 173 i32 455, i32 456, i32 457, i32 458, i32 459, i32 460, i32 461, i32 462, 174 i32 463, i32 464, i32 465, i32 466, i32 467, i32 468, i32 469, i32 470, 175 i32 471, i32 472, i32 473, i32 474, i32 475, i32 476, i32 477, i32 478, 176 i32 479, i32 480, i32 481, i32 482, i32 483, i32 484, i32 485, i32 486, 177 i32 487, i32 488, i32 489, i32 490, i32 491, i32 492, i32 493, i32 494, 178 i32 495, i32 496, i32 497, i32 498, i32 499, i32 500, i32 501, i32 502, 179 i32 503, i32 504, i32 505, i32 506, i32 507, i32 508, i32 509, i32 510> 180 store <256 x i8> %ret, <256 x i8>* %a 181 ret void 182} 183 184; Don't use SVE for 64-bit vectors 185define <4 x i16> @shuffle_ext_byone_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 { 186; CHECK-LABEL: shuffle_ext_byone_v4i16 187; CHECK: ext v0.8b, v0.8b, v1.8b, #6 188; CHECK-NEXT: ret 189 %ret = shufflevector <4 x i16> %op1, <4 x i16> %op2, <4 x i32> <i32 3, i32 4, i32 5, i32 6> 190 ret <4 x i16> %ret 191} 192 193; Don't use SVE for 128-bit vectors 194define <8 x i16> @shuffle_ext_byone_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 { 195; CHECK-LABEL: shuffle_ext_byone_v8i16 196; CHECK: ext v0.16b, v0.16b, v1.16b, #14 197; CHECK-NEXT: ret 198 %ret = shufflevector <8 x i16> %op1, <8 x i16> %op2, <8 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14> 199 ret <8 x i16> %ret 200} 201 202define void @shuffle_ext_byone_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 { 203; CHECK-LABEL: shuffle_ext_byone_v16i16 204; CHECK: ptrue [[PG:p[0-9]+]].h, vl16 205; CHECK-NEXT: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0] 206; CHECK-NEXT: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1] 207; CHECK-NEXT: mov z[[ELEM:[0-9]+]].h, [[OP1]].h[15] 208; CHECK-NEXT: fmov [[TMP:w[0-9]+]], s[[ELEM]] 209; CHECK-NEXT: insr [[OP2]].h, [[TMP]] 210; CHECK-NEXT: st1h { [[OP2]].h }, [[PG]], [x0] 211; CHECK-NEXT: ret 212 %op1 = load <16 x i16>, <16 x i16>* %a 213 %op2 = load <16 x i16>, <16 x i16>* %b 214 %ret = shufflevector <16 x i16> %op1, <16 x i16> %op2, <16 x i32> <i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, 215 i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30> 216 store <16 x i16> %ret, <16 x i16>* %a 217 ret void 218} 219 220define void @shuffle_ext_byone_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { 221; CHECK-LABEL: shuffle_ext_byone_v32i16 222; VBITS_GE_512: ptrue [[PG:p[0-9]+]].h, vl32 223; VBITS_GE_512-NEXT: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0] 224; VBITS_GE_512-NEXT: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1] 225; VBITS_GE_512-NEXT: mov z[[ELEM:[0-9]+]].h, [[OP1]].h[31] 226; VBITS_GE_512-NEXT: fmov [[TMP:w[0-9]+]], s[[ELEM]] 227; VBITS_GE_512-NEXT: insr [[OP2]].h, [[TMP]] 228; VBITS_GE_512-NEXT: st1h { [[OP2]].h }, [[PG]], [x0] 229; VBITS_GE_512-NEXT: ret 230 231; Ensure sensible type legalisation. 232; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].h, vl16 233; VBITS_EQ_256-DAG: mov x[[NUMELTS:[0-9]+]], #16 234; VBITS_EQ_256-DAG: ld1h { [[OP1_HI:z[0-9]+]].h }, [[PG]]/z, [x0, x[[NUMELTS]], lsl #1] 235; VBITS_EQ_256-DAG: ld1h { [[OP2_LO:z[0-9]+]].h }, [[PG]]/z, [x1] 236; VBITS_EQ_256-DAG: ld1h { [[OP2_HI:z[0-9]+]].h }, [[PG]]/z, [x1, x[[NUMELTS]], lsl #1] 237; VBITS_EQ_256-DAG: mov z[[ELEM1:[0-9]+]].h, [[OP1_HI]].h[15] 238; VBITS_EQ_256-DAG: fmov [[TMP1:w[0-9]+]], s[[ELEM1]] 239; VBITS_EQ_256-DAG: mov z[[ELEM2:[0-9]+]].h, [[OP2_LO]].h[15] 240; VBITS_EQ_256-DAG: insr [[OP2_LO]].h, [[TMP1]] 241; VBITS_EQ_256-DAG: fmov [[TMP2:w[0-9]+]], s[[ELEM2]] 242; VBITS_EQ_256-DAG: insr [[OP2_HI]].h, [[TMP2]] 243; VBITS_EQ_256-DAG: st1h { [[OP2_LO]].h }, [[PG]], [x0] 244; VBITS_EQ_256-DAG: st1h { [[OP2_HI]].h }, [[PG]], [x0, x[[NUMELTS]], lsl #1] 245; VBITS_EQ_256-NEXT: ret 246 %op1 = load <32 x i16>, <32 x i16>* %a 247 %op2 = load <32 x i16>, <32 x i16>* %b 248 %ret = shufflevector <32 x i16> %op1, <32 x i16> %op2, <32 x i32> <i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, 249 i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, 250 i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, 251 i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62> 252 store <32 x i16> %ret, <32 x i16>* %a 253 ret void 254} 255 256define void @shuffle_ext_byone_v64i16(<64 x i16>* %a, <64 x i16>* %b) #0 { 257; CHECK-LABEL: shuffle_ext_byone_v64i16 258; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].h, vl64 259; VBITS_GE_1024-NEXT: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0] 260; VBITS_GE_1024-NEXT: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1] 261; VBITS_GE_1024-NEXT: mov w[[TMP:[0-9]+]], #63 262; VBITS_GE_1024-NEXT: whilels [[WPG:p[0-9]+]].h, xzr, x[[TMP]] 263; VBITS_GE_1024-NEXT: lastb [[TMP2:w[0-9]+]], [[WPG]], [[OP1]].h 264; VBITS_GE_1024-NEXT: insr [[OP2]].h, [[TMP2]] 265; VBITS_GE_1024-NEXT: st1h { [[OP2]].h }, [[PG]], [x0] 266; VBITS_GE_1024-NEXT: ret 267 %op1 = load <64 x i16>, <64 x i16>* %a 268 %op2 = load <64 x i16>, <64 x i16>* %b 269 %ret = shufflevector <64 x i16> %op1, <64 x i16> %op2, <64 x i32> <i32 63, i32 64, i32 65, i32 66, i32 67, i32 68, i32 69, i32 70, 270 i32 71, i32 72, i32 73, i32 74, i32 75, i32 76, i32 77, i32 78, 271 i32 79, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, 272 i32 87, i32 88, i32 89, i32 90, i32 91, i32 92, i32 93, i32 94, 273 i32 95, i32 96, i32 97, i32 98, i32 99, i32 100, i32 101, i32 102, 274 i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, 275 i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, 276 i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126> 277 store <64 x i16> %ret, <64 x i16>* %a 278 ret void 279} 280 281define void @shuffle_ext_byone_v128i16(<128 x i16>* %a, <128 x i16>* %b) #0 { 282; CHECK-LABEL: shuffle_ext_byone_v128i16 283; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].h, vl128 284; VBITS_GE_2048-NEXT: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0] 285; VBITS_GE_2048-NEXT: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1] 286; VBITS_GE_2048-NEXT: mov w[[TMP:[0-9]+]], #127 287; VBITS_GE_2048-NEXT: whilels [[WPG:p[0-9]+]].h, xzr, x[[TMP]] 288; VBITS_GE_2048-NEXT: lastb [[TMP2:w[0-9]+]], [[WPG]], [[OP1]].h 289; VBITS_GE_2048-NEXT: insr [[OP2]].h, [[TMP2]] 290; VBITS_GE_2048-NEXT: st1h { [[OP2]].h }, [[PG]], [x0] 291; VBITS_GE_2048-NEXT: ret 292 %op1 = load <128 x i16>, <128 x i16>* %a 293 %op2 = load <128 x i16>, <128 x i16>* %b 294 %ret = shufflevector <128 x i16> %op1, <128 x i16> %op2, <128 x i32> <i32 127, i32 128, i32 129, i32 130, i32 131, i32 132, i32 133, i32 134, 295 i32 135, i32 136, i32 137, i32 138, i32 139, i32 140, i32 141, i32 142, 296 i32 143, i32 144, i32 145, i32 146, i32 147, i32 148, i32 149, i32 150, 297 i32 151, i32 152, i32 153, i32 154, i32 155, i32 156, i32 157, i32 158, 298 i32 159, i32 160, i32 161, i32 162, i32 163, i32 164, i32 165, i32 166, 299 i32 167, i32 168, i32 169, i32 170, i32 171, i32 172, i32 173, i32 174, 300 i32 175, i32 176, i32 177, i32 178, i32 179, i32 180, i32 181, i32 182, 301 i32 183, i32 184, i32 185, i32 186, i32 187, i32 188, i32 189, i32 190, 302 i32 191, i32 192, i32 193, i32 194, i32 195, i32 196, i32 197, i32 198, 303 i32 199, i32 200, i32 201, i32 202, i32 203, i32 204, i32 205, i32 206, 304 i32 207, i32 208, i32 209, i32 210, i32 211, i32 212, i32 213, i32 214, 305 i32 215, i32 216, i32 217, i32 218, i32 219, i32 220, i32 221, i32 222, 306 i32 223, i32 224, i32 225, i32 226, i32 227, i32 228, i32 229, i32 230, 307 i32 231, i32 232, i32 233, i32 234, i32 235, i32 236, i32 237, i32 238, 308 i32 239, i32 240, i32 241, i32 242, i32 243, i32 244, i32 245, i32 246, 309 i32 247, i32 248, i32 249, i32 250, i32 251, i32 252, i32 253, i32 254> 310 store <128 x i16> %ret, <128 x i16>* %a 311 ret void 312} 313 314; Don't use SVE for 64-bit vectors 315define <2 x i32> @shuffle_ext_byone_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 { 316; CHECK-LABEL: shuffle_ext_byone_v2i32 317; CHECK: ext v0.8b, v0.8b, v1.8b, #4 318; CHECK-NEXT: ret 319 %ret = shufflevector <2 x i32> %op1, <2 x i32> %op2, <2 x i32> <i32 1, i32 2> 320 ret <2 x i32> %ret 321} 322 323; Don't use SVE for 128-bit vectors 324define <4 x i32> @shuffle_ext_byone_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 { 325; CHECK-LABEL: shuffle_ext_byone_v4i32 326; CHECK: ext v0.16b, v0.16b, v1.16b, #12 327; CHECK-NEXT: ret 328 %ret = shufflevector <4 x i32> %op1, <4 x i32> %op2, <4 x i32> <i32 3, i32 4, i32 5, i32 6> 329 ret <4 x i32> %ret 330} 331 332define void @shuffle_ext_byone_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 { 333; CHECK-LABEL: shuffle_ext_byone_v8i32 334; CHECK: ptrue [[PG:p[0-9]+]].s, vl8 335; CHECK-NEXT: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0] 336; CHECK-NEXT: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1] 337; CHECK-NEXT: mov z[[ELEM:[0-9]+]].s, [[OP1]].s[7] 338; CHECK-NEXT: fmov [[TMP:w[0-9]+]], s[[ELEM]] 339; CHECK-NEXT: insr [[OP2]].s, [[TMP]] 340; CHECK-NEXT: st1w { [[OP2]].s }, [[PG]], [x0] 341; CHECK-NEXT: ret 342 %op1 = load <8 x i32>, <8 x i32>* %a 343 %op2 = load <8 x i32>, <8 x i32>* %b 344 %ret = shufflevector <8 x i32> %op1, <8 x i32> %op2, <8 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14> 345 store <8 x i32> %ret, <8 x i32>* %a 346 ret void 347} 348 349define void @shuffle_ext_byone_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 { 350; CHECK-LABEL: shuffle_ext_byone_v16i32 351; VBITS_GE_512: ptrue [[PG:p[0-9]+]].s, vl16 352; VBITS_GE_512-NEXT: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0] 353; VBITS_GE_512-NEXT: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1] 354; VBITS_GE_512-NEXT: mov z[[ELEM:[0-9]+]].s, [[OP1]].s[15] 355; VBITS_GE_512-NEXT: fmov [[TMP:w[0-9]+]], s[[ELEM]] 356; VBITS_GE_512-NEXT: insr [[OP2]].s, [[TMP]] 357; VBITS_GE_512-NEXT: st1w { [[OP2]].s }, [[PG]], [x0] 358; VBITS_GE_512-NEXT: ret 359 360; Ensure sensible type legalisation. 361; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].s, vl8 362; VBITS_EQ_256-DAG: mov x[[NUMELTS:[0-9]+]], #8 363; VBITS_EQ_256-DAG: ld1w { [[OP1_HI:z[0-9]+]].s }, [[PG]]/z, [x0, x[[NUMELTS]], lsl #2] 364; VBITS_EQ_256-DAG: ld1w { [[OP2_LO:z[0-9]+]].s }, [[PG]]/z, [x1] 365; VBITS_EQ_256-DAG: ld1w { [[OP2_HI:z[0-9]+]].s }, [[PG]]/z, [x1, x[[NUMELTS]], lsl #2] 366; VBITS_EQ_256-DAG: mov z[[ELEM1:[0-9]+]].s, [[OP1_HI]].s[7] 367; VBITS_EQ_256-DAG: fmov [[TMP1:w[0-9]+]], s[[ELEM1]] 368; VBITS_EQ_256-DAG: mov z[[ELEM2:[0-9]+]].s, [[OP2_LO]].s[7] 369; VBITS_EQ_256-DAG: insr [[OP2_LO]].s, [[TMP1]] 370; VBITS_EQ_256-DAG: fmov [[TMP2:w[0-9]+]], s[[ELEM2]] 371; VBITS_EQ_256-DAG: insr [[OP2_HI]].s, [[TMP2]] 372; VBITS_EQ_256-DAG: st1w { [[OP2_LO]].s }, [[PG]], [x0] 373; VBITS_EQ_256-DAG: st1w { [[OP2_HI]].s }, [[PG]], [x0, x[[NUMELTS]], lsl #2] 374; VBITS_EQ_256-DAG: ret 375 376 %op1 = load <16 x i32>, <16 x i32>* %a 377 %op2 = load <16 x i32>, <16 x i32>* %b 378 %ret = shufflevector <16 x i32> %op1, <16 x i32> %op2, <16 x i32> <i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, 379 i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30> 380 store <16 x i32> %ret, <16 x i32>* %a 381 ret void 382} 383 384define void @shuffle_ext_byone_v32i32(<32 x i32>* %a, <32 x i32>* %b) #0 { 385; CHECK-LABEL: shuffle_ext_byone_v32i32 386; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].s, vl32 387; VBITS_GE_1024-NEXT: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0] 388; VBITS_GE_1024-NEXT: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1] 389; VBITS_GE_1024-NEXT: mov w[[TMP:[0-9]+]], #31 390; VBITS_GE_1024-NEXT: whilels [[WPG:p[0-9]+]].s, xzr, x[[TMP]] 391; VBITS_GE_1024-NEXT: lastb [[TMP2:w[0-9]+]], [[WPG]], [[OP1]].s 392; VBITS_GE_1024-NEXT: insr [[OP2]].s, [[TMP2]] 393; VBITS_GE_1024-NEXT: st1w { [[OP2]].s }, [[PG]], [x0] 394; VBITS_GE_1024-NEXT: ret 395 %op1 = load <32 x i32>, <32 x i32>* %a 396 %op2 = load <32 x i32>, <32 x i32>* %b 397 %ret = shufflevector <32 x i32> %op1, <32 x i32> %op2, <32 x i32> <i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, 398 i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, 399 i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, 400 i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62> 401 store <32 x i32> %ret, <32 x i32>* %a 402 ret void 403} 404 405define void @shuffle_ext_byone_v64i32(<64 x i32>* %a, <64 x i32>* %b) #0 { 406; CHECK-LABEL: shuffle_ext_byone_v64i32 407; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].s, vl64 408; VBITS_GE_2048-NEXT: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0] 409; VBITS_GE_2048-NEXT: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1] 410; VBITS_GE_2048-NEXT: mov w[[TMP:[0-9]+]], #63 411; VBITS_GE_2048-NEXT: whilels [[WPG:p[0-9]+]].s, xzr, x[[TMP]] 412; VBITS_GE_2048-NEXT: lastb [[TMP2:w[0-9]+]], [[WPG]], [[OP1]].s 413; VBITS_GE_2048-NEXT: insr [[OP2]].s, [[TMP2]] 414; VBITS_GE_2048-NEXT: st1w { [[OP2]].s }, [[PG]], [x0] 415; VBITS_GE_2048-NEXT: ret 416 %op1 = load <64 x i32>, <64 x i32>* %a 417 %op2 = load <64 x i32>, <64 x i32>* %b 418 %ret = shufflevector <64 x i32> %op1, <64 x i32> %op2, <64 x i32> <i32 63, i32 64, i32 65, i32 66, i32 67, i32 68, i32 69, i32 70, 419 i32 71, i32 72, i32 73, i32 74, i32 75, i32 76, i32 77, i32 78, 420 i32 79, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, 421 i32 87, i32 88, i32 89, i32 90, i32 91, i32 92, i32 93, i32 94, 422 i32 95, i32 96, i32 97, i32 98, i32 99, i32 100, i32 101, i32 102, 423 i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, 424 i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, 425 i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126> 426 store <64 x i32> %ret, <64 x i32>* %a 427 ret void 428} 429 430; Don't use SVE for 128-bit vectors 431define <2 x i64> @shuffle_ext_byone_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 { 432; CHECK-LABEL: shuffle_ext_byone_v2i64 433; CHECK: ext v0.16b, v0.16b, v1.16b, #8 434; CHECK-NEXT: ret 435 %ret = shufflevector <2 x i64> %op1, <2 x i64> %op2, <2 x i32> <i32 1, i32 2> 436 ret <2 x i64> %ret 437} 438 439define void @shuffle_ext_byone_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 { 440; CHECK-LABEL: shuffle_ext_byone_v4i64 441; CHECK: ptrue [[PG:p[0-9]+]].d, vl4 442; CHECK-NEXT: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0] 443; CHECK-NEXT: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1] 444; CHECK-NEXT: mov z[[ELEM:[0-9]+]].d, [[OP1]].d[3] 445; CHECK-NEXT: fmov [[TMP:x[0-9]+]], d[[ELEM]] 446; CHECK-NEXT: insr [[OP2]].d, [[TMP]] 447; CHECK-NEXT: st1d { [[OP2]].d }, [[PG]], [x0] 448; CHECK-NEXT: ret 449 %op1 = load <4 x i64>, <4 x i64>* %a 450 %op2 = load <4 x i64>, <4 x i64>* %b 451 %ret = shufflevector <4 x i64> %op1, <4 x i64> %op2, <4 x i32> <i32 3, i32 4, i32 5, i32 6> 452 store <4 x i64> %ret, <4 x i64>* %a 453 ret void 454} 455 456define void @shuffle_ext_byone_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 { 457; CHECK-LABEL: shuffle_ext_byone_v8i64 458; VBITS_GE_512: ptrue [[PG:p[0-9]+]].d, vl8 459; VBITS_GE_512-NEXT: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0] 460; VBITS_GE_512-NEXT: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1] 461; VBITS_GE_512-NEXT: mov z[[ELEM:[0-9]+]].d, [[OP1]].d[7] 462; VBITS_GE_512-NEXT: fmov [[TMP:x[0-9]+]], d[[ELEM]] 463; VBITS_GE_512-NEXT: insr [[OP2]].d, [[TMP]] 464; VBITS_GE_512-NEXT: st1d { [[OP2]].d }, [[PG]], [x0] 465; VBITS_GE_512-NEXT: ret 466 467; Ensure sensible type legalisation. 468; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].d, vl4 469; VBITS_EQ_256-DAG: mov x[[NUMELTS:[0-9]+]], #4 470; VBITS_EQ_256-DAG: ld1d { [[OP1_HI:z[0-9]+]].d }, [[PG]]/z, [x0, x[[NUMELTS]], lsl #3] 471; VBITS_EQ_256-DAG: ld1d { [[OP2_LO:z[0-9]+]].d }, [[PG]]/z, [x1] 472; VBITS_EQ_256-DAG: ld1d { [[OP2_HI:z[0-9]+]].d }, [[PG]]/z, [x1, x[[NUMELTS]], lsl #3] 473; VBITS_EQ_256-DAG: mov z[[ELEM1:[0-9]+]].d, [[OP1_HI]].d[3] 474; VBITS_EQ_256-DAG: fmov [[TMP1:x[0-9]+]], d[[ELEM1]] 475; VBITS_EQ_256-DAG: mov z[[ELEM2:[0-9]+]].d, [[OP2_LO]].d[3] 476; VBITS_EQ_256-DAG: insr [[OP2_LO]].d, [[TMP1]] 477; VBITS_EQ_256-DAG: fmov [[TMP2:x[0-9]+]], d[[ELEM2]] 478; VBITS_EQ_256-DAG: insr [[OP2_HI]].d, [[TMP2]] 479; VBITS_EQ_256-DAG: st1d { [[OP2_LO]].d }, [[PG]], [x0] 480; VBITS_EQ_256-DAG: st1d { [[OP2_HI]].d }, [[PG]], [x0, x[[NUMELTS]], lsl #3] 481; VBITS_EQ_256-NEXT: ret 482 %op1 = load <8 x i64>, <8 x i64>* %a 483 %op2 = load <8 x i64>, <8 x i64>* %b 484 %ret = shufflevector <8 x i64> %op1, <8 x i64> %op2, <8 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14> 485 store <8 x i64> %ret, <8 x i64>* %a 486 ret void 487} 488 489define void @shuffle_ext_byone_v16i64(<16 x i64>* %a, <16 x i64>* %b) #0 { 490; CHECK-LABEL: shuffle_ext_byone_v16i64 491; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].d, vl16 492; VBITS_GE_1024-NEXT: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0] 493; VBITS_GE_1024-NEXT: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1] 494; VBITS_GE_1024-NEXT: mov w[[TMP:[0-9]+]], #15 495; VBITS_GE_1024-NEXT: whilels [[WPG:p[0-9]+]].d, xzr, x[[TMP]] 496; VBITS_GE_1024-NEXT: lastb [[TMP2:x[0-9]+]], [[WPG]], [[OP1]].d 497; VBITS_GE_1024-NEXT: insr [[OP2]].d, [[TMP2]] 498; VBITS_GE_1024-NEXT: st1d { [[OP2]].d }, [[PG]], [x0] 499; VBITS_GE_1024-NEXT: ret 500 %op1 = load <16 x i64>, <16 x i64>* %a 501 %op2 = load <16 x i64>, <16 x i64>* %b 502 %ret = shufflevector <16 x i64> %op1, <16 x i64> %op2, <16 x i32> <i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, 503 i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30> 504 store <16 x i64> %ret, <16 x i64>* %a 505 ret void 506} 507 508define void @shuffle_ext_byone_v32i64(<32 x i64>* %a, <32 x i64>* %b) #0 { 509; CHECK-LABEL: shuffle_ext_byone_v32i64 510; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].d, vl32 511; VBITS_GE_2048-NEXT: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0] 512; VBITS_GE_2048-NEXT: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1] 513; VBITS_GE_2048-NEXT: mov w[[TMP:[0-9]+]], #31 514; VBITS_GE_2048-NEXT: whilels [[WPG:p[0-9]+]].d, xzr, x[[TMP]] 515; VBITS_GE_2048-NEXT: lastb [[TMP2:x[0-9]+]], [[WPG]], [[OP1]].d 516; VBITS_GE_2048-NEXT: insr [[OP2]].d, [[TMP2]] 517; VBITS_GE_2048-NEXT: st1d { [[OP2]].d }, [[PG]], [x0] 518; VBITS_GE_2048-NEXT: ret 519 %op1 = load <32 x i64>, <32 x i64>* %a 520 %op2 = load <32 x i64>, <32 x i64>* %b 521 %ret = shufflevector <32 x i64> %op1, <32 x i64> %op2, <32 x i32> <i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, 522 i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, 523 i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, 524 i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62> 525 store <32 x i64> %ret, <32 x i64>* %a 526 ret void 527} 528 529; Don't use SVE for 64-bit vectors 530define <4 x half> @shuffle_ext_byone_v4f16(<4 x half> %op1, <4 x half> %op2) #0 { 531; CHECK-LABEL: shuffle_ext_byone_v4f16 532; CHECK: ext v0.8b, v0.8b, v1.8b, #6 533; CHECK-NEXT: ret 534 %ret = shufflevector <4 x half> %op1, <4 x half> %op2, <4 x i32> <i32 3, i32 4, i32 5, i32 6> 535 ret <4 x half> %ret 536} 537 538; Don't use SVE for 128-bit vectors 539define <8 x half> @shuffle_ext_byone_v8f16(<8 x half> %op1, <8 x half> %op2) #0 { 540; CHECK-LABEL: shuffle_ext_byone_v8f16 541; CHECK: ext v0.16b, v0.16b, v1.16b, #14 542; CHECK-NEXT: ret 543 %ret = shufflevector <8 x half> %op1, <8 x half> %op2, <8 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14> 544 ret <8 x half> %ret 545} 546 547define void @shuffle_ext_byone_v16f16(<16 x half>* %a, <16 x half>* %b) #0 { 548; CHECK-LABEL: shuffle_ext_byone_v16f16 549; CHECK: ptrue [[PG:p[0-9]+]].h, vl16 550; CHECK-NEXT: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0] 551; CHECK-NEXT: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1] 552; CHECK-NEXT: mov z[[ELEM:[0-9]+]].h, [[OP1]].h[15] 553; CHECK-NEXT: insr [[OP2]].h, h[[ELEM]] 554; CHECK-NEXT: st1h { [[OP2]].h }, [[PG]], [x0] 555; CHECK-NEXT: ret 556 %op1 = load <16 x half>, <16 x half>* %a 557 %op2 = load <16 x half>, <16 x half>* %b 558 %ret = shufflevector <16 x half> %op1, <16 x half> %op2, <16 x i32> <i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, 559 i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30> 560 store <16 x half> %ret, <16 x half>* %a 561 ret void 562} 563 564define void @shuffle_ext_byone_v32f16(<32 x half>* %a, <32 x half>* %b) #0 { 565; CHECK-LABEL: shuffle_ext_byone_v32f16 566; VBITS_GE_512: ptrue [[PG:p[0-9]+]].h, vl32 567; VBITS_GE_512-NEXT: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0] 568; VBITS_GE_512-NEXT: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1] 569; VBITS_GE_512-NEXT: mov z[[ELEM:[0-9]+]].h, [[OP1]].h[31] 570; VBITS_GE_512-NEXT: insr [[OP2]].h, h[[ELEM]] 571; VBITS_GE_512-NEXT: st1h { [[OP2]].h }, [[PG]], [x0] 572; VBITS_GE_512-NEXT: ret 573 574; Ensure sensible type legalisation. 575; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].h, vl16 576; VBITS_EQ_256-DAG: mov x[[NUMELTS:[0-9]+]], #16 577; VBITS_EQ_256-DAG: ld1h { [[OP1_HI:z[0-9]+]].h }, [[PG]]/z, [x0, x[[NUMELTS]], lsl #1] 578; VBITS_EQ_256-DAG: ld1h { [[OP2_LO:z[0-9]+]].h }, [[PG]]/z, [x1] 579; VBITS_EQ_256-DAG: ld1h { [[OP2_HI:z[0-9]+]].h }, [[PG]]/z, [x1, x[[NUMELTS]], lsl #1] 580; VBITS_EQ_256-DAG: mov z[[ELEM2:[0-9]+]].h, [[OP2_LO]].h[15] 581; VBITS_EQ_256-DAG: mov z[[ELEM1:[0-9]+]].h, [[OP1_HI]].h[15] 582; VBITS_EQ_256-DAG: insr [[OP2_LO]].h, h[[ELEM1]] 583; VBITS_EQ_256-DAG: insr [[OP2_HI]].h, h[[ELEM2]] 584; VBITS_EQ_256-DAG: st1h { [[OP2_LO]].h }, [[PG]], [x0] 585; VBITS_EQ_256-DAG: st1h { [[OP2_HI]].h }, [[PG]], [x0, x[[NUMELTS]], lsl #1] 586; VBITS_EQ_256-NEXT: ret 587 %op1 = load <32 x half>, <32 x half>* %a 588 %op2 = load <32 x half>, <32 x half>* %b 589 %ret = shufflevector <32 x half> %op1, <32 x half> %op2, <32 x i32> <i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, 590 i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, 591 i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, 592 i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62> 593 store <32 x half> %ret, <32 x half>* %a 594 ret void 595} 596 597define void @shuffle_ext_byone_v64f16(<64 x half>* %a, <64 x half>* %b) #0 { 598; CHECK-LABEL: shuffle_ext_byone_v64f16 599; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].h, vl64 600; VBITS_GE_1024-NEXT: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0] 601; VBITS_GE_1024-NEXT: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1] 602; VBITS_GE_1024-NEXT: mov w[[TMP:[0-9]+]], #63 603; VBITS_GE_1024-NEXT: whilels [[WPG:p[0-9]+]].h, xzr, x[[TMP]] 604; VBITS_GE_1024-NEXT: lastb [[TMP2:h[0-9]+]], [[WPG]], [[OP1]].h 605; VBITS_GE_1024-NEXT: insr [[OP2]].h, [[TMP2]] 606; VBITS_GE_1024-NEXT: st1h { [[OP2]].h }, [[PG]], [x0] 607; VBITS_GE_1024-NEXT: ret 608 %op1 = load <64 x half>, <64 x half>* %a 609 %op2 = load <64 x half>, <64 x half>* %b 610 %ret = shufflevector <64 x half> %op1, <64 x half> %op2, <64 x i32> <i32 63, i32 64, i32 65, i32 66, i32 67, i32 68, i32 69, i32 70, 611 i32 71, i32 72, i32 73, i32 74, i32 75, i32 76, i32 77, i32 78, 612 i32 79, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, 613 i32 87, i32 88, i32 89, i32 90, i32 91, i32 92, i32 93, i32 94, 614 i32 95, i32 96, i32 97, i32 98, i32 99, i32 100, i32 101, i32 102, 615 i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, 616 i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, 617 i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126> 618 store <64 x half> %ret, <64 x half>* %a 619 ret void 620} 621 622define void @shuffle_ext_byone_v128f16(<128 x half>* %a, <128 x half>* %b) #0 { 623; CHECK-LABEL: shuffle_ext_byone_v128f16 624; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].h, vl128 625; VBITS_GE_2048-NEXT: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0] 626; VBITS_GE_2048-NEXT: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1] 627; VBITS_GE_2048-NEXT: mov w[[TMP:[0-9]+]], #127 628; VBITS_GE_2048-NEXT: whilels [[WPG:p[0-9]+]].h, xzr, x[[TMP]] 629; VBITS_GE_2048-NEXT: lastb [[TMP2:h[0-9]+]], [[WPG]], [[OP1]].h 630; VBITS_GE_2048-NEXT: insr [[OP2]].h, [[TMP2]] 631; VBITS_GE_2048-NEXT: st1h { [[OP2]].h }, [[PG]], [x0] 632; VBITS_GE_2048-NEXT: ret 633 %op1 = load <128 x half>, <128 x half>* %a 634 %op2 = load <128 x half>, <128 x half>* %b 635 %ret = shufflevector <128 x half> %op1, <128 x half> %op2, <128 x i32> <i32 127, i32 128, i32 129, i32 130, i32 131, i32 132, i32 133, i32 134, 636 i32 135, i32 136, i32 137, i32 138, i32 139, i32 140, i32 141, i32 142, 637 i32 143, i32 144, i32 145, i32 146, i32 147, i32 148, i32 149, i32 150, 638 i32 151, i32 152, i32 153, i32 154, i32 155, i32 156, i32 157, i32 158, 639 i32 159, i32 160, i32 161, i32 162, i32 163, i32 164, i32 165, i32 166, 640 i32 167, i32 168, i32 169, i32 170, i32 171, i32 172, i32 173, i32 174, 641 i32 175, i32 176, i32 177, i32 178, i32 179, i32 180, i32 181, i32 182, 642 i32 183, i32 184, i32 185, i32 186, i32 187, i32 188, i32 189, i32 190, 643 i32 191, i32 192, i32 193, i32 194, i32 195, i32 196, i32 197, i32 198, 644 i32 199, i32 200, i32 201, i32 202, i32 203, i32 204, i32 205, i32 206, 645 i32 207, i32 208, i32 209, i32 210, i32 211, i32 212, i32 213, i32 214, 646 i32 215, i32 216, i32 217, i32 218, i32 219, i32 220, i32 221, i32 222, 647 i32 223, i32 224, i32 225, i32 226, i32 227, i32 228, i32 229, i32 230, 648 i32 231, i32 232, i32 233, i32 234, i32 235, i32 236, i32 237, i32 238, 649 i32 239, i32 240, i32 241, i32 242, i32 243, i32 244, i32 245, i32 246, 650 i32 247, i32 248, i32 249, i32 250, i32 251, i32 252, i32 253, i32 254> 651 store <128 x half> %ret, <128 x half>* %a 652 ret void 653} 654 655; Don't use SVE for 64-bit vectors 656define <2 x float> @shuffle_ext_byone_v2f32(<2 x float> %op1, <2 x float> %op2) #0 { 657; CHECK-LABEL: shuffle_ext_byone_v2f32 658; CHECK: ext v0.8b, v0.8b, v1.8b, #4 659; CHECK-NEXT: ret 660 %ret = shufflevector <2 x float> %op1, <2 x float> %op2, <2 x i32> <i32 1, i32 2> 661 ret <2 x float> %ret 662} 663 664; Don't use SVE for 128-bit vectors 665define <4 x float> @shuffle_ext_byone_v4f32(<4 x float> %op1, <4 x float> %op2) #0 { 666; CHECK-LABEL: shuffle_ext_byone_v4f32 667; CHECK: ext v0.16b, v0.16b, v1.16b, #12 668; CHECK-NEXT: ret 669 %ret = shufflevector <4 x float> %op1, <4 x float> %op2, <4 x i32> <i32 3, i32 4, i32 5, i32 6> 670 ret <4 x float> %ret 671} 672 673define void @shuffle_ext_byone_v8f32(<8 x float>* %a, <8 x float>* %b) #0 { 674; CHECK-LABEL: shuffle_ext_byone_v8f32 675; CHECK: ptrue [[PG:p[0-9]+]].s, vl8 676; CHECK-NEXT: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0] 677; CHECK-NEXT: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1] 678; CHECK-NEXT: mov z[[ELEM:[0-9]+]].s, [[OP1]].s[7] 679; CHECK-NEXT: insr [[OP2]].s, s[[ELEM]] 680; CHECK-NEXT: st1w { [[OP2]].s }, [[PG]], [x0] 681; CHECK-NEXT: ret 682 %op1 = load <8 x float>, <8 x float>* %a 683 %op2 = load <8 x float>, <8 x float>* %b 684 %ret = shufflevector <8 x float> %op1, <8 x float> %op2, <8 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14> 685 store <8 x float> %ret, <8 x float>* %a 686 ret void 687} 688 689define void @shuffle_ext_byone_v16f32(<16 x float>* %a, <16 x float>* %b) #0 { 690; CHECK-LABEL: shuffle_ext_byone_v16f32 691; VBITS_GE_512: ptrue [[PG:p[0-9]+]].s, vl16 692; VBITS_GE_512-NEXT: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0] 693; VBITS_GE_512-NEXT: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1] 694; VBITS_GE_512-NEXT: mov z[[ELEM:[0-9]+]].s, [[OP1]].s[15] 695; VBITS_GE_512-NEXT: insr [[OP2]].s, s[[ELEM]] 696; VBITS_GE_512-NEXT: st1w { [[OP2]].s }, [[PG]], [x0] 697; VBITS_GE_512-NEXT: ret 698 699; Ensure sensible type legalisation. 700; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].s, vl8 701; VBITS_EQ_256-DAG: mov x[[NUMELTS:[0-9]+]], #8 702; VBITS_EQ_256-DAG: ld1w { [[OP1_HI:z[0-9]+]].s }, [[PG]]/z, [x0, x[[NUMELTS]], lsl #2] 703; VBITS_EQ_256-DAG: ld1w { [[OP2_LO:z[0-9]+]].s }, [[PG]]/z, [x1] 704; VBITS_EQ_256-DAG: ld1w { [[OP2_HI:z[0-9]+]].s }, [[PG]]/z, [x1, x[[NUMELTS]], lsl #2] 705; VBITS_EQ_256-DAG: mov z[[ELEM2:[0-9]+]].s, [[OP2_LO]].s[7] 706; VBITS_EQ_256-DAG: mov z[[ELEM1:[0-9]+]].s, [[OP1_HI]].s[7] 707; VBITS_EQ_256-DAG: insr [[OP2_LO]].s, s[[ELEM1]] 708; VBITS_EQ_256-DAG: insr [[OP2_HI]].s, s[[ELEM2]] 709; VBITS_EQ_256-DAG: st1w { [[OP2_LO]].s }, [[PG]], [x0] 710; VBITS_EQ_256-DAG: st1w { [[OP2_HI]].s }, [[PG]], [x0, x[[NUMELTS]], lsl #2] 711; VBITS_EQ_256-NEXT: ret 712 %op1 = load <16 x float>, <16 x float>* %a 713 %op2 = load <16 x float>, <16 x float>* %b 714 %ret = shufflevector <16 x float> %op1, <16 x float> %op2, <16 x i32> <i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, 715 i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30> 716 store <16 x float> %ret, <16 x float>* %a 717 ret void 718} 719 720define void @shuffle_ext_byone_v32f32(<32 x float>* %a, <32 x float>* %b) #0 { 721; CHECK-LABEL: shuffle_ext_byone_v32f32 722; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].s, vl32 723; VBITS_GE_1024-NEXT: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0] 724; VBITS_GE_1024-NEXT: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1] 725; VBITS_GE_1024-NEXT: mov w[[TMP:[0-9]+]], #31 726; VBITS_GE_1024-NEXT: whilels [[WPG:p[0-9]+]].s, xzr, x[[TMP]] 727; VBITS_GE_1024-NEXT: lastb [[TMP2:s[0-9]+]], [[WPG]], [[OP1]].s 728; VBITS_GE_1024-NEXT: insr [[OP2]].s, [[TMP2]] 729; VBITS_GE_1024-NEXT: st1w { [[OP2]].s }, [[PG]], [x0] 730; VBITS_GE_1024-NEXT: ret 731 %op1 = load <32 x float>, <32 x float>* %a 732 %op2 = load <32 x float>, <32 x float>* %b 733 %ret = shufflevector <32 x float> %op1, <32 x float> %op2, <32 x i32> <i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, 734 i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, 735 i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, 736 i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62> 737 store <32 x float> %ret, <32 x float>* %a 738 ret void 739} 740 741define void @shuffle_ext_byone_v64f32(<64 x float>* %a, <64 x float>* %b) #0 { 742; CHECK-LABEL: shuffle_ext_byone_v64f32 743; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].s, vl64 744; VBITS_GE_2048-NEXT: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0] 745; VBITS_GE_2048-NEXT: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1] 746; VBITS_GE_2048-NEXT: mov w[[TMP:[0-9]+]], #63 747; VBITS_GE_2048-NEXT: whilels [[WPG:p[0-9]+]].s, xzr, x[[TMP]] 748; VBITS_GE_2048-NEXT: lastb [[TMP2:s[0-9]+]], [[WPG]], [[OP1]].s 749; VBITS_GE_2048-NEXT: insr [[OP2]].s, [[TMP2]] 750; VBITS_GE_2048-NEXT: st1w { [[OP2]].s }, [[PG]], [x0] 751; VBITS_GE_2048-NEXT: ret 752 %op1 = load <64 x float>, <64 x float>* %a 753 %op2 = load <64 x float>, <64 x float>* %b 754 %ret = shufflevector <64 x float> %op1, <64 x float> %op2, <64 x i32> <i32 63, i32 64, i32 65, i32 66, i32 67, i32 68, i32 69, i32 70, 755 i32 71, i32 72, i32 73, i32 74, i32 75, i32 76, i32 77, i32 78, 756 i32 79, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, 757 i32 87, i32 88, i32 89, i32 90, i32 91, i32 92, i32 93, i32 94, 758 i32 95, i32 96, i32 97, i32 98, i32 99, i32 100, i32 101, i32 102, 759 i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, 760 i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, 761 i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126> 762 store <64 x float> %ret, <64 x float>* %a 763 ret void 764} 765 766; Don't use SVE for 128-bit vectors 767define <2 x double> @shuffle_ext_byone_v2f64(<2 x double> %op1, <2 x double> %op2) #0 { 768; CHECK-LABEL: shuffle_ext_byone_v2f64 769; CHECK: ext v0.16b, v0.16b, v1.16b, #8 770; CHECK-NEXT: ret 771 %ret = shufflevector <2 x double> %op1, <2 x double> %op2, <2 x i32> <i32 1, i32 2> 772 ret <2 x double> %ret 773} 774 775define void @shuffle_ext_byone_v4f64(<4 x double>* %a, <4 x double>* %b) #0 { 776; CHECK-LABEL: shuffle_ext_byone_v4f64 777; CHECK: ptrue [[PG:p[0-9]+]].d, vl4 778; CHECK-NEXT: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0] 779; CHECK-NEXT: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1] 780; CHECK-NEXT: mov z[[ELEM:[0-9]+]].d, [[OP1]].d[3] 781; CHECK-NEXT: insr [[OP2]].d, d[[ELEM]] 782; CHECK-NEXT: st1d { [[OP2]].d }, [[PG]], [x0] 783; CHECK-NEXT: ret 784 %op1 = load <4 x double>, <4 x double>* %a 785 %op2 = load <4 x double>, <4 x double>* %b 786 %ret = shufflevector <4 x double> %op1, <4 x double> %op2, <4 x i32> <i32 3, i32 4, i32 5, i32 6> 787 store <4 x double> %ret, <4 x double>* %a 788 ret void 789} 790 791define void @shuffle_ext_byone_v8f64(<8 x double>* %a, <8 x double>* %b) #0 { 792; CHECK-LABEL: shuffle_ext_byone_v8f64 793; VBITS_GE_512: ptrue [[PG:p[0-9]+]].d, vl8 794; VBITS_GE_512-NEXT: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0] 795; VBITS_GE_512-NEXT: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1] 796; VBITS_GE_512-NEXT: mov z[[ELEM:[0-9]+]].d, [[OP1]].d[7] 797; VBITS_GE_512-NEXT: insr [[OP2]].d, d[[ELEM]] 798; VBITS_GE_512-NEXT: st1d { [[OP2]].d }, [[PG]], [x0] 799; VBITS_GE_512-NEXT: ret 800 801; Ensure sensible type legalisation. 802; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].d, vl4 803; VBITS_EQ_256-DAG: mov x[[NUMELTS:[0-9]+]], #4 804; VBITS_EQ_256-DAG: ld1d { [[OP1_HI:z[0-9]+]].d }, [[PG]]/z, [x0, x[[NUMELTS]], lsl #3] 805; VBITS_EQ_256-DAG: ld1d { [[OP2_LO:z[0-9]+]].d }, [[PG]]/z, [x1] 806; VBITS_EQ_256-DAG: ld1d { [[OP2_HI:z[0-9]+]].d }, [[PG]]/z, [x1, x[[NUMELTS]], lsl #3] 807; VBITS_EQ_256-DAG: mov z[[ELEM2:[0-9]+]].d, [[OP2_LO]].d[3] 808; VBITS_EQ_256-DAG: mov z[[ELEM1:[0-9]+]].d, [[OP1_HI]].d[3] 809; VBITS_EQ_256-DAG: insr [[OP2_LO]].d, d[[ELEM1]] 810; VBITS_EQ_256-DAG: insr [[OP2_HI]].d, d[[ELEM2]] 811; VBITS_EQ_256-DAG: st1d { [[OP2_LO]].d }, [[PG]], [x0] 812; VBITS_EQ_256-DAG: st1d { [[OP2_HI]].d }, [[PG]], [x0, x[[NUMELTS]], lsl #3] 813; VBITS_EQ_256-NEXT: ret 814 %op1 = load <8 x double>, <8 x double>* %a 815 %op2 = load <8 x double>, <8 x double>* %b 816 %ret = shufflevector <8 x double> %op1, <8 x double> %op2, <8 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14> 817 store <8 x double> %ret, <8 x double>* %a 818 ret void 819} 820 821define void @shuffle_ext_byone_v16f64(<16 x double>* %a, <16 x double>* %b) #0 { 822; CHECK-LABEL: shuffle_ext_byone_v16f64 823; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].d, vl16 824; VBITS_GE_1024-NEXT: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0] 825; VBITS_GE_1024-NEXT: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1] 826; VBITS_GE_1024-NEXT: mov w[[TMP:[0-9]+]], #15 827; VBITS_GE_1024-NEXT: whilels [[WPG:p[0-9]+]].d, xzr, x[[TMP]] 828; VBITS_GE_1024-NEXT: lastb [[TMP2:d[0-9]+]], [[WPG]], [[OP1]].d 829; VBITS_GE_1024-NEXT: insr [[OP2]].d, [[TMP2]] 830; VBITS_GE_1024-NEXT: st1d { [[OP2]].d }, [[PG]], [x0] 831; VBITS_GE_1024-NEXT: ret 832 %op1 = load <16 x double>, <16 x double>* %a 833 %op2 = load <16 x double>, <16 x double>* %b 834 %ret = shufflevector <16 x double> %op1, <16 x double> %op2, <16 x i32> <i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, 835 i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30> 836 store <16 x double> %ret, <16 x double>* %a 837 ret void 838} 839 840define void @shuffle_ext_byone_v32f64(<32 x double>* %a, <32 x double>* %b) #0 { 841; CHECK-LABEL: shuffle_ext_byone_v32f64 842; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].d, vl32 843; VBITS_GE_2048-NEXT: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0] 844; VBITS_GE_2048-NEXT: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1] 845; VBITS_GE_2048-NEXT: mov w[[TMP:[0-9]+]], #31 846; VBITS_GE_2048-NEXT: whilels [[WPG:p[0-9]+]].d, xzr, x[[TMP]] 847; VBITS_GE_2048-NEXT: lastb [[TMP2:d[0-9]+]], [[WPG]], [[OP1]].d 848; VBITS_GE_2048-NEXT: insr [[OP2]].d, [[TMP2]] 849; VBITS_GE_2048-NEXT: st1d { [[OP2]].d }, [[PG]], [x0] 850; VBITS_GE_2048-NEXT: ret 851 %op1 = load <32 x double>, <32 x double>* %a 852 %op2 = load <32 x double>, <32 x double>* %b 853 %ret = shufflevector <32 x double> %op1, <32 x double> %op2, <32 x i32> <i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, 854 i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, 855 i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, 856 i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62> 857 store <32 x double> %ret, <32 x double>* %a 858 ret void 859} 860 861define void @shuffle_ext_byone_reverse(<4 x double>* %a, <4 x double>* %b) #0 { 862; CHECK-LABEL: shuffle_ext_byone_reverse 863; CHECK: ptrue [[PG:p[0-9]+]].d, vl4 864; CHECK-NEXT: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0] 865; CHECK-NEXT: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1] 866; CHECK-NEXT: mov z[[ELEM:[0-9]+]].d, [[OP2]].d[3] 867; CHECK-NEXT: insr [[OP1]].d, d[[ELEM]] 868; CHECK-NEXT: st1d { [[OP1]].d }, [[PG]], [x0] 869; CHECK-NEXT: ret 870 %op1 = load <4 x double>, <4 x double>* %a 871 %op2 = load <4 x double>, <4 x double>* %b 872 %ret = shufflevector <4 x double> %op1, <4 x double> %op2, <4 x i32> <i32 7, i32 0, i32 1, i32 2> 873 store <4 x double> %ret, <4 x double>* %a 874 ret void 875} 876 877define void @shuffle_ext_invalid(<4 x double>* %a, <4 x double>* %b) #0 { 878; CHECK-LABEL: shuffle_ext_invalid 879; CHECK: ptrue [[PG:p[0-9]+]].d, vl4 880; CHECK-NEXT: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0] 881; CHECK-NEXT: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1] 882; CHECK-NEXT: mov x8, sp 883; CHECK-NEXT: mov z2.d, [[OP1]].d[3] 884; CHECK-NEXT: mov z3.d, [[OP2]].d[1] 885; CHECK-NEXT: mov z0.d, [[OP1]].d[2] 886; CHECK-NEXT: stp d1, d3, [sp, #16] 887; CHECK-NEXT: stp d0, d2, [sp] 888; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8] 889; CHECK-NEXT: st1d { z0.d }, p0, [x0] 890; CHECK-NEXT: mov sp, x29 891; CHECK-NEXT: ldp x29, x30, [sp], #16 892; CHECK-NEXT: ret 893 %op1 = load <4 x double>, <4 x double>* %a 894 %op2 = load <4 x double>, <4 x double>* %b 895 %ret = shufflevector <4 x double> %op1, <4 x double> %op2, <4 x i32> <i32 2, i32 3, i32 4, i32 5> 896 store <4 x double> %ret, <4 x double>* %a 897 ret void 898} 899 900attributes #0 = { "target-features"="+sve" } 901