1; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt,-enable-ds128 < %s | FileCheck --check-prefix=CI %s 2 3@lds = addrspace(3) global [512 x float] undef, align 4 4@lds.v2 = addrspace(3) global [512 x <2 x float>] undef, align 4 5@lds.v3 = addrspace(3) global [512 x <3 x float>] undef, align 4 6@lds.v4 = addrspace(3) global [512 x <4 x float>] undef, align 4 7@lds.v8 = addrspace(3) global [512 x <8 x float>] undef, align 4 8@lds.v16 = addrspace(3) global [512 x <16 x float>] undef, align 4 9 10; CI-LABEL: {{^}}simple_read2_v2f32_superreg_align4: 11; CI: ds_read2_b32 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}} 12; CI: s_waitcnt lgkmcnt(0) 13; CI: buffer_store_dwordx2 [[RESULT]] 14; CI: s_endpgm 15define amdgpu_kernel void @simple_read2_v2f32_superreg_align4(<2 x float> addrspace(1)* %out) #0 { 16 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 17 %arrayidx0 = getelementptr inbounds [512 x <2 x float>], [512 x <2 x float>] addrspace(3)* @lds.v2, i32 0, i32 %x.i 18 %val0 = load <2 x float>, <2 x float> addrspace(3)* %arrayidx0, align 4 19 %out.gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %out, i32 %x.i 20 store <2 x float> %val0, <2 x float> addrspace(1)* %out.gep 21 ret void 22} 23 24; CI-LABEL: {{^}}simple_read2_v2f32_superreg: 25; CI: ds_read_b64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}{{$}} 26; CI: s_waitcnt lgkmcnt(0) 27; CI: buffer_store_dwordx2 [[RESULT]] 28; CI: s_endpgm 29define amdgpu_kernel void @simple_read2_v2f32_superreg(<2 x float> addrspace(1)* %out) #0 { 30 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 31 %arrayidx0 = getelementptr inbounds [512 x <2 x float>], [512 x <2 x float>] addrspace(3)* @lds.v2, i32 0, i32 %x.i 32 %val0 = load <2 x float>, <2 x float> addrspace(3)* %arrayidx0 33 %out.gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %out, i32 %x.i 34 store <2 x float> %val0, <2 x float> addrspace(1)* %out.gep 35 ret void 36} 37 38; CI-LABEL: {{^}}simple_read2_v4f32_superreg_align4: 39; CI-DAG: ds_read2_b32 v{{\[}}[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1{{$}} 40; CI-DAG: ds_read2_b32 v{{\[}}[[REG_Z:[0-9]+]]:[[REG_W:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}} 41; CI-DAG: v_add_f32_e32 v[[ADD0:[0-9]+]], v[[REG_X]], v[[REG_Z]] 42; CI-DAG: v_add_f32_e32 v[[ADD1:[0-9]+]], v[[REG_Y]], v[[REG_W]] 43; CI: v_add_f32_e32 v[[ADD2:[0-9]+]], v[[ADD0]], v[[ADD1]] 44; CI: buffer_store_dword v[[ADD2]] 45; CI: s_endpgm 46define amdgpu_kernel void @simple_read2_v4f32_superreg_align4(float addrspace(1)* %out) #0 { 47 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 48 %arrayidx0 = getelementptr inbounds [512 x <4 x float>], [512 x <4 x float>] addrspace(3)* @lds.v4, i32 0, i32 %x.i 49 %val0 = load <4 x float>, <4 x float> addrspace(3)* %arrayidx0, align 4 50 %elt0 = extractelement <4 x float> %val0, i32 0 51 %elt1 = extractelement <4 x float> %val0, i32 1 52 %elt2 = extractelement <4 x float> %val0, i32 2 53 %elt3 = extractelement <4 x float> %val0, i32 3 54 55 %add0 = fadd float %elt0, %elt2 56 %add1 = fadd float %elt1, %elt3 57 %add2 = fadd float %add0, %add1 58 59 %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i 60 store float %add2, float addrspace(1)* %out.gep 61 ret void 62} 63 64; CI-LABEL: {{^}}simple_read2_v3f32_superreg_align4: 65; CI-DAG: ds_read2_b32 v{{\[}}[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1{{$}} 66; CI-DAG: ds_read_b32 v[[REG_Z:[0-9]+]], v{{[0-9]+}} offset:8{{$}} 67; CI-DAG: v_add_f32_e32 v[[ADD0:[0-9]+]], v[[REG_X]], v[[REG_Z]] 68; CI-DAG: v_add_f32_e32 v[[ADD1:[0-9]+]], v[[ADD0]], v[[REG_Y]] 69; CI: buffer_store_dword v[[ADD1]] 70; CI: s_endpgm 71define amdgpu_kernel void @simple_read2_v3f32_superreg_align4(float addrspace(1)* %out) #0 { 72 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 73 %arrayidx0 = getelementptr inbounds [512 x <3 x float>], [512 x <3 x float>] addrspace(3)* @lds.v3, i32 0, i32 %x.i 74 %val0 = load <3 x float>, <3 x float> addrspace(3)* %arrayidx0, align 4 75 %elt0 = extractelement <3 x float> %val0, i32 0 76 %elt1 = extractelement <3 x float> %val0, i32 1 77 %elt2 = extractelement <3 x float> %val0, i32 2 78 79 %add0 = fadd float %elt0, %elt2 80 %add1 = fadd float %add0, %elt1 81 82 %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i 83 store float %add1, float addrspace(1)* %out.gep 84 ret void 85} 86 87; CI-LABEL: {{^}}simple_read2_v4f32_superreg_align8: 88; CI: ds_read2_b64 [[REG_ZW:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}} 89; CI: buffer_store_dwordx4 [[REG_ZW]] 90; CI: s_endpgm 91define amdgpu_kernel void @simple_read2_v4f32_superreg_align8(<4 x float> addrspace(1)* %out) #0 { 92 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 93 %arrayidx0 = getelementptr inbounds [512 x <4 x float>], [512 x <4 x float>] addrspace(3)* @lds.v4, i32 0, i32 %x.i 94 %val0 = load <4 x float>, <4 x float> addrspace(3)* %arrayidx0, align 8 95 %out.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %out, i32 %x.i 96 store <4 x float> %val0, <4 x float> addrspace(1)* %out.gep 97 ret void 98} 99 100; CI-LABEL: {{^}}simple_read2_v4f32_superreg: 101; CI-DAG: ds_read2_b64 [[REG_ZW:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}} 102; CI: buffer_store_dwordx4 [[REG_ZW]] 103; CI: s_endpgm 104define amdgpu_kernel void @simple_read2_v4f32_superreg(<4 x float> addrspace(1)* %out) #0 { 105 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 106 %arrayidx0 = getelementptr inbounds [512 x <4 x float>], [512 x <4 x float>] addrspace(3)* @lds.v4, i32 0, i32 %x.i 107 %val0 = load <4 x float>, <4 x float> addrspace(3)* %arrayidx0 108 %out.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %out, i32 %x.i 109 store <4 x float> %val0, <4 x float> addrspace(1)* %out.gep 110 ret void 111} 112 113; FIXME: Extra moves shuffling superregister 114; CI-LABEL: {{^}}simple_read2_v8f32_superreg: 115; CI-DAG: ds_read2_b64 [[VEC_HI:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:2 offset1:3{{$}} 116; CI-DAG: ds_read2_b64 [[VEC_LO:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}} 117; CI-DAG: buffer_store_dwordx4 [[VEC_HI]], v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:16 118; CI-DAG: buffer_store_dwordx4 [[VEC_LO]], v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64{{$}} 119; CI: s_endpgm 120define amdgpu_kernel void @simple_read2_v8f32_superreg(<8 x float> addrspace(1)* %out) #0 { 121 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 122 %arrayidx0 = getelementptr inbounds [512 x <8 x float>], [512 x <8 x float>] addrspace(3)* @lds.v8, i32 0, i32 %x.i 123 %val0 = load <8 x float>, <8 x float> addrspace(3)* %arrayidx0 124 %out.gep = getelementptr inbounds <8 x float>, <8 x float> addrspace(1)* %out, i32 %x.i 125 store <8 x float> %val0, <8 x float> addrspace(1)* %out.gep 126 ret void 127} 128 129; FIXME: Extra moves shuffling superregister 130; CI-LABEL: {{^}}simple_read2_v16f32_superreg: 131; CI-DAG: ds_read2_b64 [[VEC0_3:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}} 132; CI-DAG: ds_read2_b64 [[VEC4_7:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:2 offset1:3{{$}} 133; CI-DAG: ds_read2_b64 [[VEC8_11:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:4 offset1:5{{$}} 134; CI-DAG: ds_read2_b64 [[VEC12_15:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:6 offset1:7{{$}} 135; CI: s_waitcnt lgkmcnt(0) 136; CI-DAG: buffer_store_dwordx4 [[VEC0_3]], v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64{{$}} 137; CI-DAG: buffer_store_dwordx4 [[VEC4_7]], v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:16 138; CI-DAG: buffer_store_dwordx4 [[VEC8_11]], v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:32 139; CI-DAG: buffer_store_dwordx4 [[VEC12_15]], v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:48 140; CI: s_endpgm 141define amdgpu_kernel void @simple_read2_v16f32_superreg(<16 x float> addrspace(1)* %out) #0 { 142 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 143 %arrayidx0 = getelementptr inbounds [512 x <16 x float>], [512 x <16 x float>] addrspace(3)* @lds.v16, i32 0, i32 %x.i 144 %val0 = load <16 x float>, <16 x float> addrspace(3)* %arrayidx0 145 %out.gep = getelementptr inbounds <16 x float>, <16 x float> addrspace(1)* %out, i32 %x.i 146 store <16 x float> %val0, <16 x float> addrspace(1)* %out.gep 147 ret void 148} 149 150; Do scalar loads into the super register we need. 151; CI-LABEL: {{^}}simple_read2_v2f32_superreg_scalar_loads_align4: 152; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT0:[0-9]+]]:[[REG_ELT1:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1{{$}} 153; CI-NOT: v_mov {{v[0-9]+}}, {{[sv][0-9]+}} 154; CI: buffer_store_dwordx2 v{{\[}}[[REG_ELT0]]:[[REG_ELT1]]{{\]}} 155; CI: s_endpgm 156define amdgpu_kernel void @simple_read2_v2f32_superreg_scalar_loads_align4(<2 x float> addrspace(1)* %out) #0 { 157 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 158 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i 159 %arrayidx1 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 1 160 161 %val0 = load float, float addrspace(3)* %arrayidx0 162 %val1 = load float, float addrspace(3)* %arrayidx1 163 164 %vec.0 = insertelement <2 x float> undef, float %val0, i32 0 165 %vec.1 = insertelement <2 x float> %vec.0, float %val1, i32 1 166 167 %out.gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %out, i32 %x.i 168 store <2 x float> %vec.1, <2 x float> addrspace(1)* %out.gep 169 ret void 170} 171 172; Do scalar loads into the super register we need. 173; CI-LABEL: {{^}}simple_read2_v4f32_superreg_scalar_loads_align4: 174; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT0:[0-9]+]]:[[REG_ELT1:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1{{$}} 175; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT2:[0-9]+]]:[[REG_ELT3:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}} 176; CI-NOT: v_mov {{v[0-9]+}}, {{[sv][0-9]+}} 177; CI: buffer_store_dwordx4 v{{\[}}[[REG_ELT0]]:[[REG_ELT3]]{{\]}} 178; CI: s_endpgm 179define amdgpu_kernel void @simple_read2_v4f32_superreg_scalar_loads_align4(<4 x float> addrspace(1)* %out) #0 { 180 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 181 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i 182 %arrayidx1 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 1 183 %arrayidx2 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 2 184 %arrayidx3 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 3 185 186 %val0 = load float, float addrspace(3)* %arrayidx0 187 %val1 = load float, float addrspace(3)* %arrayidx1 188 %val2 = load float, float addrspace(3)* %arrayidx2 189 %val3 = load float, float addrspace(3)* %arrayidx3 190 191 %vec.0 = insertelement <4 x float> undef, float %val0, i32 0 192 %vec.1 = insertelement <4 x float> %vec.0, float %val1, i32 1 193 %vec.2 = insertelement <4 x float> %vec.1, float %val2, i32 2 194 %vec.3 = insertelement <4 x float> %vec.2, float %val3, i32 3 195 196 %out.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %out, i32 %x.i 197 store <4 x float> %vec.3, <4 x float> addrspace(1)* %out.gep 198 ret void 199} 200 201; Function Attrs: nounwind readnone 202declare i32 @llvm.amdgcn.workitem.id.x() #1 203 204; Function Attrs: nounwind readnone 205declare i32 @llvm.amdgcn.workitem.id.y() #1 206 207attributes #0 = { nounwind } 208attributes #1 = { nounwind readnone } 209attributes #2 = { convergent nounwind } 210