1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck %s 3 4; Test for ICE in SelectionDAG::computeKnownBits when visiting EXTRACT_SUBVECTOR 5; with DemandedElts already as wide as the source vector. 6 7define <3 x i32> @quux() { 8; CHECK-LABEL: quux: 9; CHECK: ; %bb.0: ; %bb 10; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 11; CHECK-NEXT: v_mov_b32_e32 v0, 0 12; CHECK-NEXT: v_mov_b32_e32 v1, 1 13; CHECK-NEXT: v_mov_b32_e32 v2, 1 14; CHECK-NEXT: s_setpc_b64 s[30:31] 15bb: 16 %tmp = shufflevector <4 x i8> <i8 1, i8 2, i8 3, i8 4>, <4 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2> 17 %tmp1 = extractelement <3 x i8> %tmp, i64 0 18 %tmp2 = zext i8 %tmp1 to i32 19 %tmp3 = insertelement <3 x i32> undef, i32 %tmp2, i32 0 20 %tmp4 = extractelement <3 x i8> %tmp, i64 1 21 %tmp5 = zext i8 %tmp4 to i32 22 %tmp6 = insertelement <3 x i32> %tmp3, i32 %tmp5, i32 1 23 %tmp7 = extractelement <3 x i8> %tmp, i64 2 24 %tmp8 = zext i8 %tmp7 to i32 25 %tmp9 = insertelement <3 x i32> %tmp6, i32 %tmp8, i32 2 26 %tmp10 = lshr <3 x i32> %tmp9, <i32 1, i32 1, i32 1> 27 ret <3 x i32> %tmp10 28} 29