1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 3; RUN: llc -march=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=SI %s 4; RUN: opt -mtriple=amdgcn-- -S -amdgpu-unify-divergent-exit-nodes -verify -simplifycfg-require-and-preserve-domtree=1 %s | FileCheck -check-prefix=IR %s 5 6define amdgpu_kernel void @infinite_loop(i32 addrspace(1)* %out) { 7; SI-LABEL: infinite_loop: 8; SI: ; %bb.0: ; %entry 9; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 10; SI-NEXT: s_mov_b32 s3, 0xf000 11; SI-NEXT: s_mov_b32 s2, -1 12; SI-NEXT: v_mov_b32_e32 v0, 0x3e7 13; SI-NEXT: BB0_1: ; %loop 14; SI-NEXT: ; =>This Inner Loop Header: Depth=1 15; SI-NEXT: s_waitcnt lgkmcnt(0) 16; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 17; SI-NEXT: s_waitcnt vmcnt(0) 18; SI-NEXT: s_branch BB0_1 19; IR-LABEL: @infinite_loop( 20; IR-NEXT: entry: 21; IR-NEXT: br label [[LOOP:%.*]] 22; IR: loop: 23; IR-NEXT: store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4 24; IR-NEXT: br label [[LOOP]] 25entry: 26 br label %loop 27 28loop: 29 store volatile i32 999, i32 addrspace(1)* %out, align 4 30 br label %loop 31} 32 33define amdgpu_kernel void @infinite_loop_ret(i32 addrspace(1)* %out) { 34; SI-LABEL: infinite_loop_ret: 35; SI: ; %bb.0: ; %entry 36; SI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 37; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc 38; SI-NEXT: s_cbranch_execz BB1_3 39; SI-NEXT: ; %bb.1: ; %loop.preheader 40; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 41; SI-NEXT: s_mov_b32 s3, 0xf000 42; SI-NEXT: s_mov_b32 s2, -1 43; SI-NEXT: v_mov_b32_e32 v0, 0x3e7 44; SI-NEXT: s_and_b64 vcc, exec, -1 45; SI-NEXT: BB1_2: ; %loop 46; SI-NEXT: ; =>This Inner Loop Header: Depth=1 47; SI-NEXT: s_waitcnt lgkmcnt(0) 48; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 49; SI-NEXT: s_waitcnt vmcnt(0) 50; SI-NEXT: s_mov_b64 vcc, vcc 51; SI-NEXT: s_cbranch_vccnz BB1_2 52; SI-NEXT: BB1_3: ; %UnifiedReturnBlock 53; SI-NEXT: s_endpgm 54; IR-LABEL: @infinite_loop_ret( 55; IR-NEXT: entry: 56; IR-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x() 57; IR-NEXT: [[COND:%.*]] = icmp eq i32 [[TMP]], 1 58; IR-NEXT: br i1 [[COND]], label [[LOOP:%.*]], label [[UNIFIEDRETURNBLOCK:%.*]] 59; IR: loop: 60; IR-NEXT: store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4 61; IR-NEXT: br i1 true, label [[LOOP]], label [[UNIFIEDRETURNBLOCK]] 62; IR: UnifiedReturnBlock: 63; IR-NEXT: ret void 64entry: 65 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() 66 %cond = icmp eq i32 %tmp, 1 67 br i1 %cond, label %loop, label %return 68 69loop: 70 store volatile i32 999, i32 addrspace(1)* %out, align 4 71 br label %loop 72 73return: 74 ret void 75} 76 77define amdgpu_kernel void @infinite_loops(i32 addrspace(1)* %out) { 78; SI-LABEL: infinite_loops: 79; SI: ; %bb.0: ; %entry 80; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 81; SI-NEXT: s_mov_b64 s[2:3], -1 82; SI-NEXT: s_cbranch_scc1 BB2_4 83; SI-NEXT: ; %bb.1: 84; SI-NEXT: s_mov_b32 s3, 0xf000 85; SI-NEXT: s_mov_b32 s2, -1 86; SI-NEXT: v_mov_b32_e32 v0, 0x378 87; SI-NEXT: s_and_b64 vcc, exec, -1 88; SI-NEXT: BB2_2: ; %loop2 89; SI-NEXT: ; =>This Inner Loop Header: Depth=1 90; SI-NEXT: s_waitcnt lgkmcnt(0) 91; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 92; SI-NEXT: s_waitcnt vmcnt(0) 93; SI-NEXT: s_mov_b64 vcc, vcc 94; SI-NEXT: s_cbranch_vccnz BB2_2 95; SI-NEXT: ; %bb.3: ; %Flow 96; SI-NEXT: s_mov_b64 s[2:3], 0 97; SI-NEXT: BB2_4: ; %Flow2 98; SI-NEXT: s_and_b64 vcc, exec, s[2:3] 99; SI-NEXT: s_waitcnt lgkmcnt(0) 100; SI-NEXT: s_mov_b64 vcc, vcc 101; SI-NEXT: s_cbranch_vccz BB2_7 102; SI-NEXT: ; %bb.5: 103; SI-NEXT: s_mov_b32 s3, 0xf000 104; SI-NEXT: s_mov_b32 s2, -1 105; SI-NEXT: s_waitcnt expcnt(0) 106; SI-NEXT: v_mov_b32_e32 v0, 0x3e7 107; SI-NEXT: s_and_b64 vcc, exec, 0 108; SI-NEXT: BB2_6: ; %loop1 109; SI-NEXT: ; =>This Inner Loop Header: Depth=1 110; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 111; SI-NEXT: s_waitcnt vmcnt(0) 112; SI-NEXT: s_mov_b64 vcc, vcc 113; SI-NEXT: s_cbranch_vccz BB2_6 114; SI-NEXT: BB2_7: ; %DummyReturnBlock 115; SI-NEXT: s_endpgm 116; IR-LABEL: @infinite_loops( 117; IR-NEXT: entry: 118; IR-NEXT: br i1 undef, label [[LOOP1:%.*]], label [[LOOP2:%.*]] 119; IR: loop1: 120; IR-NEXT: store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4 121; IR-NEXT: br i1 true, label [[LOOP1]], label [[DUMMYRETURNBLOCK:%.*]] 122; IR: loop2: 123; IR-NEXT: store volatile i32 888, i32 addrspace(1)* [[OUT]], align 4 124; IR-NEXT: br i1 true, label [[LOOP2]], label [[DUMMYRETURNBLOCK]] 125; IR: DummyReturnBlock: 126; IR-NEXT: ret void 127entry: 128 br i1 undef, label %loop1, label %loop2 129 130loop1: 131 store volatile i32 999, i32 addrspace(1)* %out, align 4 132 br label %loop1 133 134loop2: 135 store volatile i32 888, i32 addrspace(1)* %out, align 4 136 br label %loop2 137} 138 139define amdgpu_kernel void @infinite_loop_nest_ret(i32 addrspace(1)* %out) { 140; SI-LABEL: infinite_loop_nest_ret: 141; SI: ; %bb.0: ; %entry 142; SI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 143; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc 144; SI-NEXT: s_cbranch_execz BB3_5 145; SI-NEXT: ; %bb.1: ; %outer_loop.preheader 146; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 147; SI-NEXT: v_cmp_ne_u32_e64 s[0:1], 3, v0 148; SI-NEXT: s_mov_b32 s7, 0xf000 149; SI-NEXT: s_mov_b32 s6, -1 150; SI-NEXT: BB3_2: ; %outer_loop 151; SI-NEXT: ; =>This Loop Header: Depth=1 152; SI-NEXT: ; Child Loop BB3_3 Depth 2 153; SI-NEXT: s_mov_b64 s[2:3], 0 154; SI-NEXT: BB3_3: ; %inner_loop 155; SI-NEXT: ; Parent Loop BB3_2 Depth=1 156; SI-NEXT: ; => This Inner Loop Header: Depth=2 157; SI-NEXT: s_and_b64 s[8:9], exec, s[0:1] 158; SI-NEXT: s_or_b64 s[2:3], s[8:9], s[2:3] 159; SI-NEXT: s_waitcnt expcnt(0) 160; SI-NEXT: v_mov_b32_e32 v0, 0x3e7 161; SI-NEXT: s_waitcnt lgkmcnt(0) 162; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 163; SI-NEXT: s_waitcnt vmcnt(0) 164; SI-NEXT: s_andn2_b64 exec, exec, s[2:3] 165; SI-NEXT: s_cbranch_execnz BB3_3 166; SI-NEXT: ; %bb.4: ; %loop.exit.guard 167; SI-NEXT: ; in Loop: Header=BB3_2 Depth=1 168; SI-NEXT: s_or_b64 exec, exec, s[2:3] 169; SI-NEXT: s_mov_b64 vcc, 0 170; SI-NEXT: s_branch BB3_2 171; SI-NEXT: BB3_5: ; %UnifiedReturnBlock 172; SI-NEXT: s_endpgm 173; IR-LABEL: @infinite_loop_nest_ret( 174; IR-NEXT: entry: 175; IR-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x() 176; IR-NEXT: [[COND1:%.*]] = icmp eq i32 [[TMP]], 1 177; IR-NEXT: br i1 [[COND1]], label [[OUTER_LOOP:%.*]], label [[UNIFIEDRETURNBLOCK:%.*]] 178; IR: outer_loop: 179; IR-NEXT: br label [[INNER_LOOP:%.*]] 180; IR: inner_loop: 181; IR-NEXT: store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4 182; IR-NEXT: [[COND3:%.*]] = icmp eq i32 [[TMP]], 3 183; IR-NEXT: br i1 true, label [[TRANSITIONBLOCK:%.*]], label [[UNIFIEDRETURNBLOCK]] 184; IR: TransitionBlock: 185; IR-NEXT: br i1 [[COND3]], label [[INNER_LOOP]], label [[OUTER_LOOP]] 186; IR: UnifiedReturnBlock: 187; IR-NEXT: ret void 188entry: 189 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() 190 %cond1 = icmp eq i32 %tmp, 1 191 br i1 %cond1, label %outer_loop, label %return 192 193outer_loop: 194 ; %cond2 = icmp eq i32 %tmp, 2 195 ; br i1 %cond2, label %outer_loop, label %inner_loop 196 br label %inner_loop 197 198inner_loop: ; preds = %LeafBlock, %LeafBlock1 199 store volatile i32 999, i32 addrspace(1)* %out, align 4 200 %cond3 = icmp eq i32 %tmp, 3 201 br i1 %cond3, label %inner_loop, label %outer_loop 202 203return: 204 ret void 205} 206 207declare i32 @llvm.amdgcn.workitem.id.x() 208