1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10 %s
3
4define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) {
5; GFX10-LABEL: sample_d_1d:
6; GFX10:       ; %bb.0: ; %main_body
7; GFX10-NEXT:    image_sample_d_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
8; GFX10-NEXT:    s_waitcnt vmcnt(0)
9; GFX10-NEXT:    ; return to shader part epilog
10main_body:
11  %v = call <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
12  ret <4 x float> %v
13}
14
15define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) {
16; GFX10-LABEL: sample_d_2d:
17; GFX10:       ; %bb.0: ; %main_body
18; GFX10-NEXT:    v_mov_b32_e32 v6, 0xffff
19; GFX10-NEXT:    v_and_b32_e32 v2, v6, v2
20; GFX10-NEXT:    v_and_b32_e32 v0, v6, v0
21; GFX10-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
22; GFX10-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
23; GFX10-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
24; GFX10-NEXT:    s_waitcnt vmcnt(0)
25; GFX10-NEXT:    ; return to shader part epilog
26main_body:
27  %v = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
28  ret <4 x float> %v
29}
30
31define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, float %s, float %t, float %r) {
32; GFX10-LABEL: sample_d_3d:
33; GFX10:       ; %bb.0: ; %main_body
34; GFX10-NEXT:    v_mov_b32_e32 v9, v3
35; GFX10-NEXT:    v_mov_b32_e32 v3, v2
36; GFX10-NEXT:    v_mov_b32_e32 v2, 0xffff
37; GFX10-NEXT:    v_and_b32_e32 v9, v2, v9
38; GFX10-NEXT:    v_and_b32_e32 v0, v2, v0
39; GFX10-NEXT:    v_lshl_or_b32 v4, v4, 16, v9
40; GFX10-NEXT:    v_lshl_or_b32 v2, v1, 16, v0
41; GFX10-NEXT:    image_sample_d_g16 v[0:3], v[2:8], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
42; GFX10-NEXT:    s_waitcnt vmcnt(0)
43; GFX10-NEXT:    ; return to shader part epilog
44main_body:
45  %v = call <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, float %s, float %t, float %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
46  ret <4 x float> %v
47}
48
49define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s) {
50; GFX10-LABEL: sample_c_d_1d:
51; GFX10:       ; %bb.0: ; %main_body
52; GFX10-NEXT:    image_sample_c_d_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
53; GFX10-NEXT:    s_waitcnt vmcnt(0)
54; GFX10-NEXT:    ; return to shader part epilog
55main_body:
56  %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
57  ret <4 x float> %v
58}
59
60define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) {
61; GFX10-LABEL: sample_c_d_2d:
62; GFX10:       ; %bb.0: ; %main_body
63; GFX10-NEXT:    v_mov_b32_e32 v7, 0xffff
64; GFX10-NEXT:    v_and_b32_e32 v3, v7, v3
65; GFX10-NEXT:    v_and_b32_e32 v1, v7, v1
66; GFX10-NEXT:    v_lshl_or_b32 v3, v4, 16, v3
67; GFX10-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
68; GFX10-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v3, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
69; GFX10-NEXT:    s_waitcnt vmcnt(0)
70; GFX10-NEXT:    ; return to shader part epilog
71main_body:
72  %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
73  ret <4 x float> %v
74}
75
76define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s, float %clamp) {
77; GFX10-LABEL: sample_d_cl_1d:
78; GFX10:       ; %bb.0: ; %main_body
79; GFX10-NEXT:    image_sample_d_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
80; GFX10-NEXT:    s_waitcnt vmcnt(0)
81; GFX10-NEXT:    ; return to shader part epilog
82main_body:
83  %v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
84  ret <4 x float> %v
85}
86
87define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) {
88; GFX10-LABEL: sample_d_cl_2d:
89; GFX10:       ; %bb.0: ; %main_body
90; GFX10-NEXT:    v_mov_b32_e32 v7, 0xffff
91; GFX10-NEXT:    v_and_b32_e32 v2, v7, v2
92; GFX10-NEXT:    v_and_b32_e32 v0, v7, v0
93; GFX10-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
94; GFX10-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
95; GFX10-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
96; GFX10-NEXT:    s_waitcnt vmcnt(0)
97; GFX10-NEXT:    ; return to shader part epilog
98main_body:
99  %v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
100  ret <4 x float> %v
101}
102
103define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp) {
104; GFX10-LABEL: sample_c_d_cl_1d:
105; GFX10:       ; %bb.0: ; %main_body
106; GFX10-NEXT:    image_sample_c_d_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
107; GFX10-NEXT:    s_waitcnt vmcnt(0)
108; GFX10-NEXT:    ; return to shader part epilog
109main_body:
110  %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
111  ret <4 x float> %v
112}
113
114define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) {
115; GFX10-LABEL: sample_c_d_cl_2d:
116; GFX10:       ; %bb.0: ; %main_body
117; GFX10-NEXT:    v_mov_b32_e32 v8, v2
118; GFX10-NEXT:    v_mov_b32_e32 v2, v0
119; GFX10-NEXT:    v_mov_b32_e32 v0, 0xffff
120; GFX10-NEXT:    v_and_b32_e32 v3, v0, v3
121; GFX10-NEXT:    v_and_b32_e32 v0, v0, v1
122; GFX10-NEXT:    v_lshl_or_b32 v4, v4, 16, v3
123; GFX10-NEXT:    v_lshl_or_b32 v3, v8, 16, v0
124; GFX10-NEXT:    image_sample_c_d_cl_g16 v[0:3], v[2:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
125; GFX10-NEXT:    s_waitcnt vmcnt(0)
126; GFX10-NEXT:    ; return to shader part epilog
127main_body:
128  %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
129  ret <4 x float> %v
130}
131
132define amdgpu_ps <4 x float> @sample_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) {
133; GFX10-LABEL: sample_cd_1d:
134; GFX10:       ; %bb.0: ; %main_body
135; GFX10-NEXT:    image_sample_cd_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
136; GFX10-NEXT:    s_waitcnt vmcnt(0)
137; GFX10-NEXT:    ; return to shader part epilog
138main_body:
139  %v = call <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
140  ret <4 x float> %v
141}
142
143define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) {
144; GFX10-LABEL: sample_cd_2d:
145; GFX10:       ; %bb.0: ; %main_body
146; GFX10-NEXT:    v_mov_b32_e32 v6, 0xffff
147; GFX10-NEXT:    v_and_b32_e32 v2, v6, v2
148; GFX10-NEXT:    v_and_b32_e32 v0, v6, v0
149; GFX10-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
150; GFX10-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
151; GFX10-NEXT:    image_sample_cd_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
152; GFX10-NEXT:    s_waitcnt vmcnt(0)
153; GFX10-NEXT:    ; return to shader part epilog
154main_body:
155  %v = call <4 x float> @llvm.amdgcn.image.sample.cd.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
156  ret <4 x float> %v
157}
158
159define amdgpu_ps <4 x float> @sample_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s) {
160; GFX10-LABEL: sample_c_cd_1d:
161; GFX10:       ; %bb.0: ; %main_body
162; GFX10-NEXT:    image_sample_c_cd_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
163; GFX10-NEXT:    s_waitcnt vmcnt(0)
164; GFX10-NEXT:    ; return to shader part epilog
165main_body:
166  %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
167  ret <4 x float> %v
168}
169
170define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) {
171; GFX10-LABEL: sample_c_cd_2d:
172; GFX10:       ; %bb.0: ; %main_body
173; GFX10-NEXT:    v_mov_b32_e32 v7, 0xffff
174; GFX10-NEXT:    v_and_b32_e32 v3, v7, v3
175; GFX10-NEXT:    v_and_b32_e32 v1, v7, v1
176; GFX10-NEXT:    v_lshl_or_b32 v3, v4, 16, v3
177; GFX10-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
178; GFX10-NEXT:    image_sample_c_cd_g16 v[0:3], [v0, v1, v3, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
179; GFX10-NEXT:    s_waitcnt vmcnt(0)
180; GFX10-NEXT:    ; return to shader part epilog
181main_body:
182  %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
183  ret <4 x float> %v
184}
185
186define amdgpu_ps <4 x float> @sample_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s, float %clamp) {
187; GFX10-LABEL: sample_cd_cl_1d:
188; GFX10:       ; %bb.0: ; %main_body
189; GFX10-NEXT:    image_sample_cd_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
190; GFX10-NEXT:    s_waitcnt vmcnt(0)
191; GFX10-NEXT:    ; return to shader part epilog
192main_body:
193  %v = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
194  ret <4 x float> %v
195}
196
197define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) {
198; GFX10-LABEL: sample_cd_cl_2d:
199; GFX10:       ; %bb.0: ; %main_body
200; GFX10-NEXT:    v_mov_b32_e32 v7, 0xffff
201; GFX10-NEXT:    v_and_b32_e32 v2, v7, v2
202; GFX10-NEXT:    v_and_b32_e32 v0, v7, v0
203; GFX10-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
204; GFX10-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
205; GFX10-NEXT:    image_sample_cd_cl_g16 v[0:3], [v0, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
206; GFX10-NEXT:    s_waitcnt vmcnt(0)
207; GFX10-NEXT:    ; return to shader part epilog
208main_body:
209  %v = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
210  ret <4 x float> %v
211}
212
213define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp) {
214; GFX10-LABEL: sample_c_cd_cl_1d:
215; GFX10:       ; %bb.0: ; %main_body
216; GFX10-NEXT:    image_sample_c_cd_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
217; GFX10-NEXT:    s_waitcnt vmcnt(0)
218; GFX10-NEXT:    ; return to shader part epilog
219main_body:
220  %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
221  ret <4 x float> %v
222}
223
224define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) {
225; GFX10-LABEL: sample_c_cd_cl_2d:
226; GFX10:       ; %bb.0: ; %main_body
227; GFX10-NEXT:    v_mov_b32_e32 v8, v2
228; GFX10-NEXT:    v_mov_b32_e32 v2, v0
229; GFX10-NEXT:    v_mov_b32_e32 v0, 0xffff
230; GFX10-NEXT:    v_and_b32_e32 v3, v0, v3
231; GFX10-NEXT:    v_and_b32_e32 v0, v0, v1
232; GFX10-NEXT:    v_lshl_or_b32 v4, v4, 16, v3
233; GFX10-NEXT:    v_lshl_or_b32 v3, v8, 16, v0
234; GFX10-NEXT:    image_sample_c_cd_cl_g16 v[0:3], v[2:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
235; GFX10-NEXT:    s_waitcnt vmcnt(0)
236; GFX10-NEXT:    ; return to shader part epilog
237main_body:
238  %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
239  ret <4 x float> %v
240}
241
242define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice) {
243; GFX10-LABEL: sample_c_d_o_2darray_V1:
244; GFX10:       ; %bb.0: ; %main_body
245; GFX10-NEXT:    v_mov_b32_e32 v9, v2
246; GFX10-NEXT:    v_mov_b32_e32 v2, v0
247; GFX10-NEXT:    v_mov_b32_e32 v0, 0xffff
248; GFX10-NEXT:    v_mov_b32_e32 v10, v3
249; GFX10-NEXT:    v_mov_b32_e32 v3, v1
250; GFX10-NEXT:    v_and_b32_e32 v1, v0, v4
251; GFX10-NEXT:    v_and_b32_e32 v0, v0, v9
252; GFX10-NEXT:    v_lshl_or_b32 v5, v5, 16, v1
253; GFX10-NEXT:    v_lshl_or_b32 v4, v10, 16, v0
254; GFX10-NEXT:    image_sample_c_d_o_g16 v0, v[2:8], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
255; GFX10-NEXT:    s_waitcnt vmcnt(0)
256; GFX10-NEXT:    ; return to shader part epilog
257main_body:
258  %v = call float @llvm.amdgcn.image.sample.c.d.o.2darray.f16.f32.f32(i32 4, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
259  ret float %v
260}
261
262define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice) {
263; GFX10-LABEL: sample_c_d_o_2darray_V2:
264; GFX10:       ; %bb.0: ; %main_body
265; GFX10-NEXT:    v_mov_b32_e32 v9, v2
266; GFX10-NEXT:    v_mov_b32_e32 v2, v0
267; GFX10-NEXT:    v_mov_b32_e32 v0, 0xffff
268; GFX10-NEXT:    v_mov_b32_e32 v10, v3
269; GFX10-NEXT:    v_mov_b32_e32 v3, v1
270; GFX10-NEXT:    v_and_b32_e32 v1, v0, v4
271; GFX10-NEXT:    v_and_b32_e32 v0, v0, v9
272; GFX10-NEXT:    v_lshl_or_b32 v5, v5, 16, v1
273; GFX10-NEXT:    v_lshl_or_b32 v4, v10, 16, v0
274; GFX10-NEXT:    image_sample_c_d_o_g16 v[0:1], v[2:8], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY
275; GFX10-NEXT:    s_waitcnt vmcnt(0)
276; GFX10-NEXT:    ; return to shader part epilog
277main_body:
278  %v = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f32(i32 6, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
279  ret <2 x float> %v
280}
281
282declare <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f16.f32(i32, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
283declare <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f16.f32(i32, half, half, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
284declare <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f16.f32(i32, half, half, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
285declare <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f16.f32(i32, float, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
286declare <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f16.f32(i32, float, half, half, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
287declare <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f16.f32(i32, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
288declare <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f16.f32(i32, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
289declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f16.f32(i32, float, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
290declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f16.f32(i32, float, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
291
292declare <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f16.f32(i32, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
293declare <4 x float> @llvm.amdgcn.image.sample.cd.2d.v4f32.f16.f32(i32, half, half, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
294declare <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f16.f32(i32, float, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
295declare <4 x float> @llvm.amdgcn.image.sample.c.cd.2d.v4f32.f16.f32(i32, float, half, half, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
296declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f16.f32(i32, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
297declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.2d.v4f32.f16.f32(i32, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
298declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f16.f32(i32, float, half, half, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
299declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f16.f32(i32, float, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
300
301declare float @llvm.amdgcn.image.sample.c.d.o.2darray.f16.f32.f32(i32, i32, float, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
302declare <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f32(i32, i32, float, half, half, half, half, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
303
304attributes #0 = { nounwind }
305attributes #1 = { nounwind readonly }
306attributes #2 = { nounwind readnone }
307