1; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,CI %s
2; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI %s
3
4; GCN-LABEL: {{^}}mad_i64_i32_sextops:
5; CI: v_mad_i64_i32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
6
7; SI: v_mul_lo_u32
8; SI: v_mul_hi_i32
9; SI: v_add_i32
10; SI: v_addc_u32
11define i64 @mad_i64_i32_sextops(i32 %arg0, i32 %arg1, i64 %arg2) #0 {
12  %sext0 = sext i32 %arg0 to i64
13  %sext1 = sext i32 %arg1 to i64
14  %mul = mul i64 %sext0, %sext1
15  %mad = add i64 %mul, %arg2
16  ret i64 %mad
17}
18
19; GCN-LABEL: {{^}}mad_i64_i32_sextops_commute:
20; CI: v_mad_i64_i32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
21
22; SI-DAG: v_mul_lo_u32
23; SI-DAG: v_mul_hi_i32
24; SI: v_add_i32
25; SI: v_addc_u32
26define i64 @mad_i64_i32_sextops_commute(i32 %arg0, i32 %arg1, i64 %arg2) #0 {
27  %sext0 = sext i32 %arg0 to i64
28  %sext1 = sext i32 %arg1 to i64
29  %mul = mul i64 %sext0, %sext1
30  %mad = add i64 %arg2, %mul
31  ret i64 %mad
32}
33
34; GCN-LABEL: {{^}}mad_u64_u32_zextops:
35; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
36
37; SI-DAG: v_mul_lo_u32
38; SI-DAG: v_mul_hi_u32
39; SI: v_add_i32
40; SI: v_addc_u32
41define i64 @mad_u64_u32_zextops(i32 %arg0, i32 %arg1, i64 %arg2) #0 {
42  %sext0 = zext i32 %arg0 to i64
43  %sext1 = zext i32 %arg1 to i64
44  %mul = mul i64 %sext0, %sext1
45  %mad = add i64 %mul, %arg2
46  ret i64 %mad
47}
48
49; GCN-LABEL: {{^}}mad_u64_u32_zextops_commute:
50; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
51
52; SI-DAG: v_mul_lo_u32
53; SI-DAG: v_mul_hi_u32
54; SI: v_add_i32
55; SI: v_addc_u32
56define i64 @mad_u64_u32_zextops_commute(i32 %arg0, i32 %arg1, i64 %arg2) #0 {
57  %sext0 = zext i32 %arg0 to i64
58  %sext1 = zext i32 %arg1 to i64
59  %mul = mul i64 %sext0, %sext1
60  %mad = add i64 %arg2, %mul
61  ret i64 %mad
62}
63
64
65
66
67
68
69; GCN-LABEL: {{^}}mad_i64_i32_sextops_i32_i128:
70; CI: v_mad_u64_u32
71; CI: v_mad_u64_u32
72; CI: v_mad_i64_i32
73; CI: v_mad_u64_u32
74
75
76; SI-NOT: v_mad_
77define i128 @mad_i64_i32_sextops_i32_i128(i32 %arg0, i32 %arg1, i128 %arg2) #0 {
78  %sext0 = sext i32 %arg0 to i128
79  %sext1 = sext i32 %arg1 to i128
80  %mul = mul i128 %sext0, %sext1
81  %mad = add i128 %mul, %arg2
82  ret i128 %mad
83}
84
85; GCN-LABEL: {{^}}mad_i64_i32_sextops_i32_i63:
86; CI: v_lshl_b64
87; CI: v_ashr
88; CI: v_mad_i64_i32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
89
90; SI-NOT: v_mad_u64_u32
91define i63 @mad_i64_i32_sextops_i32_i63(i32 %arg0, i32 %arg1, i63 %arg2) #0 {
92  %sext0 = sext i32 %arg0 to i63
93  %sext1 = sext i32 %arg1 to i63
94  %mul = mul i63 %sext0, %sext1
95  %mad = add i63 %mul, %arg2
96  ret i63 %mad
97}
98
99; GCN-LABEL: {{^}}mad_i64_i32_sextops_i31_i63:
100; CI: v_lshl_b64
101; CI: v_bfe_i32 v[[B1:[0-9]+]], v1, 0, 31
102; CI: v_ashr_i64
103; CI: v_bfe_i32 v[[B2:[0-9]+]], v0, 0, 31
104; CI: v_mad_i64_i32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v[[B2]], v[[B1]], v{{\[[0-9]+:[0-9]+\]}}
105define i63 @mad_i64_i32_sextops_i31_i63(i31 %arg0, i31 %arg1, i63 %arg2) #0 {
106  %sext0 = sext i31 %arg0 to i63
107  %sext1 = sext i31 %arg1 to i63
108  %mul = mul i63 %sext0, %sext1
109  %mad = add i63 %mul, %arg2
110  ret i63 %mad
111}
112
113; GCN-LABEL: {{^}}mad_u64_u32_bitops:
114; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v2, v[4:5]
115define i64 @mad_u64_u32_bitops(i64 %arg0, i64 %arg1, i64 %arg2) #0 {
116  %trunc.lhs = and i64 %arg0, 4294967295
117  %trunc.rhs = and i64 %arg1, 4294967295
118  %mul = mul i64 %trunc.lhs, %trunc.rhs
119  %add = add i64 %mul, %arg2
120  ret i64 %add
121}
122
123; GCN-LABEL: {{^}}mad_u64_u32_bitops_lhs_mask_small:
124; GCN-NOT: v_mad_
125define i64 @mad_u64_u32_bitops_lhs_mask_small(i64 %arg0, i64 %arg1, i64 %arg2) #0 {
126  %trunc.lhs = and i64 %arg0, 8589934591
127  %trunc.rhs = and i64 %arg1, 4294967295
128  %mul = mul i64 %trunc.lhs, %trunc.rhs
129  %add = add i64 %mul, %arg2
130  ret i64 %add
131}
132
133; GCN-LABEL: {{^}}mad_u64_u32_bitops_rhs_mask_small:
134; GCN-NOT: v_mad_
135define i64 @mad_u64_u32_bitops_rhs_mask_small(i64 %arg0, i64 %arg1, i64 %arg2) #0 {
136  %trunc.lhs = and i64 %arg0, 4294967295
137  %trunc.rhs = and i64 %arg1, 8589934591
138  %mul = mul i64 %trunc.lhs, %trunc.rhs
139  %add = add i64 %mul, %arg2
140  ret i64 %add
141}
142
143; GCN-LABEL: {{^}}mad_i64_i32_bitops:
144; CI: v_mad_i64_i32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v2, v[4:5]
145; SI-NOT: v_mad_
146define i64 @mad_i64_i32_bitops(i64 %arg0, i64 %arg1, i64 %arg2) #0 {
147  %shl.lhs = shl i64 %arg0, 32
148  %trunc.lhs = ashr i64 %shl.lhs, 32
149  %shl.rhs = shl i64 %arg1, 32
150  %trunc.rhs = ashr i64 %shl.rhs, 32
151  %mul = mul i64 %trunc.lhs, %trunc.rhs
152  %add = add i64 %mul, %arg2
153  ret i64 %add
154}
155
156; Example from bug report
157; GCN-LABEL: {{^}}mad_i64_i32_unpack_i64ops:
158; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v1, v0, v[0:1]
159; SI-NOT: v_mad_u64_u32
160define i64 @mad_i64_i32_unpack_i64ops(i64 %arg0) #0 {
161  %tmp4 = lshr i64 %arg0, 32
162  %tmp5 = and i64 %arg0, 4294967295
163  %mul = mul nuw i64 %tmp4, %tmp5
164  %mad = add i64 %mul, %arg0
165  ret i64 %mad
166}
167
168attributes #0 = { nounwind }
169attributes #1 = { nounwind readnone speculatable }
170