1; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s 2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s 3 4declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 5 6; GCN-LABEL: {{^}}v_uint_to_fp_i64_to_f64 7; GCN: flat_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} 8; GCN-DAG: v_cvt_f64_u32_e32 [[HI_CONV:v\[[0-9]+:[0-9]+\]]], v[[HI]] 9; GCN-DAG: v_cvt_f64_u32_e32 [[LO_CONV:v\[[0-9]+:[0-9]+\]]], v[[LO]] 10; GCN-DAG: v_ldexp_f64 [[LDEXP:v\[[0-9]+:[0-9]+\]]], [[HI_CONV]], 32 11; GCN: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[LDEXP]], [[LO_CONV]] 12; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] 13define amdgpu_kernel void @v_uint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 addrspace(1)* %in) { 14 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 15 %gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid 16 %val = load i64, i64 addrspace(1)* %gep, align 8 17 %result = uitofp i64 %val to double 18 store double %result, double addrspace(1)* %out 19 ret void 20} 21 22; GCN-LABEL: {{^}}s_uint_to_fp_i64_to_f64 23define amdgpu_kernel void @s_uint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 %in) { 24 %cast = uitofp i64 %in to double 25 store double %cast, double addrspace(1)* %out, align 8 26 ret void 27} 28 29; GCN-LABEL: {{^}}s_uint_to_fp_v2i64_to_v2f64 30define amdgpu_kernel void @s_uint_to_fp_v2i64_to_v2f64(<2 x double> addrspace(1)* %out, <2 x i64> %in) { 31 %cast = uitofp <2 x i64> %in to <2 x double> 32 store <2 x double> %cast, <2 x double> addrspace(1)* %out, align 16 33 ret void 34} 35 36; GCN-LABEL: {{^}}s_uint_to_fp_v4i64_to_v4f64 37define amdgpu_kernel void @s_uint_to_fp_v4i64_to_v4f64(<4 x double> addrspace(1)* %out, <4 x i64> %in) { 38 %cast = uitofp <4 x i64> %in to <4 x double> 39 store <4 x double> %cast, <4 x double> addrspace(1)* %out, align 16 40 ret void 41} 42 43; GCN-LABEL: {{^}}s_uint_to_fp_i32_to_f64 44; GCN: v_cvt_f64_u32_e32 45; GCN: s_endpgm 46define amdgpu_kernel void @s_uint_to_fp_i32_to_f64(double addrspace(1)* %out, i32 %in) { 47 %cast = uitofp i32 %in to double 48 store double %cast, double addrspace(1)* %out, align 8 49 ret void 50} 51 52; GCN-LABEL: {{^}}s_uint_to_fp_v2i32_to_v2f64 53; GCN: v_cvt_f64_u32_e32 54; GCN: v_cvt_f64_u32_e32 55; GCN: s_endpgm 56define amdgpu_kernel void @s_uint_to_fp_v2i32_to_v2f64(<2 x double> addrspace(1)* %out, <2 x i32> %in) { 57 %cast = uitofp <2 x i32> %in to <2 x double> 58 store <2 x double> %cast, <2 x double> addrspace(1)* %out, align 16 59 ret void 60} 61 62; GCN-LABEL: {{^}}s_uint_to_fp_v4i32_to_v4f64 63; GCN: v_cvt_f64_u32_e32 64; GCN: v_cvt_f64_u32_e32 65; GCN: v_cvt_f64_u32_e32 66; GCN: v_cvt_f64_u32_e32 67; GCN: s_endpgm 68define amdgpu_kernel void @s_uint_to_fp_v4i32_to_v4f64(<4 x double> addrspace(1)* %out, <4 x i32> %in) { 69 %cast = uitofp <4 x i32> %in to <4 x double> 70 store <4 x double> %cast, <4 x double> addrspace(1)* %out, align 16 71 ret void 72} 73 74; We can't fold the SGPRs into v_cndmask_b32_e32, because it already 75; uses an SGPR (implicit vcc). 76 77; GCN-LABEL: {{^}}uint_to_fp_i1_to_f64: 78; VI-DAG: s_cmp_eq_u32 79; VI-DAG: s_cselect_b32 s[[SSEL:[0-9]+]], 0x3ff00000, 0 80; VI-DAG: v_mov_b32_e32 v[[SEL:[0-9]+]], s[[SSEL]] 81; SI-DAG: v_cmp_eq_u32_e64 vcc 82; SI-DAG: v_cndmask_b32_e32 v[[SEL:[0-9]+]], 0, v{{[0-9]+}} 83; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} 84; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[ZERO]]:[[SEL]]{{\]}} 85; GCN: s_endpgm 86define amdgpu_kernel void @uint_to_fp_i1_to_f64(double addrspace(1)* %out, i32 %in) { 87 %cmp = icmp eq i32 %in, 0 88 %fp = uitofp i1 %cmp to double 89 store double %fp, double addrspace(1)* %out, align 4 90 ret void 91} 92 93; GCN-LABEL: {{^}}uint_to_fp_i1_to_f64_load: 94; GCN: v_cndmask_b32_e64 [[IRESULT:v[0-9]]], 0, 1 95; GCN: v_cvt_f64_u32_e32 [[RESULT:v\[[0-9]+:[0-9]\]]], [[IRESULT]] 96; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] 97; GCN: s_endpgm 98define amdgpu_kernel void @uint_to_fp_i1_to_f64_load(double addrspace(1)* %out, i1 %in) { 99 %fp = uitofp i1 %in to double 100 store double %fp, double addrspace(1)* %out, align 8 101 ret void 102} 103 104; GCN-LABEL: {{^}}s_uint_to_fp_i8_to_f64: 105; GCN: s_load_dword [[VAL:s[0-9]+]] 106; SI: s_and_b32 [[ZEXT:s[0-9]+]], [[VAL]], 0xff{{$}} 107; SI: v_cvt_f64_u32_e32 v{{\[[0-9]+:[0-9]+\]}}, [[ZEXT]] 108 109; VI: s_and_b32 [[ZEXT:s[0-9]+]], [[VAL]], 0xff{{$}} 110; VI: v_cvt_f64_u32_e32 v{{\[[0-9]+:[0-9]+\]}}, [[ZEXT]] 111define amdgpu_kernel void @s_uint_to_fp_i8_to_f64(double addrspace(1)* %out, i8 %in) { 112 %fp = uitofp i8 %in to double 113 store double %fp, double addrspace(1)* %out 114 ret void 115} 116 117; FIXME: Worse on VI 118; GCN-LABEL: {{^}}v_uint_to_fp_i8_to_f64: 119; SI: v_and_b32_e32 [[ZEXT:v[0-9]+]], 0xff, v0 120; SI: v_cvt_f64_u32_e32 v{{\[[0-9]+:[0-9]+\]}}, [[ZEXT]] 121 122; VI: v_mov_b32_e32 v{{[0-9]+}} 123; VI: v_and_b32_sdwa 124; VI: v_cvt_f64_u32_e32 v{{\[[0-9]+:[0-9]+\]}}, 125define double @v_uint_to_fp_i8_to_f64(i8 %in) { 126 %fp = uitofp i8 %in to double 127 ret double %fp 128} 129