1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc %s -o - -mtriple=thumbv8m.main -mattr=+fp-armv8d16sp,+dsp | \
3; RUN:   FileCheck %s --check-prefix=CHECK-8M --check-prefix=CHECK-8M-LE
4; RUN: llc %s -o - -mtriple=thumbebv8m.main -mattr=+fp-armv8d16sp,+dsp | \
5; RUN:   FileCheck %s --check-prefix=CHECK-8M --check-prefix=CHECK-8M-BE
6
7; RUN: llc %s -o - -mtriple=thumbv8.1m.main -mattr=+fp-armv8d16sp,+dsp | \
8; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-LE
9; RUN: llc %s -o - -mtriple=thumbebv8.1m.main -mattr=+fp-armv8d16sp,+dsp | \
10; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-BE
11; RUN: llc %s -o - -mtriple=thumbv8.1m.main -mattr=+mve | \
12; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-LE
13; RUN: llc %s -o - -mtriple=thumbebv8.1m.main -mattr=+mve | \
14; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-BE
15
16define float @f1(float (float)* nocapture %fptr) #0 {
17; CHECK-8M-LABEL: f1:
18; CHECK-8M:       @ %bb.0: @ %entry
19; CHECK-8M-NEXT:    push {r7, lr}
20; CHECK-8M-NEXT:    mov r1, r0
21; CHECK-8M-NEXT:    movs r0, #0
22; CHECK-8M-NEXT:    movt r0, #16672
23; CHECK-8M-NEXT:    blx r1
24; CHECK-8M-NEXT:    pop.w {r7, lr}
25; CHECK-8M-NEXT:    mrs r12, control
26; CHECK-8M-NEXT:    tst.w r12, #8
27; CHECK-8M-NEXT:    beq .LBB0_2
28; CHECK-8M-NEXT:  @ %bb.1: @ %entry
29; CHECK-8M-NEXT:    vmrs r12, fpscr
30; CHECK-8M-NEXT:    vmov d0, lr, lr
31; CHECK-8M-NEXT:    vmov d1, lr, lr
32; CHECK-8M-NEXT:    vmov d2, lr, lr
33; CHECK-8M-NEXT:    vmov d3, lr, lr
34; CHECK-8M-NEXT:    vmov d4, lr, lr
35; CHECK-8M-NEXT:    vmov d5, lr, lr
36; CHECK-8M-NEXT:    vmov d6, lr, lr
37; CHECK-8M-NEXT:    vmov d7, lr, lr
38; CHECK-8M-NEXT:    bic r12, r12, #159
39; CHECK-8M-NEXT:    bic r12, r12, #4026531840
40; CHECK-8M-NEXT:    vmsr fpscr, r12
41; CHECK-8M-NEXT:  .LBB0_2: @ %entry
42; CHECK-8M-NEXT:    mov r1, lr
43; CHECK-8M-NEXT:    mov r2, lr
44; CHECK-8M-NEXT:    mov r3, lr
45; CHECK-8M-NEXT:    mov r12, lr
46; CHECK-8M-NEXT:    msr apsr_nzcvqg, lr
47; CHECK-8M-NEXT:    bxns lr
48;
49; CHECK-81M-LABEL: f1:
50; CHECK-81M:       @ %bb.0: @ %entry
51; CHECK-81M-NEXT:    vstr fpcxtns, [sp, #-4]!
52; CHECK-81M-NEXT:    push {r7, lr}
53; CHECK-81M-NEXT:    sub sp, #4
54; CHECK-81M-NEXT:    mov r1, r0
55; CHECK-81M-NEXT:    movs r0, #0
56; CHECK-81M-NEXT:    movt r0, #16672
57; CHECK-81M-NEXT:    blx r1
58; CHECK-81M-NEXT:    add sp, #4
59; CHECK-81M-NEXT:    pop.w {r7, lr}
60; CHECK-81M-NEXT:    vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
61; CHECK-81M-NEXT:    vldr fpcxtns, [sp], #4
62; CHECK-81M-NEXT:    clrm {r1, r2, r3, r12, apsr}
63; CHECK-81M-NEXT:    bxns lr
64entry:
65  %call = call float %fptr(float 10.0) #1
66  ret float %call
67}
68
69attributes #0 = { "cmse_nonsecure_entry" nounwind }
70attributes #1 = { nounwind }
71
72define double @d1(double (double)* nocapture %fptr) #0 {
73; CHECK-8M-LE-LABEL: d1:
74; CHECK-8M-LE:       @ %bb.0: @ %entry
75; CHECK-8M-LE-NEXT:    push {r7, lr}
76; CHECK-8M-LE-NEXT:    vldr d0, .LCPI1_0
77; CHECK-8M-LE-NEXT:    mov r2, r0
78; CHECK-8M-LE-NEXT:    vmov r0, r1, d0
79; CHECK-8M-LE-NEXT:    blx r2
80; CHECK-8M-LE-NEXT:    pop.w {r7, lr}
81; CHECK-8M-LE-NEXT:    mrs r12, control
82; CHECK-8M-LE-NEXT:    tst.w r12, #8
83; CHECK-8M-LE-NEXT:    beq .LBB1_2
84; CHECK-8M-LE-NEXT:  @ %bb.1: @ %entry
85; CHECK-8M-LE-NEXT:    vmrs r12, fpscr
86; CHECK-8M-LE-NEXT:    vmov d0, lr, lr
87; CHECK-8M-LE-NEXT:    vmov d1, lr, lr
88; CHECK-8M-LE-NEXT:    vmov d2, lr, lr
89; CHECK-8M-LE-NEXT:    vmov d3, lr, lr
90; CHECK-8M-LE-NEXT:    vmov d4, lr, lr
91; CHECK-8M-LE-NEXT:    vmov d5, lr, lr
92; CHECK-8M-LE-NEXT:    vmov d6, lr, lr
93; CHECK-8M-LE-NEXT:    vmov d7, lr, lr
94; CHECK-8M-LE-NEXT:    bic r12, r12, #159
95; CHECK-8M-LE-NEXT:    bic r12, r12, #4026531840
96; CHECK-8M-LE-NEXT:    vmsr fpscr, r12
97; CHECK-8M-LE-NEXT:  .LBB1_2: @ %entry
98; CHECK-8M-LE-NEXT:    mov r2, lr
99; CHECK-8M-LE-NEXT:    mov r3, lr
100; CHECK-8M-LE-NEXT:    mov r12, lr
101; CHECK-8M-LE-NEXT:    msr apsr_nzcvqg, lr
102; CHECK-8M-LE-NEXT:    bxns lr
103; CHECK-8M-LE-NEXT:    .p2align 3
104; CHECK-8M-LE-NEXT:  @ %bb.3:
105; CHECK-8M-LE-NEXT:  .LCPI1_0:
106; CHECK-8M-LE-NEXT:    .long 0 @ double 10
107; CHECK-8M-LE-NEXT:    .long 1076101120
108;
109; CHECK-8M-BE-LABEL: d1:
110; CHECK-8M-BE:       @ %bb.0: @ %entry
111; CHECK-8M-BE-NEXT:    push {r7, lr}
112; CHECK-8M-BE-NEXT:    vldr d0, .LCPI1_0
113; CHECK-8M-BE-NEXT:    mov r2, r0
114; CHECK-8M-BE-NEXT:    vmov r1, r0, d0
115; CHECK-8M-BE-NEXT:    blx r2
116; CHECK-8M-BE-NEXT:    pop.w {r7, lr}
117; CHECK-8M-BE-NEXT:    mrs r12, control
118; CHECK-8M-BE-NEXT:    tst.w r12, #8
119; CHECK-8M-BE-NEXT:    beq .LBB1_2
120; CHECK-8M-BE-NEXT:  @ %bb.1: @ %entry
121; CHECK-8M-BE-NEXT:    vmrs r12, fpscr
122; CHECK-8M-BE-NEXT:    vmov d0, lr, lr
123; CHECK-8M-BE-NEXT:    vmov d1, lr, lr
124; CHECK-8M-BE-NEXT:    vmov d2, lr, lr
125; CHECK-8M-BE-NEXT:    vmov d3, lr, lr
126; CHECK-8M-BE-NEXT:    vmov d4, lr, lr
127; CHECK-8M-BE-NEXT:    vmov d5, lr, lr
128; CHECK-8M-BE-NEXT:    vmov d6, lr, lr
129; CHECK-8M-BE-NEXT:    vmov d7, lr, lr
130; CHECK-8M-BE-NEXT:    bic r12, r12, #159
131; CHECK-8M-BE-NEXT:    bic r12, r12, #4026531840
132; CHECK-8M-BE-NEXT:    vmsr fpscr, r12
133; CHECK-8M-BE-NEXT:  .LBB1_2: @ %entry
134; CHECK-8M-BE-NEXT:    mov r2, lr
135; CHECK-8M-BE-NEXT:    mov r3, lr
136; CHECK-8M-BE-NEXT:    mov r12, lr
137; CHECK-8M-BE-NEXT:    msr apsr_nzcvqg, lr
138; CHECK-8M-BE-NEXT:    bxns lr
139; CHECK-8M-BE-NEXT:    .p2align 3
140; CHECK-8M-BE-NEXT:  @ %bb.3:
141; CHECK-8M-BE-NEXT:  .LCPI1_0:
142; CHECK-8M-BE-NEXT:    .long 1076101120 @ double 10
143; CHECK-8M-BE-NEXT:    .long 0
144;
145; CHECK-81M-LE-LABEL: d1:
146; CHECK-81M-LE:       @ %bb.0: @ %entry
147; CHECK-81M-LE-NEXT:    vstr fpcxtns, [sp, #-4]!
148; CHECK-81M-LE-NEXT:    push {r7, lr}
149; CHECK-81M-LE-NEXT:    sub sp, #4
150; CHECK-81M-LE-NEXT:    vldr d0, .LCPI1_0
151; CHECK-81M-LE-NEXT:    mov r2, r0
152; CHECK-81M-LE-NEXT:    vmov r0, r1, d0
153; CHECK-81M-LE-NEXT:    blx r2
154; CHECK-81M-LE-NEXT:    add sp, #4
155; CHECK-81M-LE-NEXT:    pop.w {r7, lr}
156; CHECK-81M-LE-NEXT:    vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
157; CHECK-81M-LE-NEXT:    vldr fpcxtns, [sp], #4
158; CHECK-81M-LE-NEXT:    clrm {r2, r3, r12, apsr}
159; CHECK-81M-LE-NEXT:    bxns lr
160; CHECK-81M-LE-NEXT:    .p2align 3
161; CHECK-81M-LE-NEXT:  @ %bb.1:
162; CHECK-81M-LE-NEXT:  .LCPI1_0:
163; CHECK-81M-LE-NEXT:    .long 0 @ double 10
164; CHECK-81M-LE-NEXT:    .long 1076101120
165;
166; CHECK-81M-BE-LABEL: d1:
167; CHECK-81M-BE:       @ %bb.0: @ %entry
168; CHECK-81M-BE-NEXT:    vstr fpcxtns, [sp, #-4]!
169; CHECK-81M-BE-NEXT:    push {r7, lr}
170; CHECK-81M-BE-NEXT:    sub sp, #4
171; CHECK-81M-BE-NEXT:    vldr d0, .LCPI1_0
172; CHECK-81M-BE-NEXT:    mov r2, r0
173; CHECK-81M-BE-NEXT:    vmov r1, r0, d0
174; CHECK-81M-BE-NEXT:    blx r2
175; CHECK-81M-BE-NEXT:    add sp, #4
176; CHECK-81M-BE-NEXT:    pop.w {r7, lr}
177; CHECK-81M-BE-NEXT:    vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
178; CHECK-81M-BE-NEXT:    vldr fpcxtns, [sp], #4
179; CHECK-81M-BE-NEXT:    clrm {r2, r3, r12, apsr}
180; CHECK-81M-BE-NEXT:    bxns lr
181; CHECK-81M-BE-NEXT:    .p2align 3
182; CHECK-81M-BE-NEXT:  @ %bb.1:
183; CHECK-81M-BE-NEXT:  .LCPI1_0:
184; CHECK-81M-BE-NEXT:    .long 1076101120 @ double 10
185; CHECK-81M-BE-NEXT:    .long 0
186entry:
187  %call = call double %fptr(double 10.0) #1
188  ret double %call
189}
190
191define float @f2(float (float)* nocapture %fptr) #2 {
192; CHECK-8M-LABEL: f2:
193; CHECK-8M:       @ %bb.0: @ %entry
194; CHECK-8M-NEXT:    push {r7, lr}
195; CHECK-8M-NEXT:    mov r1, r0
196; CHECK-8M-NEXT:    movs r0, #0
197; CHECK-8M-NEXT:    movt r0, #16672
198; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
199; CHECK-8M-NEXT:    bic r1, r1, #1
200; CHECK-8M-NEXT:    sub sp, #136
201; CHECK-8M-NEXT:    vlstm sp
202; CHECK-8M-NEXT:    mov r2, r1
203; CHECK-8M-NEXT:    mov r3, r1
204; CHECK-8M-NEXT:    mov r4, r1
205; CHECK-8M-NEXT:    mov r5, r1
206; CHECK-8M-NEXT:    mov r6, r1
207; CHECK-8M-NEXT:    mov r7, r1
208; CHECK-8M-NEXT:    mov r8, r1
209; CHECK-8M-NEXT:    mov r9, r1
210; CHECK-8M-NEXT:    mov r10, r1
211; CHECK-8M-NEXT:    mov r11, r1
212; CHECK-8M-NEXT:    mov r12, r1
213; CHECK-8M-NEXT:    msr apsr_nzcvqg, r1
214; CHECK-8M-NEXT:    blxns r1
215; CHECK-8M-NEXT:    vlldm sp
216; CHECK-8M-NEXT:    add sp, #136
217; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
218; CHECK-8M-NEXT:    pop {r7, pc}
219;
220; CHECK-81M-LABEL: f2:
221; CHECK-81M:       @ %bb.0: @ %entry
222; CHECK-81M-NEXT:    push {r7, lr}
223; CHECK-81M-NEXT:    mov r1, r0
224; CHECK-81M-NEXT:    movs r0, #0
225; CHECK-81M-NEXT:    movt r0, #16672
226; CHECK-81M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
227; CHECK-81M-NEXT:    bic r1, r1, #1
228; CHECK-81M-NEXT:    sub sp, #136
229; CHECK-81M-NEXT:    vlstm sp
230; CHECK-81M-NEXT:    clrm {r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
231; CHECK-81M-NEXT:    blxns r1
232; CHECK-81M-NEXT:    vlldm sp
233; CHECK-81M-NEXT:    add sp, #136
234; CHECK-81M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
235; CHECK-81M-NEXT:    pop {r7, pc}
236entry:
237  %call = call float %fptr(float 10.0) #3
238  ret float %call
239}
240
241attributes #2 = { nounwind }
242attributes #3 = { "cmse_nonsecure_call" nounwind }
243
244define double @d2(double (double)* nocapture %fptr) #2 {
245; CHECK-8M-LE-LABEL: d2:
246; CHECK-8M-LE:       @ %bb.0: @ %entry
247; CHECK-8M-LE-NEXT:    push {r7, lr}
248; CHECK-8M-LE-NEXT:    vldr d0, .LCPI3_0
249; CHECK-8M-LE-NEXT:    mov r2, r0
250; CHECK-8M-LE-NEXT:    vmov r0, r1, d0
251; CHECK-8M-LE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
252; CHECK-8M-LE-NEXT:    bic r2, r2, #1
253; CHECK-8M-LE-NEXT:    sub sp, #136
254; CHECK-8M-LE-NEXT:    vlstm sp
255; CHECK-8M-LE-NEXT:    mov r3, r2
256; CHECK-8M-LE-NEXT:    mov r4, r2
257; CHECK-8M-LE-NEXT:    mov r5, r2
258; CHECK-8M-LE-NEXT:    mov r6, r2
259; CHECK-8M-LE-NEXT:    mov r7, r2
260; CHECK-8M-LE-NEXT:    mov r8, r2
261; CHECK-8M-LE-NEXT:    mov r9, r2
262; CHECK-8M-LE-NEXT:    mov r10, r2
263; CHECK-8M-LE-NEXT:    mov r11, r2
264; CHECK-8M-LE-NEXT:    mov r12, r2
265; CHECK-8M-LE-NEXT:    msr apsr_nzcvqg, r2
266; CHECK-8M-LE-NEXT:    blxns r2
267; CHECK-8M-LE-NEXT:    vlldm sp
268; CHECK-8M-LE-NEXT:    add sp, #136
269; CHECK-8M-LE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
270; CHECK-8M-LE-NEXT:    pop {r7, pc}
271; CHECK-8M-LE-NEXT:    .p2align 3
272; CHECK-8M-LE-NEXT:  @ %bb.1:
273; CHECK-8M-LE-NEXT:  .LCPI3_0:
274; CHECK-8M-LE-NEXT:    .long 0 @ double 10
275; CHECK-8M-LE-NEXT:    .long 1076101120
276;
277; CHECK-8M-BE-LABEL: d2:
278; CHECK-8M-BE:       @ %bb.0: @ %entry
279; CHECK-8M-BE-NEXT:    push {r7, lr}
280; CHECK-8M-BE-NEXT:    vldr d0, .LCPI3_0
281; CHECK-8M-BE-NEXT:    mov r2, r0
282; CHECK-8M-BE-NEXT:    vmov r1, r0, d0
283; CHECK-8M-BE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
284; CHECK-8M-BE-NEXT:    bic r2, r2, #1
285; CHECK-8M-BE-NEXT:    sub sp, #136
286; CHECK-8M-BE-NEXT:    vlstm sp
287; CHECK-8M-BE-NEXT:    mov r3, r2
288; CHECK-8M-BE-NEXT:    mov r4, r2
289; CHECK-8M-BE-NEXT:    mov r5, r2
290; CHECK-8M-BE-NEXT:    mov r6, r2
291; CHECK-8M-BE-NEXT:    mov r7, r2
292; CHECK-8M-BE-NEXT:    mov r8, r2
293; CHECK-8M-BE-NEXT:    mov r9, r2
294; CHECK-8M-BE-NEXT:    mov r10, r2
295; CHECK-8M-BE-NEXT:    mov r11, r2
296; CHECK-8M-BE-NEXT:    mov r12, r2
297; CHECK-8M-BE-NEXT:    msr apsr_nzcvqg, r2
298; CHECK-8M-BE-NEXT:    blxns r2
299; CHECK-8M-BE-NEXT:    vlldm sp
300; CHECK-8M-BE-NEXT:    add sp, #136
301; CHECK-8M-BE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
302; CHECK-8M-BE-NEXT:    pop {r7, pc}
303; CHECK-8M-BE-NEXT:    .p2align 3
304; CHECK-8M-BE-NEXT:  @ %bb.1:
305; CHECK-8M-BE-NEXT:  .LCPI3_0:
306; CHECK-8M-BE-NEXT:    .long 1076101120 @ double 10
307; CHECK-8M-BE-NEXT:    .long 0
308;
309; CHECK-81M-LE-LABEL: d2:
310; CHECK-81M-LE:       @ %bb.0: @ %entry
311; CHECK-81M-LE-NEXT:    push {r7, lr}
312; CHECK-81M-LE-NEXT:    vldr d0, .LCPI3_0
313; CHECK-81M-LE-NEXT:    mov r2, r0
314; CHECK-81M-LE-NEXT:    vmov r0, r1, d0
315; CHECK-81M-LE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
316; CHECK-81M-LE-NEXT:    bic r2, r2, #1
317; CHECK-81M-LE-NEXT:    sub sp, #136
318; CHECK-81M-LE-NEXT:    vlstm sp
319; CHECK-81M-LE-NEXT:    clrm {r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
320; CHECK-81M-LE-NEXT:    blxns r2
321; CHECK-81M-LE-NEXT:    vlldm sp
322; CHECK-81M-LE-NEXT:    add sp, #136
323; CHECK-81M-LE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
324; CHECK-81M-LE-NEXT:    pop {r7, pc}
325; CHECK-81M-LE-NEXT:    .p2align 3
326; CHECK-81M-LE-NEXT:  @ %bb.1:
327; CHECK-81M-LE-NEXT:  .LCPI3_0:
328; CHECK-81M-LE-NEXT:    .long 0 @ double 10
329; CHECK-81M-LE-NEXT:    .long 1076101120
330;
331; CHECK-81M-BE-LABEL: d2:
332; CHECK-81M-BE:       @ %bb.0: @ %entry
333; CHECK-81M-BE-NEXT:    push {r7, lr}
334; CHECK-81M-BE-NEXT:    vldr d0, .LCPI3_0
335; CHECK-81M-BE-NEXT:    mov r2, r0
336; CHECK-81M-BE-NEXT:    vmov r1, r0, d0
337; CHECK-81M-BE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
338; CHECK-81M-BE-NEXT:    bic r2, r2, #1
339; CHECK-81M-BE-NEXT:    sub sp, #136
340; CHECK-81M-BE-NEXT:    vlstm sp
341; CHECK-81M-BE-NEXT:    clrm {r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
342; CHECK-81M-BE-NEXT:    blxns r2
343; CHECK-81M-BE-NEXT:    vlldm sp
344; CHECK-81M-BE-NEXT:    add sp, #136
345; CHECK-81M-BE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
346; CHECK-81M-BE-NEXT:    pop {r7, pc}
347; CHECK-81M-BE-NEXT:    .p2align 3
348; CHECK-81M-BE-NEXT:  @ %bb.1:
349; CHECK-81M-BE-NEXT:  .LCPI3_0:
350; CHECK-81M-BE-NEXT:    .long 1076101120 @ double 10
351; CHECK-81M-BE-NEXT:    .long 0
352entry:
353  %call = call double %fptr(double 10.0) #3
354  ret double %call
355}
356
357define float @f3(float (float)* nocapture %fptr) #4 {
358; CHECK-8M-LABEL: f3:
359; CHECK-8M:       @ %bb.0: @ %entry
360; CHECK-8M-NEXT:    push {r7, lr}
361; CHECK-8M-NEXT:    mov r1, r0
362; CHECK-8M-NEXT:    movs r0, #0
363; CHECK-8M-NEXT:    movt r0, #16672
364; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
365; CHECK-8M-NEXT:    bic r1, r1, #1
366; CHECK-8M-NEXT:    sub sp, #136
367; CHECK-8M-NEXT:    vlstm sp
368; CHECK-8M-NEXT:    mov r2, r1
369; CHECK-8M-NEXT:    mov r3, r1
370; CHECK-8M-NEXT:    mov r4, r1
371; CHECK-8M-NEXT:    mov r5, r1
372; CHECK-8M-NEXT:    mov r6, r1
373; CHECK-8M-NEXT:    mov r7, r1
374; CHECK-8M-NEXT:    mov r8, r1
375; CHECK-8M-NEXT:    mov r9, r1
376; CHECK-8M-NEXT:    mov r10, r1
377; CHECK-8M-NEXT:    mov r11, r1
378; CHECK-8M-NEXT:    mov r12, r1
379; CHECK-8M-NEXT:    msr apsr_nzcvqg, r1
380; CHECK-8M-NEXT:    blxns r1
381; CHECK-8M-NEXT:    vlldm sp
382; CHECK-8M-NEXT:    add sp, #136
383; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
384; CHECK-8M-NEXT:    pop {r7, pc}
385;
386; CHECK-81M-LABEL: f3:
387; CHECK-81M:       @ %bb.0: @ %entry
388; CHECK-81M-NEXT:    push {r7, lr}
389; CHECK-81M-NEXT:    mov r1, r0
390; CHECK-81M-NEXT:    movs r0, #0
391; CHECK-81M-NEXT:    movt r0, #16672
392; CHECK-81M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
393; CHECK-81M-NEXT:    bic r1, r1, #1
394; CHECK-81M-NEXT:    sub sp, #136
395; CHECK-81M-NEXT:    vlstm sp
396; CHECK-81M-NEXT:    clrm {r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
397; CHECK-81M-NEXT:    blxns r1
398; CHECK-81M-NEXT:    vlldm sp
399; CHECK-81M-NEXT:    add sp, #136
400; CHECK-81M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
401; CHECK-81M-NEXT:    pop {r7, pc}
402entry:
403  %call = tail call float %fptr(float 10.0) #5
404  ret float %call
405}
406
407attributes #4 = { nounwind }
408attributes #5 = { "cmse_nonsecure_call" nounwind }
409
410define double @d3(double (double)* nocapture %fptr) #4 {
411; CHECK-8M-LE-LABEL: d3:
412; CHECK-8M-LE:       @ %bb.0: @ %entry
413; CHECK-8M-LE-NEXT:    push {r7, lr}
414; CHECK-8M-LE-NEXT:    vldr d0, .LCPI5_0
415; CHECK-8M-LE-NEXT:    mov r2, r0
416; CHECK-8M-LE-NEXT:    vmov r0, r1, d0
417; CHECK-8M-LE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
418; CHECK-8M-LE-NEXT:    bic r2, r2, #1
419; CHECK-8M-LE-NEXT:    sub sp, #136
420; CHECK-8M-LE-NEXT:    vlstm sp
421; CHECK-8M-LE-NEXT:    mov r3, r2
422; CHECK-8M-LE-NEXT:    mov r4, r2
423; CHECK-8M-LE-NEXT:    mov r5, r2
424; CHECK-8M-LE-NEXT:    mov r6, r2
425; CHECK-8M-LE-NEXT:    mov r7, r2
426; CHECK-8M-LE-NEXT:    mov r8, r2
427; CHECK-8M-LE-NEXT:    mov r9, r2
428; CHECK-8M-LE-NEXT:    mov r10, r2
429; CHECK-8M-LE-NEXT:    mov r11, r2
430; CHECK-8M-LE-NEXT:    mov r12, r2
431; CHECK-8M-LE-NEXT:    msr apsr_nzcvqg, r2
432; CHECK-8M-LE-NEXT:    blxns r2
433; CHECK-8M-LE-NEXT:    vlldm sp
434; CHECK-8M-LE-NEXT:    add sp, #136
435; CHECK-8M-LE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
436; CHECK-8M-LE-NEXT:    pop {r7, pc}
437; CHECK-8M-LE-NEXT:    .p2align 3
438; CHECK-8M-LE-NEXT:  @ %bb.1:
439; CHECK-8M-LE-NEXT:  .LCPI5_0:
440; CHECK-8M-LE-NEXT:    .long 0 @ double 10
441; CHECK-8M-LE-NEXT:    .long 1076101120
442;
443; CHECK-8M-BE-LABEL: d3:
444; CHECK-8M-BE:       @ %bb.0: @ %entry
445; CHECK-8M-BE-NEXT:    push {r7, lr}
446; CHECK-8M-BE-NEXT:    vldr d0, .LCPI5_0
447; CHECK-8M-BE-NEXT:    mov r2, r0
448; CHECK-8M-BE-NEXT:    vmov r1, r0, d0
449; CHECK-8M-BE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
450; CHECK-8M-BE-NEXT:    bic r2, r2, #1
451; CHECK-8M-BE-NEXT:    sub sp, #136
452; CHECK-8M-BE-NEXT:    vlstm sp
453; CHECK-8M-BE-NEXT:    mov r3, r2
454; CHECK-8M-BE-NEXT:    mov r4, r2
455; CHECK-8M-BE-NEXT:    mov r5, r2
456; CHECK-8M-BE-NEXT:    mov r6, r2
457; CHECK-8M-BE-NEXT:    mov r7, r2
458; CHECK-8M-BE-NEXT:    mov r8, r2
459; CHECK-8M-BE-NEXT:    mov r9, r2
460; CHECK-8M-BE-NEXT:    mov r10, r2
461; CHECK-8M-BE-NEXT:    mov r11, r2
462; CHECK-8M-BE-NEXT:    mov r12, r2
463; CHECK-8M-BE-NEXT:    msr apsr_nzcvqg, r2
464; CHECK-8M-BE-NEXT:    blxns r2
465; CHECK-8M-BE-NEXT:    vlldm sp
466; CHECK-8M-BE-NEXT:    add sp, #136
467; CHECK-8M-BE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
468; CHECK-8M-BE-NEXT:    pop {r7, pc}
469; CHECK-8M-BE-NEXT:    .p2align 3
470; CHECK-8M-BE-NEXT:  @ %bb.1:
471; CHECK-8M-BE-NEXT:  .LCPI5_0:
472; CHECK-8M-BE-NEXT:    .long 1076101120 @ double 10
473; CHECK-8M-BE-NEXT:    .long 0
474;
475; CHECK-81M-LE-LABEL: d3:
476; CHECK-81M-LE:       @ %bb.0: @ %entry
477; CHECK-81M-LE-NEXT:    push {r7, lr}
478; CHECK-81M-LE-NEXT:    vldr d0, .LCPI5_0
479; CHECK-81M-LE-NEXT:    mov r2, r0
480; CHECK-81M-LE-NEXT:    vmov r0, r1, d0
481; CHECK-81M-LE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
482; CHECK-81M-LE-NEXT:    bic r2, r2, #1
483; CHECK-81M-LE-NEXT:    sub sp, #136
484; CHECK-81M-LE-NEXT:    vlstm sp
485; CHECK-81M-LE-NEXT:    clrm {r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
486; CHECK-81M-LE-NEXT:    blxns r2
487; CHECK-81M-LE-NEXT:    vlldm sp
488; CHECK-81M-LE-NEXT:    add sp, #136
489; CHECK-81M-LE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
490; CHECK-81M-LE-NEXT:    pop {r7, pc}
491; CHECK-81M-LE-NEXT:    .p2align 3
492; CHECK-81M-LE-NEXT:  @ %bb.1:
493; CHECK-81M-LE-NEXT:  .LCPI5_0:
494; CHECK-81M-LE-NEXT:    .long 0 @ double 10
495; CHECK-81M-LE-NEXT:    .long 1076101120
496;
497; CHECK-81M-BE-LABEL: d3:
498; CHECK-81M-BE:       @ %bb.0: @ %entry
499; CHECK-81M-BE-NEXT:    push {r7, lr}
500; CHECK-81M-BE-NEXT:    vldr d0, .LCPI5_0
501; CHECK-81M-BE-NEXT:    mov r2, r0
502; CHECK-81M-BE-NEXT:    vmov r1, r0, d0
503; CHECK-81M-BE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
504; CHECK-81M-BE-NEXT:    bic r2, r2, #1
505; CHECK-81M-BE-NEXT:    sub sp, #136
506; CHECK-81M-BE-NEXT:    vlstm sp
507; CHECK-81M-BE-NEXT:    clrm {r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
508; CHECK-81M-BE-NEXT:    blxns r2
509; CHECK-81M-BE-NEXT:    vlldm sp
510; CHECK-81M-BE-NEXT:    add sp, #136
511; CHECK-81M-BE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
512; CHECK-81M-BE-NEXT:    pop {r7, pc}
513; CHECK-81M-BE-NEXT:    .p2align 3
514; CHECK-81M-BE-NEXT:  @ %bb.1:
515; CHECK-81M-BE-NEXT:  .LCPI5_0:
516; CHECK-81M-BE-NEXT:    .long 1076101120 @ double 10
517; CHECK-81M-BE-NEXT:    .long 0
518entry:
519  %call = tail call double %fptr(double 10.0) #5
520  ret double %call
521}
522
523define float @f4(float ()* nocapture %fptr) #6 {
524; CHECK-8M-LABEL: f4:
525; CHECK-8M:       @ %bb.0: @ %entry
526; CHECK-8M-NEXT:    push {r7, lr}
527; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
528; CHECK-8M-NEXT:    bic r0, r0, #1
529; CHECK-8M-NEXT:    sub sp, #136
530; CHECK-8M-NEXT:    vlstm sp
531; CHECK-8M-NEXT:    mov r1, r0
532; CHECK-8M-NEXT:    mov r2, r0
533; CHECK-8M-NEXT:    mov r3, r0
534; CHECK-8M-NEXT:    mov r4, r0
535; CHECK-8M-NEXT:    mov r5, r0
536; CHECK-8M-NEXT:    mov r6, r0
537; CHECK-8M-NEXT:    mov r7, r0
538; CHECK-8M-NEXT:    mov r8, r0
539; CHECK-8M-NEXT:    mov r9, r0
540; CHECK-8M-NEXT:    mov r10, r0
541; CHECK-8M-NEXT:    mov r11, r0
542; CHECK-8M-NEXT:    mov r12, r0
543; CHECK-8M-NEXT:    msr apsr_nzcvqg, r0
544; CHECK-8M-NEXT:    blxns r0
545; CHECK-8M-NEXT:    vlldm sp
546; CHECK-8M-NEXT:    add sp, #136
547; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
548; CHECK-8M-NEXT:    pop {r7, pc}
549;
550; CHECK-81M-LABEL: f4:
551; CHECK-81M:       @ %bb.0: @ %entry
552; CHECK-81M-NEXT:    push {r7, lr}
553; CHECK-81M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
554; CHECK-81M-NEXT:    bic r0, r0, #1
555; CHECK-81M-NEXT:    sub sp, #136
556; CHECK-81M-NEXT:    vlstm sp
557; CHECK-81M-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
558; CHECK-81M-NEXT:    blxns r0
559; CHECK-81M-NEXT:    vlldm sp
560; CHECK-81M-NEXT:    add sp, #136
561; CHECK-81M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
562; CHECK-81M-NEXT:    pop {r7, pc}
563entry:
564  %call = call float %fptr() #7
565  ret float %call
566}
567
568attributes #6 = { nounwind }
569attributes #7 = { "cmse_nonsecure_call" nounwind }
570
571define double @d4(double ()* nocapture %fptr) #6 {
572; CHECK-8M-LABEL: d4:
573; CHECK-8M:       @ %bb.0: @ %entry
574; CHECK-8M-NEXT:    push {r7, lr}
575; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
576; CHECK-8M-NEXT:    bic r0, r0, #1
577; CHECK-8M-NEXT:    sub sp, #136
578; CHECK-8M-NEXT:    vlstm sp
579; CHECK-8M-NEXT:    mov r1, r0
580; CHECK-8M-NEXT:    mov r2, r0
581; CHECK-8M-NEXT:    mov r3, r0
582; CHECK-8M-NEXT:    mov r4, r0
583; CHECK-8M-NEXT:    mov r5, r0
584; CHECK-8M-NEXT:    mov r6, r0
585; CHECK-8M-NEXT:    mov r7, r0
586; CHECK-8M-NEXT:    mov r8, r0
587; CHECK-8M-NEXT:    mov r9, r0
588; CHECK-8M-NEXT:    mov r10, r0
589; CHECK-8M-NEXT:    mov r11, r0
590; CHECK-8M-NEXT:    mov r12, r0
591; CHECK-8M-NEXT:    msr apsr_nzcvqg, r0
592; CHECK-8M-NEXT:    blxns r0
593; CHECK-8M-NEXT:    vlldm sp
594; CHECK-8M-NEXT:    add sp, #136
595; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
596; CHECK-8M-NEXT:    pop {r7, pc}
597;
598; CHECK-81M-LABEL: d4:
599; CHECK-81M:       @ %bb.0: @ %entry
600; CHECK-81M-NEXT:    push {r7, lr}
601; CHECK-81M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
602; CHECK-81M-NEXT:    bic r0, r0, #1
603; CHECK-81M-NEXT:    sub sp, #136
604; CHECK-81M-NEXT:    vlstm sp
605; CHECK-81M-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
606; CHECK-81M-NEXT:    blxns r0
607; CHECK-81M-NEXT:    vlldm sp
608; CHECK-81M-NEXT:    add sp, #136
609; CHECK-81M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
610; CHECK-81M-NEXT:    pop {r7, pc}
611entry:
612  %call = call double %fptr() #7
613  ret double %call
614}
615
616define void @fd(void (float, double)* %f, float %a, double %b) #8 {
617; CHECK-8M-LABEL: fd:
618; CHECK-8M:       @ %bb.0: @ %entry
619; CHECK-8M-NEXT:    push {r7, lr}
620; CHECK-8M-NEXT:    mov r12, r0
621; CHECK-8M-NEXT:    mov r0, r1
622; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
623; CHECK-8M-NEXT:    bic r12, r12, #1
624; CHECK-8M-NEXT:    sub sp, #136
625; CHECK-8M-NEXT:    vlstm sp
626; CHECK-8M-NEXT:    mov r1, r12
627; CHECK-8M-NEXT:    mov r4, r12
628; CHECK-8M-NEXT:    mov r5, r12
629; CHECK-8M-NEXT:    mov r6, r12
630; CHECK-8M-NEXT:    mov r7, r12
631; CHECK-8M-NEXT:    mov r8, r12
632; CHECK-8M-NEXT:    mov r9, r12
633; CHECK-8M-NEXT:    mov r10, r12
634; CHECK-8M-NEXT:    mov r11, r12
635; CHECK-8M-NEXT:    msr apsr_nzcvqg, r12
636; CHECK-8M-NEXT:    blxns r12
637; CHECK-8M-NEXT:    vlldm sp
638; CHECK-8M-NEXT:    add sp, #136
639; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
640; CHECK-8M-NEXT:    pop {r7, pc}
641;
642; CHECK-81M-LABEL: fd:
643; CHECK-81M:       @ %bb.0: @ %entry
644; CHECK-81M-NEXT:    push {r7, lr}
645; CHECK-81M-NEXT:    mov r12, r0
646; CHECK-81M-NEXT:    mov r0, r1
647; CHECK-81M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
648; CHECK-81M-NEXT:    bic r12, r12, #1
649; CHECK-81M-NEXT:    sub sp, #136
650; CHECK-81M-NEXT:    vlstm sp
651; CHECK-81M-NEXT:    clrm {r1, r4, r5, r6, r7, r8, r9, r10, r11, apsr}
652; CHECK-81M-NEXT:    blxns r12
653; CHECK-81M-NEXT:    vlldm sp
654; CHECK-81M-NEXT:    add sp, #136
655; CHECK-81M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
656; CHECK-81M-NEXT:    pop {r7, pc}
657entry:
658  call void %f(float %a, double %b) #9
659  ret void
660}
661
662attributes #8 = { nounwind }
663attributes #9 = { "cmse_nonsecure_call" nounwind }
664
665define float @f1_minsize(float (float)* nocapture %fptr) #10 {
666; CHECK-8M-LABEL: f1_minsize:
667; CHECK-8M:       @ %bb.0: @ %entry
668; CHECK-8M-NEXT:    push {r7, lr}
669; CHECK-8M-NEXT:    mov r1, r0
670; CHECK-8M-NEXT:    ldr r0, .LCPI9_0
671; CHECK-8M-NEXT:    blx r1
672; CHECK-8M-NEXT:    pop.w {r7, lr}
673; CHECK-8M-NEXT:    vmrs r12, fpscr
674; CHECK-8M-NEXT:    vmov d0, lr, lr
675; CHECK-8M-NEXT:    vmov d1, lr, lr
676; CHECK-8M-NEXT:    mov r1, lr
677; CHECK-8M-NEXT:    vmov d2, lr, lr
678; CHECK-8M-NEXT:    mov r2, lr
679; CHECK-8M-NEXT:    vmov d3, lr, lr
680; CHECK-8M-NEXT:    mov r3, lr
681; CHECK-8M-NEXT:    vmov d4, lr, lr
682; CHECK-8M-NEXT:    vmov d5, lr, lr
683; CHECK-8M-NEXT:    vmov d6, lr, lr
684; CHECK-8M-NEXT:    vmov d7, lr, lr
685; CHECK-8M-NEXT:    bic r12, r12, #159
686; CHECK-8M-NEXT:    bic r12, r12, #4026531840
687; CHECK-8M-NEXT:    vmsr fpscr, r12
688; CHECK-8M-NEXT:    mov r12, lr
689; CHECK-8M-NEXT:    msr apsr_nzcvqg, lr
690; CHECK-8M-NEXT:    bxns lr
691; CHECK-8M-NEXT:    .p2align 2
692; CHECK-8M-NEXT:  @ %bb.1:
693; CHECK-8M-NEXT:  .LCPI9_0:
694; CHECK-8M-NEXT:    .long 1092616192 @ 0x41200000
695;
696; CHECK-81M-LABEL: f1_minsize:
697; CHECK-81M:       @ %bb.0: @ %entry
698; CHECK-81M-NEXT:    vstr fpcxtns, [sp, #-4]!
699; CHECK-81M-NEXT:    push {r6, r7, lr}
700; CHECK-81M-NEXT:    mov r1, r0
701; CHECK-81M-NEXT:    ldr r0, .LCPI9_0
702; CHECK-81M-NEXT:    blx r1
703; CHECK-81M-NEXT:    pop.w {r3, r7, lr}
704; CHECK-81M-NEXT:    vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
705; CHECK-81M-NEXT:    vldr fpcxtns, [sp], #4
706; CHECK-81M-NEXT:    clrm {r1, r2, r3, r12, apsr}
707; CHECK-81M-NEXT:    bxns lr
708; CHECK-81M-NEXT:    .p2align 2
709; CHECK-81M-NEXT:  @ %bb.1:
710; CHECK-81M-NEXT:  .LCPI9_0:
711; CHECK-81M-NEXT:    .long 1092616192 @ 0x41200000
712entry:
713  %call = call float %fptr(float 10.0) #11
714  ret float %call
715}
716
717attributes #10 = { "cmse_nonsecure_entry" minsize nounwind }
718attributes #11 = { nounwind }
719