1; Test the MSA intrinsics that are encoded with the I5 instruction format. 2; There are lots of these so this covers those beginning with 'c' 3 4; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s 5; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s 6 7@llvm_mips_ceqi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 8@llvm_mips_ceqi_b_RES1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 9@llvm_mips_ceqi_b_RES2 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 10 11define void @llvm_mips_ceqi_b_test() nounwind { 12entry: 13 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_ceqi_b_ARG1 14 %1 = tail call <16 x i8> @llvm.mips.ceqi.b(<16 x i8> %0, i32 14) 15 store <16 x i8> %1, <16 x i8>* @llvm_mips_ceqi_b_RES1 16 %2 = tail call <16 x i8> @llvm.mips.ceqi.b(<16 x i8> %0, i32 -14) 17 store <16 x i8> %2, <16 x i8>* @llvm_mips_ceqi_b_RES2 18 ret void 19} 20 21declare <16 x i8> @llvm.mips.ceqi.b(<16 x i8>, i32) nounwind 22 23; CHECK: llvm_mips_ceqi_b_test: 24; CHECK: ld.b [[RS:\$w[0-9]+]] 25; CHECK: ceqi.b [[RD1:\$w[0-9]]], [[RS]], 14 26; CHECK: st.b [[RD1]] 27; CHECK: ceqi.b [[RD2:\$w[0-9]]], [[RS]], -14 28; CHECK: st.b [[RD2]] 29; CHECK: .size llvm_mips_ceqi_b_test 30; 31@llvm_mips_ceqi_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 32@llvm_mips_ceqi_h_RES1 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 33@llvm_mips_ceqi_h_RES2 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 34 35define void @llvm_mips_ceqi_h_test() nounwind { 36entry: 37 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_ceqi_h_ARG1 38 %1 = tail call <8 x i16> @llvm.mips.ceqi.h(<8 x i16> %0, i32 14) 39 store <8 x i16> %1, <8 x i16>* @llvm_mips_ceqi_h_RES1 40 %2 = tail call <8 x i16> @llvm.mips.ceqi.h(<8 x i16> %0, i32 -14) 41 store <8 x i16> %2, <8 x i16>* @llvm_mips_ceqi_h_RES2 42 ret void 43} 44 45declare <8 x i16> @llvm.mips.ceqi.h(<8 x i16>, i32) nounwind 46 47; CHECK: llvm_mips_ceqi_h_test: 48; CHECK: ld.h [[RS:\$w[0-9]+]] 49; CHECK: ceqi.h [[RD1:\$w[0-9]]], [[RS]], 14 50; CHECK: st.h [[RD1]] 51; CHECK: ceqi.h [[RD2:\$w[0-9]]], [[RS]], -14 52; CHECK: st.h [[RD2]] 53; CHECK: .size llvm_mips_ceqi_h_test 54; 55@llvm_mips_ceqi_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 56@llvm_mips_ceqi_w_RES1 = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 57@llvm_mips_ceqi_w_RES2 = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 58 59define void @llvm_mips_ceqi_w_test() nounwind { 60entry: 61 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_ceqi_w_ARG1 62 %1 = tail call <4 x i32> @llvm.mips.ceqi.w(<4 x i32> %0, i32 14) 63 store <4 x i32> %1, <4 x i32>* @llvm_mips_ceqi_w_RES1 64 %2 = tail call <4 x i32> @llvm.mips.ceqi.w(<4 x i32> %0, i32 -14) 65 store <4 x i32> %2, <4 x i32>* @llvm_mips_ceqi_w_RES2 66 ret void 67} 68 69declare <4 x i32> @llvm.mips.ceqi.w(<4 x i32>, i32) nounwind 70 71; CHECK: llvm_mips_ceqi_w_test: 72; CHECK: ld.w [[RS:\$w[0-9]+]] 73; CHECK: ceqi.w [[RD1:\$w[0-9]]], [[RS]], 14 74; CHECK: st.w [[RD1]] 75; CHECK: ceqi.w [[RD2:\$w[0-9]]], [[RS]], -14 76; CHECK: st.w [[RD2]] 77; CHECK: .size llvm_mips_ceqi_w_test 78; 79@llvm_mips_ceqi_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 80@llvm_mips_ceqi_d_RES1 = global <2 x i64> <i64 0, i64 0>, align 16 81@llvm_mips_ceqi_d_RES2 = global <2 x i64> <i64 0, i64 0>, align 16 82 83define void @llvm_mips_ceqi_d_test() nounwind { 84entry: 85 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_ceqi_d_ARG1 86 %1 = tail call <2 x i64> @llvm.mips.ceqi.d(<2 x i64> %0, i32 14) 87 store <2 x i64> %1, <2 x i64>* @llvm_mips_ceqi_d_RES1 88 %2 = tail call <2 x i64> @llvm.mips.ceqi.d(<2 x i64> %0, i32 -14) 89 store <2 x i64> %2, <2 x i64>* @llvm_mips_ceqi_d_RES2 90 ret void 91} 92 93declare <2 x i64> @llvm.mips.ceqi.d(<2 x i64>, i32) nounwind 94 95; CHECK: llvm_mips_ceqi_d_test: 96; CHECK: ld.d [[RS:\$w[0-9]+]] 97; CHECK: ceqi.d [[RD1:\$w[0-9]]], [[RS]], 14 98; CHECK: st.d [[RD1]] 99; CHECK: ceqi.d [[RD2:\$w[0-9]]], [[RS]], -14 100; CHECK: st.d [[RD2]] 101; CHECK: .size llvm_mips_ceqi_d_test 102; 103@llvm_mips_clei_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 104@llvm_mips_clei_s_b_RES1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 105@llvm_mips_clei_s_b_RES2 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 106 107define void @llvm_mips_clei_s_b_test() nounwind { 108entry: 109 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_clei_s_b_ARG1 110 %1 = tail call <16 x i8> @llvm.mips.clei.s.b(<16 x i8> %0, i32 14) 111 store <16 x i8> %1, <16 x i8>* @llvm_mips_clei_s_b_RES1 112 %2 = tail call <16 x i8> @llvm.mips.clei.s.b(<16 x i8> %0, i32 -14) 113 store <16 x i8> %2, <16 x i8>* @llvm_mips_clei_s_b_RES2 114 ret void 115} 116 117declare <16 x i8> @llvm.mips.clei.s.b(<16 x i8>, i32) nounwind 118 119; CHECK: llvm_mips_clei_s_b_test: 120; CHECK: ld.b [[RS:\$w[0-9]+]] 121; CHECK: clei_s.b [[RD1:\$w[0-9]]], [[RS]], 14 122; CHECK: st.b [[RD1]] 123; CHECK: clei_s.b [[RD2:\$w[0-9]]], [[RS]], -14 124; CHECK: st.b [[RD2]] 125; CHECK: .size llvm_mips_clei_s_b_test 126; 127@llvm_mips_clei_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 128@llvm_mips_clei_s_h_RES1 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 129@llvm_mips_clei_s_h_RES2 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 130 131define void @llvm_mips_clei_s_h_test() nounwind { 132entry: 133 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_clei_s_h_ARG1 134 %1 = tail call <8 x i16> @llvm.mips.clei.s.h(<8 x i16> %0, i32 14) 135 store <8 x i16> %1, <8 x i16>* @llvm_mips_clei_s_h_RES1 136 %2 = tail call <8 x i16> @llvm.mips.clei.s.h(<8 x i16> %0, i32 -14) 137 store <8 x i16> %2, <8 x i16>* @llvm_mips_clei_s_h_RES2 138 ret void 139} 140 141declare <8 x i16> @llvm.mips.clei.s.h(<8 x i16>, i32) nounwind 142 143; CHECK: llvm_mips_clei_s_h_test: 144; CHECK: ld.h [[RS:\$w[0-9]+]] 145; CHECK: clei_s.h [[RD1:\$w[0-9]]], [[RS]], 14 146; CHECK: st.h [[RD1]] 147; CHECK: clei_s.h [[RD2:\$w[0-9]]], [[RS]], -14 148; CHECK: st.h [[RD2]] 149; CHECK: .size llvm_mips_clei_s_h_test 150; 151@llvm_mips_clei_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 152@llvm_mips_clei_s_w_RES1 = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 153@llvm_mips_clei_s_w_RES2 = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 154 155define void @llvm_mips_clei_s_w_test() nounwind { 156entry: 157 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_clei_s_w_ARG1 158 %1 = tail call <4 x i32> @llvm.mips.clei.s.w(<4 x i32> %0, i32 14) 159 store <4 x i32> %1, <4 x i32>* @llvm_mips_clei_s_w_RES1 160 %2 = tail call <4 x i32> @llvm.mips.clei.s.w(<4 x i32> %0, i32 -14) 161 store <4 x i32> %2, <4 x i32>* @llvm_mips_clei_s_w_RES2 162 ret void 163} 164 165declare <4 x i32> @llvm.mips.clei.s.w(<4 x i32>, i32) nounwind 166 167; CHECK: llvm_mips_clei_s_w_test: 168; CHECK: ld.w [[RS:\$w[0-9]+]] 169; CHECK: clei_s.w [[RD1:\$w[0-9]]], [[RS]], 14 170; CHECK: st.w [[RD1]] 171; CHECK: clei_s.w [[RD2:\$w[0-9]]], [[RS]], -14 172; CHECK: st.w [[RD2]] 173; CHECK: .size llvm_mips_clei_s_w_test 174; 175@llvm_mips_clei_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 176@llvm_mips_clei_s_d_RES1 = global <2 x i64> <i64 0, i64 0>, align 16 177@llvm_mips_clei_s_d_RES2 = global <2 x i64> <i64 0, i64 0>, align 16 178 179define void @llvm_mips_clei_s_d_test() nounwind { 180entry: 181 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_clei_s_d_ARG1 182 %1 = tail call <2 x i64> @llvm.mips.clei.s.d(<2 x i64> %0, i32 14) 183 store <2 x i64> %1, <2 x i64>* @llvm_mips_clei_s_d_RES1 184 %2 = tail call <2 x i64> @llvm.mips.clei.s.d(<2 x i64> %0, i32 -14) 185 store <2 x i64> %2, <2 x i64>* @llvm_mips_clei_s_d_RES2 186 ret void 187} 188 189declare <2 x i64> @llvm.mips.clei.s.d(<2 x i64>, i32) nounwind 190 191; CHECK: llvm_mips_clei_s_d_test: 192; CHECK: ld.d [[RS:\$w[0-9]+]] 193; CHECK: clei_s.d [[RD1:\$w[0-9]]], [[RS]], 14 194; CHECK: st.d [[RD1]] 195; CHECK: clei_s.d [[RD2:\$w[0-9]]], [[RS]], -14 196; CHECK: st.d [[RD2]] 197; CHECK: .size llvm_mips_clei_s_d_test 198; 199@llvm_mips_clei_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 200@llvm_mips_clei_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 201 202define void @llvm_mips_clei_u_b_test() nounwind { 203entry: 204 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_clei_u_b_ARG1 205 %1 = tail call <16 x i8> @llvm.mips.clei.u.b(<16 x i8> %0, i32 14) 206 store <16 x i8> %1, <16 x i8>* @llvm_mips_clei_u_b_RES 207 ret void 208} 209 210declare <16 x i8> @llvm.mips.clei.u.b(<16 x i8>, i32) nounwind 211 212; CHECK: llvm_mips_clei_u_b_test: 213; CHECK: ld.b 214; CHECK: clei_u.b 215; CHECK: st.b 216; CHECK: .size llvm_mips_clei_u_b_test 217; 218@llvm_mips_clei_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 219@llvm_mips_clei_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 220 221define void @llvm_mips_clei_u_h_test() nounwind { 222entry: 223 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_clei_u_h_ARG1 224 %1 = tail call <8 x i16> @llvm.mips.clei.u.h(<8 x i16> %0, i32 14) 225 store <8 x i16> %1, <8 x i16>* @llvm_mips_clei_u_h_RES 226 ret void 227} 228 229declare <8 x i16> @llvm.mips.clei.u.h(<8 x i16>, i32) nounwind 230 231; CHECK: llvm_mips_clei_u_h_test: 232; CHECK: ld.h 233; CHECK: clei_u.h 234; CHECK: st.h 235; CHECK: .size llvm_mips_clei_u_h_test 236; 237@llvm_mips_clei_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 238@llvm_mips_clei_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 239 240define void @llvm_mips_clei_u_w_test() nounwind { 241entry: 242 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_clei_u_w_ARG1 243 %1 = tail call <4 x i32> @llvm.mips.clei.u.w(<4 x i32> %0, i32 14) 244 store <4 x i32> %1, <4 x i32>* @llvm_mips_clei_u_w_RES 245 ret void 246} 247 248declare <4 x i32> @llvm.mips.clei.u.w(<4 x i32>, i32) nounwind 249 250; CHECK: llvm_mips_clei_u_w_test: 251; CHECK: ld.w 252; CHECK: clei_u.w 253; CHECK: st.w 254; CHECK: .size llvm_mips_clei_u_w_test 255; 256@llvm_mips_clei_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 257@llvm_mips_clei_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 258 259define void @llvm_mips_clei_u_d_test() nounwind { 260entry: 261 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_clei_u_d_ARG1 262 %1 = tail call <2 x i64> @llvm.mips.clei.u.d(<2 x i64> %0, i32 14) 263 store <2 x i64> %1, <2 x i64>* @llvm_mips_clei_u_d_RES 264 ret void 265} 266 267declare <2 x i64> @llvm.mips.clei.u.d(<2 x i64>, i32) nounwind 268 269; CHECK: llvm_mips_clei_u_d_test: 270; CHECK: ld.d 271; CHECK: clei_u.d 272; CHECK: st.d 273; CHECK: .size llvm_mips_clei_u_d_test 274; 275@llvm_mips_clti_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 276@llvm_mips_clti_s_b_RES1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 277@llvm_mips_clti_s_b_RES2 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 278 279define void @llvm_mips_clti_s_b_test() nounwind { 280entry: 281 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_clti_s_b_ARG1 282 %1 = tail call <16 x i8> @llvm.mips.clti.s.b(<16 x i8> %0, i32 14) 283 store <16 x i8> %1, <16 x i8>* @llvm_mips_clti_s_b_RES1 284 %2 = tail call <16 x i8> @llvm.mips.clti.s.b(<16 x i8> %0, i32 -14) 285 store <16 x i8> %2, <16 x i8>* @llvm_mips_clti_s_b_RES2 286 ret void 287} 288 289declare <16 x i8> @llvm.mips.clti.s.b(<16 x i8>, i32) nounwind 290 291; CHECK: llvm_mips_clti_s_b_test: 292; CHECK: ld.b [[RS:\$w[0-9]+]] 293; CHECK: clti_s.b [[RD1:\$w[0-9]]], [[RS]], 14 294; CHECK: st.b [[RD1]] 295; CHECK: clti_s.b [[RD2:\$w[0-9]]], [[RS]], -14 296; CHECK: st.b [[RD2]] 297; CHECK: .size llvm_mips_clti_s_b_test 298; 299@llvm_mips_clti_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 300@llvm_mips_clti_s_h_RES1 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 301@llvm_mips_clti_s_h_RES2 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 302 303define void @llvm_mips_clti_s_h_test() nounwind { 304entry: 305 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_clti_s_h_ARG1 306 %1 = tail call <8 x i16> @llvm.mips.clti.s.h(<8 x i16> %0, i32 14) 307 store <8 x i16> %1, <8 x i16>* @llvm_mips_clti_s_h_RES1 308 %2 = tail call <8 x i16> @llvm.mips.clti.s.h(<8 x i16> %0, i32 -14) 309 store <8 x i16> %2, <8 x i16>* @llvm_mips_clti_s_h_RES2 310 ret void 311} 312 313declare <8 x i16> @llvm.mips.clti.s.h(<8 x i16>, i32) nounwind 314 315; CHECK: llvm_mips_clti_s_h_test: 316; CHECK: ld.h [[RS:\$w[0-9]+]] 317; CHECK: clti_s.h [[RD1:\$w[0-9]]], [[RS]], 14 318; CHECK: st.h [[RD1]] 319; CHECK: clti_s.h [[RD2:\$w[0-9]]], [[RS]], -14 320; CHECK: st.h [[RD2]] 321; CHECK: .size llvm_mips_clti_s_h_test 322; 323@llvm_mips_clti_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 324@llvm_mips_clti_s_w_RES1 = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 325@llvm_mips_clti_s_w_RES2 = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 326 327define void @llvm_mips_clti_s_w_test() nounwind { 328entry: 329 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_clti_s_w_ARG1 330 %1 = tail call <4 x i32> @llvm.mips.clti.s.w(<4 x i32> %0, i32 14) 331 store <4 x i32> %1, <4 x i32>* @llvm_mips_clti_s_w_RES1 332 %2 = tail call <4 x i32> @llvm.mips.clti.s.w(<4 x i32> %0, i32 -14) 333 store <4 x i32> %2, <4 x i32>* @llvm_mips_clti_s_w_RES2 334 ret void 335} 336 337declare <4 x i32> @llvm.mips.clti.s.w(<4 x i32>, i32) nounwind 338 339; CHECK: llvm_mips_clti_s_w_test: 340; CHECK: ld.w [[RS:\$w[0-9]+]] 341; CHECK: clti_s.w [[RD1:\$w[0-9]]], [[RS]], 14 342; CHECK: st.w [[RD1]] 343; CHECK: clti_s.w [[RD2:\$w[0-9]]], [[RS]], -14 344; CHECK: st.w [[RD2]] 345; CHECK: .size llvm_mips_clti_s_w_test 346; 347@llvm_mips_clti_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 348@llvm_mips_clti_s_d_RES1 = global <2 x i64> <i64 0, i64 0>, align 16 349@llvm_mips_clti_s_d_RES2 = global <2 x i64> <i64 0, i64 0>, align 16 350 351define void @llvm_mips_clti_s_d_test() nounwind { 352entry: 353 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_clti_s_d_ARG1 354 %1 = tail call <2 x i64> @llvm.mips.clti.s.d(<2 x i64> %0, i32 14) 355 store <2 x i64> %1, <2 x i64>* @llvm_mips_clti_s_d_RES1 356 %2 = tail call <2 x i64> @llvm.mips.clti.s.d(<2 x i64> %0, i32 -14) 357 store <2 x i64> %2, <2 x i64>* @llvm_mips_clti_s_d_RES2 358 ret void 359} 360 361declare <2 x i64> @llvm.mips.clti.s.d(<2 x i64>, i32) nounwind 362 363; CHECK: llvm_mips_clti_s_d_test: 364; CHECK: ld.d [[RS:\$w[0-9]+]] 365; CHECK: clti_s.d [[RD1:\$w[0-9]]], [[RS]], 14 366; CHECK: st.d [[RD1]] 367; CHECK: clti_s.d [[RD2:\$w[0-9]]], [[RS]], -14 368; CHECK: st.d [[RD2]] 369; CHECK: .size llvm_mips_clti_s_d_test 370; 371@llvm_mips_clti_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 372@llvm_mips_clti_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 373 374define void @llvm_mips_clti_u_b_test() nounwind { 375entry: 376 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_clti_u_b_ARG1 377 %1 = tail call <16 x i8> @llvm.mips.clti.u.b(<16 x i8> %0, i32 14) 378 store <16 x i8> %1, <16 x i8>* @llvm_mips_clti_u_b_RES 379 ret void 380} 381 382declare <16 x i8> @llvm.mips.clti.u.b(<16 x i8>, i32) nounwind 383 384; CHECK: llvm_mips_clti_u_b_test: 385; CHECK: ld.b 386; CHECK: clti_u.b 387; CHECK: st.b 388; CHECK: .size llvm_mips_clti_u_b_test 389; 390@llvm_mips_clti_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 391@llvm_mips_clti_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 392 393define void @llvm_mips_clti_u_h_test() nounwind { 394entry: 395 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_clti_u_h_ARG1 396 %1 = tail call <8 x i16> @llvm.mips.clti.u.h(<8 x i16> %0, i32 14) 397 store <8 x i16> %1, <8 x i16>* @llvm_mips_clti_u_h_RES 398 ret void 399} 400 401declare <8 x i16> @llvm.mips.clti.u.h(<8 x i16>, i32) nounwind 402 403; CHECK: llvm_mips_clti_u_h_test: 404; CHECK: ld.h 405; CHECK: clti_u.h 406; CHECK: st.h 407; CHECK: .size llvm_mips_clti_u_h_test 408; 409@llvm_mips_clti_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 410@llvm_mips_clti_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 411 412define void @llvm_mips_clti_u_w_test() nounwind { 413entry: 414 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_clti_u_w_ARG1 415 %1 = tail call <4 x i32> @llvm.mips.clti.u.w(<4 x i32> %0, i32 14) 416 store <4 x i32> %1, <4 x i32>* @llvm_mips_clti_u_w_RES 417 ret void 418} 419 420declare <4 x i32> @llvm.mips.clti.u.w(<4 x i32>, i32) nounwind 421 422; CHECK: llvm_mips_clti_u_w_test: 423; CHECK: ld.w 424; CHECK: clti_u.w 425; CHECK: st.w 426; CHECK: .size llvm_mips_clti_u_w_test 427; 428@llvm_mips_clti_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 429@llvm_mips_clti_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 430 431define void @llvm_mips_clti_u_d_test() nounwind { 432entry: 433 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_clti_u_d_ARG1 434 %1 = tail call <2 x i64> @llvm.mips.clti.u.d(<2 x i64> %0, i32 14) 435 store <2 x i64> %1, <2 x i64>* @llvm_mips_clti_u_d_RES 436 ret void 437} 438 439declare <2 x i64> @llvm.mips.clti.u.d(<2 x i64>, i32) nounwind 440 441; CHECK: llvm_mips_clti_u_d_test: 442; CHECK: ld.d 443; CHECK: clti_u.d 444; CHECK: st.d 445; CHECK: .size llvm_mips_clti_u_d_test 446; 447