1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-cp-islands %s -o - | FileCheck %s 3--- | 4 @d = hidden local_unnamed_addr global i32 0, align 4 5 @a = hidden global i32 0, align 4 6 @e = hidden local_unnamed_addr global i32 0, align 4 7 8 define hidden void @f(i64 %g) { 9 entry: 10 %conv = trunc i64 %g to i32 11 %tobool5 = icmp eq i64 %g, 0 12 br i1 %tobool5, label %j.us.us.preheader, label %entry.split 13 14 j.us.us.preheader: ; preds = %entry 15 %.pre59 = load i32, i32* @d, align 4 16 br label %j.us.us 17 18 j.us.us: ; preds = %j.us.us, %if.end.us.us.us, %if.end.us.us.us.1, %if.end.us.us.us.2, %if.end.us.us.us.3, %if.end.us.us.us.4, %if.end.us.us.us.5, %if.end.us.us.us.6, %j.us.us.preheader 19 %0 = phi i32 [ %.pre59, %j.us.us.preheader ], [ %12, %if.end.us.us.us.6 ], [ %11, %if.end.us.us.us.5 ], [ %10, %if.end.us.us.us.4 ], [ %9, %if.end.us.us.us.3 ], [ %8, %if.end.us.us.us.2 ], [ %7, %if.end.us.us.us.1 ], [ %2, %if.end.us.us.us ], [ %0, %j.us.us ] 20 %cmp.us.us = icmp slt i32 %0, ptrtoint (i32* @a to i32) 21 %conv1.us.us = zext i1 %cmp.us.us to i32 22 %1 = load i32, i32* @e, align 4 23 %and.us.us = and i32 %1, %conv1.us.us 24 store i32 %and.us.us, i32* @e, align 4 25 %tobool4.us.us.us = icmp eq i32 %0, 0 26 br i1 %tobool4.us.us.us, label %if.end.us.us.us, label %j.us.us 27 28 if.end.us.us.us: ; preds = %j.us.us 29 tail call void asm sideeffect "", ""() 30 %2 = load i32, i32* @d, align 4 31 %tobool4.us.us.us.1 = icmp eq i32 %2, 0 32 br i1 %tobool4.us.us.us.1, label %if.end.us.us.us.1, label %j.us.us 33 34 entry.split: ; preds = %entry 35 %tobool = icmp eq i32 %conv, 0 36 br i1 %tobool, label %j.us27.preheader, label %j.preheader 37 38 j.preheader: ; preds = %entry.split 39 %.pre = load i32, i32* @e, align 4 40 %.pre55 = load i32, i32* @d, align 4 41 %cmp = icmp slt i32 %conv, ptrtoint (i32* @a to i32) 42 %conv1 = zext i1 %cmp to i32 43 br label %j 44 45 j.us27.preheader: ; preds = %entry.split 46 %.pre56 = load i32, i32* @d, align 4 47 %.pre57 = load i32, i32* @e, align 4 48 %cmp.us29 = icmp slt i32 %.pre56, ptrtoint (i32* @a to i32) 49 %conv1.us30 = zext i1 %cmp.us29 to i32 50 br label %j.us27 51 52 j.us27: ; preds = %j.us27, %j.us27.preheader 53 %3 = phi i32 [ %.pre57, %j.us27.preheader ], [ %and.us31, %j.us27 ] 54 %4 = icmp eq i32 %.pre56, 0 55 %and.us31 = and i32 %3, %conv1.us30 56 br i1 %4, label %if.end.us38, label %j.us27 57 58 if.end.us38: ; preds = %j.us27 59 store i32 %and.us31, i32* @e, align 4 60 tail call void asm sideeffect "", ""() 61 ret void 62 63 j: ; preds = %j, %j.preheader 64 %5 = phi i32 [ %.pre, %j.preheader ], [ %and, %j ] 65 %6 = icmp eq i32 %.pre55, 0 66 %and = and i32 %5, %conv1 67 br i1 %6, label %if.end, label %j 68 69 if.end: ; preds = %j 70 store i32 %and, i32* @e, align 4 71 tail call void asm sideeffect "", ""() 72 ret void 73 74 if.end.us.us.us.1: ; preds = %if.end.us.us.us 75 tail call void asm sideeffect "", ""() 76 %7 = load i32, i32* @d, align 4 77 %tobool4.us.us.us.2 = icmp eq i32 %7, 0 78 br i1 %tobool4.us.us.us.2, label %if.end.us.us.us.2, label %j.us.us 79 80 if.end.us.us.us.2: ; preds = %if.end.us.us.us.1 81 tail call void asm sideeffect "", ""() 82 %8 = load i32, i32* @d, align 4 83 %tobool4.us.us.us.3 = icmp eq i32 %8, 0 84 br i1 %tobool4.us.us.us.3, label %if.end.us.us.us.3, label %j.us.us 85 86 if.end.us.us.us.3: ; preds = %if.end.us.us.us.2 87 tail call void asm sideeffect "", ""() 88 %9 = load i32, i32* @d, align 4 89 %tobool4.us.us.us.4 = icmp eq i32 %9, 0 90 br i1 %tobool4.us.us.us.4, label %if.end.us.us.us.4, label %j.us.us 91 92 if.end.us.us.us.4: ; preds = %if.end.us.us.us.3 93 tail call void asm sideeffect "", ""() 94 %10 = load i32, i32* @d, align 4 95 %tobool4.us.us.us.5 = icmp eq i32 %10, 0 96 br i1 %tobool4.us.us.us.5, label %if.end.us.us.us.5, label %j.us.us 97 98 if.end.us.us.us.5: ; preds = %if.end.us.us.us.4 99 tail call void asm sideeffect "", ""() 100 %11 = load i32, i32* @d, align 4 101 %tobool4.us.us.us.6 = icmp eq i32 %11, 0 102 br i1 %tobool4.us.us.us.6, label %if.end.us.us.us.6, label %j.us.us 103 104 if.end.us.us.us.6: ; preds = %if.end.us.us.us.5 105 tail call void asm sideeffect "", ""() 106 %12 = load i32, i32* @d, align 4 107 %tobool4.us.us.us.7 = icmp eq i32 %12, 0 108 br i1 %tobool4.us.us.us.7, label %if.end.us.us.us.7, label %j.us.us 109 110 if.end.us.us.us.7: ; preds = %if.end.us.us.us.6 111 tail call void asm sideeffect "", ""() 112 ret void 113 } 114 115... 116--- 117name: f 118alignment: 4 119exposesReturnsTwice: false 120legalized: false 121regBankSelected: false 122selected: false 123failedISel: false 124tracksRegLiveness: true 125hasWinCFI: false 126registers: [] 127liveins: 128 - { reg: '$r0', virtual-reg: '' } 129 - { reg: '$r1', virtual-reg: '' } 130frameInfo: 131 isFrameAddressTaken: false 132 isReturnAddressTaken: false 133 hasStackMap: false 134 hasPatchPoint: false 135 stackSize: 8 136 offsetAdjustment: 0 137 maxAlignment: 4 138 adjustsStack: false 139 hasCalls: false 140 stackProtector: '' 141 maxCallFrameSize: 0 142 cvBytesOfCalleeSavedRegisters: 0 143 hasOpaqueSPAdjustment: false 144 hasVAStart: false 145 hasMustTailInVarArgFunc: false 146 localFrameSize: 0 147 savePoint: '' 148 restorePoint: '' 149fixedStack: [] 150stack: 151 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 152 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 153 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 154 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 155 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 156 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 157callSites: [] 158constants: [] 159machineFunctionInfo: {} 160body: | 161 ; CHECK-LABEL: name: f 162 ; CHECK: bb.0.entry: 163 ; CHECK: successors: %bb.5(0x30000000), %bb.1(0x50000000) 164 ; CHECK: liveins: $r0, $r1, $r7, $lr 165 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 166 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 167 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 168 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 169 ; CHECK: dead renamable $r1, $cpsr = tORR killed renamable $r1, renamable $r0, 14 /* CC::al */, $noreg 170 ; CHECK: tBcc %bb.5, 0 /* CC::eq */, killed $cpsr 171 ; CHECK: bb.1.entry.split: 172 ; CHECK: successors: %bb.15(0x30000000), %bb.2(0x50000000) 173 ; CHECK: liveins: $r0 174 ; CHECK: tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 175 ; CHECK: tBcc %bb.15, 0 /* CC::eq */, killed $cpsr 176 ; CHECK: bb.2.j.preheader: 177 ; CHECK: successors: %bb.3(0x80000000) 178 ; CHECK: liveins: $r0 179 ; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @a, 14 /* CC::al */, $noreg 180 ; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @a, 14 /* CC::al */, $noreg 181 ; CHECK: tCMPr killed renamable $r0, killed renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr 182 ; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @d, 14 /* CC::al */, $noreg 183 ; CHECK: renamable $r0 = t2CSINC $zr, $zr, 10, implicit killed $cpsr 184 ; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @d, 14 /* CC::al */, $noreg 185 ; CHECK: renamable $r2 = tLDRi killed renamable $r1, 0, 14 /* CC::al */, $noreg :: (dereferenceable load (s32) from @d) 186 ; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @e, 14 /* CC::al */, $noreg 187 ; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @e, 14 /* CC::al */, $noreg 188 ; CHECK: renamable $r3 = tLDRi renamable $r1, 0, 14 /* CC::al */, $noreg :: (dereferenceable load (s32) from @e) 189 ; CHECK: bb.3.j (align 4): 190 ; CHECK: successors: %bb.4(0x04000000), %bb.3(0x7c000000) 191 ; CHECK: liveins: $r0, $r1, $r2, $r3 192 ; CHECK: renamable $r3, dead $cpsr = tAND killed renamable $r3, renamable $r0, 14 /* CC::al */, $noreg 193 ; CHECK: tCBZ renamable $r2, %bb.4 194 ; CHECK: t2LE %bb.3 195 ; CHECK: bb.4.if.end: 196 ; CHECK: liveins: $r1, $r3 197 ; CHECK: tSTRi killed renamable $r3, killed renamable $r1, 0, 14 /* CC::al */, $noreg :: (store (s32) into @e) 198 ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */ 199 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 200 ; CHECK: bb.5.j.us.us.preheader: 201 ; CHECK: successors: %bb.6(0x80000000) 202 ; CHECK: $r12 = t2MOVi16 target-flags(arm-lo16) @d, 14 /* CC::al */, $noreg 203 ; CHECK: $lr = t2MOVi16 target-flags(arm-lo16) @a, 14 /* CC::al */, $noreg 204 ; CHECK: $r12 = t2MOVTi16 killed $r12, target-flags(arm-hi16) @d, 14 /* CC::al */, $noreg 205 ; CHECK: $r2 = t2MOVi16 target-flags(arm-lo16) @e, 14 /* CC::al */, $noreg 206 ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load (s32) from @d) 207 ; CHECK: $lr = t2MOVTi16 killed $lr, target-flags(arm-hi16) @a, 14 /* CC::al */, $noreg 208 ; CHECK: $r2 = t2MOVTi16 killed $r2, target-flags(arm-hi16) @e, 14 /* CC::al */, $noreg 209 ; CHECK: bb.6.j.us.us (align 4): 210 ; CHECK: successors: %bb.7(0x40000000), %bb.6(0x40000000) 211 ; CHECK: liveins: $lr, $r2, $r3, $r12 212 ; CHECK: tCMPhir renamable $r3, renamable $lr, 14 /* CC::al */, $noreg, implicit-def $cpsr 213 ; CHECK: renamable $r1 = tLDRi renamable $r2, 0, 14 /* CC::al */, $noreg :: (dereferenceable load (s32) from @e) 214 ; CHECK: renamable $r0 = t2CSINC $zr, $zr, 10, implicit killed $cpsr 215 ; CHECK: renamable $r0 = t2ANDrr killed renamable $r0, killed renamable $r1, 14 /* CC::al */, $noreg, $noreg 216 ; CHECK: tSTRi killed renamable $r0, renamable $r2, 0, 14 /* CC::al */, $noreg :: (store (s32) into @e) 217 ; CHECK: tCBZ renamable $r3, %bb.7 218 ; CHECK: t2LE %bb.6 219 ; CHECK: bb.7.if.end.us.us.us: 220 ; CHECK: successors: %bb.8(0x40000000), %bb.6(0x40000000) 221 ; CHECK: liveins: $lr, $r2, $r12 222 ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */ 223 ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load (s32) from @d) 224 ; CHECK: tCBZ renamable $r3, %bb.8 225 ; CHECK: t2LE %bb.6 226 ; CHECK: bb.8.if.end.us.us.us.1: 227 ; CHECK: successors: %bb.9(0x40000000), %bb.6(0x40000000) 228 ; CHECK: liveins: $lr, $r2, $r12 229 ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */ 230 ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load (s32) from @d) 231 ; CHECK: tCBZ renamable $r3, %bb.9 232 ; CHECK: t2LE %bb.6 233 ; CHECK: bb.9.if.end.us.us.us.2: 234 ; CHECK: successors: %bb.10(0x40000000), %bb.6(0x40000000) 235 ; CHECK: liveins: $lr, $r2, $r12 236 ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */ 237 ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load (s32) from @d) 238 ; CHECK: tCBZ renamable $r3, %bb.10 239 ; CHECK: t2LE %bb.6 240 ; CHECK: bb.10.if.end.us.us.us.3: 241 ; CHECK: successors: %bb.11(0x40000000), %bb.6(0x40000000) 242 ; CHECK: liveins: $lr, $r2, $r12 243 ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */ 244 ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load (s32) from @d) 245 ; CHECK: tCBZ renamable $r3, %bb.11 246 ; CHECK: t2LE %bb.6 247 ; CHECK: bb.11.if.end.us.us.us.4: 248 ; CHECK: successors: %bb.12(0x40000000), %bb.6(0x40000000) 249 ; CHECK: liveins: $lr, $r2, $r12 250 ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */ 251 ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load (s32) from @d) 252 ; CHECK: tCBZ renamable $r3, %bb.12 253 ; CHECK: t2LE %bb.6 254 ; CHECK: bb.12.if.end.us.us.us.5: 255 ; CHECK: successors: %bb.13(0x40000000), %bb.6(0x40000000) 256 ; CHECK: liveins: $lr, $r2, $r12 257 ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */ 258 ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load (s32) from @d) 259 ; CHECK: tCBZ renamable $r3, %bb.13 260 ; CHECK: t2LE %bb.6 261 ; CHECK: bb.13.if.end.us.us.us.6: 262 ; CHECK: successors: %bb.14(0x04000000), %bb.6(0x7c000000) 263 ; CHECK: liveins: $lr, $r2, $r12 264 ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */ 265 ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load (s32) from @d) 266 ; CHECK: tCBZ renamable $r3, %bb.14 267 ; CHECK: t2LE %bb.6 268 ; CHECK: bb.14.if.end.us.us.us.7: 269 ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */ 270 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 271 ; CHECK: bb.15.j.us27.preheader: 272 ; CHECK: successors: %bb.16(0x80000000) 273 ; CHECK: $r0 = t2MOVi16 target-flags(arm-lo16) @d, 14 /* CC::al */, $noreg 274 ; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @a, 14 /* CC::al */, $noreg 275 ; CHECK: $r0 = t2MOVTi16 killed $r0, target-flags(arm-hi16) @d, 14 /* CC::al */, $noreg 276 ; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @a, 14 /* CC::al */, $noreg 277 ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (dereferenceable load (s32) from @d) 278 ; CHECK: tCMPr renamable $r0, killed renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr 279 ; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @e, 14 /* CC::al */, $noreg 280 ; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @e, 14 /* CC::al */, $noreg 281 ; CHECK: renamable $r2 = t2CSINC $zr, $zr, 10, implicit killed $cpsr 282 ; CHECK: renamable $r3 = tLDRi renamable $r1, 0, 14 /* CC::al */, $noreg :: (dereferenceable load (s32) from @e) 283 ; CHECK: bb.16.j.us27 (align 4): 284 ; CHECK: successors: %bb.17(0x04000000), %bb.16(0x7c000000) 285 ; CHECK: liveins: $r0, $r1, $r2, $r3 286 ; CHECK: renamable $r3, dead $cpsr = tAND killed renamable $r3, renamable $r2, 14 /* CC::al */, $noreg 287 ; CHECK: tCBZ renamable $r0, %bb.17 288 ; CHECK: t2LE %bb.16 289 ; CHECK: bb.17.if.end.us38: 290 ; CHECK: liveins: $r1, $r3 291 ; CHECK: tSTRi killed renamable $r3, killed renamable $r1, 0, 14 /* CC::al */, $noreg :: (store (s32) into @e) 292 ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */ 293 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 294 bb.0.entry: 295 successors: %bb.1(0x30000000), %bb.11(0x50000000) 296 liveins: $r0, $r1, $r7, $lr 297 298 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 299 frame-setup CFI_INSTRUCTION def_cfa_offset 8 300 frame-setup CFI_INSTRUCTION offset $lr, -4 301 frame-setup CFI_INSTRUCTION offset $r7, -8 302 dead renamable $r1, $cpsr = tORR killed renamable $r1, renamable $r0, 14, $noreg 303 t2Bcc %bb.1, 0, killed $cpsr 304 305 bb.11.entry.split: 306 successors: %bb.15(0x30000000), %bb.12(0x50000000) 307 liveins: $r0 308 309 tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr 310 t2Bcc %bb.15, 0, killed $cpsr 311 312 bb.12.j.preheader: 313 successors: %bb.13(0x80000000) 314 liveins: $r0 315 316 $r1 = t2MOVi16 target-flags(arm-lo16) @a, 14, $noreg 317 $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @a, 14, $noreg 318 tCMPr killed renamable $r0, killed renamable $r1, 14, $noreg, implicit-def $cpsr 319 $r1 = t2MOVi16 target-flags(arm-lo16) @d, 14, $noreg 320 renamable $r0 = t2CSINC $zr, $zr, 10, implicit killed $cpsr 321 $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @d, 14, $noreg 322 renamable $r2 = tLDRi killed renamable $r1, 0, 14, $noreg :: (dereferenceable load (s32) from @d) 323 $r1 = t2MOVi16 target-flags(arm-lo16) @e, 14, $noreg 324 $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @e, 14, $noreg 325 renamable $r3 = tLDRi renamable $r1, 0, 14, $noreg :: (dereferenceable load (s32) from @e) 326 327 bb.13.j (align 4): 328 successors: %bb.14(0x04000000), %bb.13(0x7c000000) 329 liveins: $r0, $r1, $r2, $r3 330 331 renamable $r3, dead $cpsr = tAND killed renamable $r3, renamable $r0, 14, $noreg 332 tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr 333 t2Bcc %bb.13, 1, killed $cpsr 334 335 bb.14.if.end: 336 liveins: $r1, $r3 337 338 tSTRi killed renamable $r3, killed renamable $r1, 0, 14, $noreg :: (store (s32) into @e) 339 INLINEASM &"", 1 340 tPOP_RET 14, $noreg, def $r7, def $pc 341 342 bb.1.j.us.us.preheader: 343 successors: %bb.2(0x80000000) 344 345 $r12 = t2MOVi16 target-flags(arm-lo16) @d, 14, $noreg 346 $lr = t2MOVi16 target-flags(arm-lo16) @a, 14, $noreg 347 $r12 = t2MOVTi16 killed $r12, target-flags(arm-hi16) @d, 14, $noreg 348 $r2 = t2MOVi16 target-flags(arm-lo16) @e, 14, $noreg 349 renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load (s32) from @d) 350 $lr = t2MOVTi16 killed $lr, target-flags(arm-hi16) @a, 14, $noreg 351 $r2 = t2MOVTi16 killed $r2, target-flags(arm-hi16) @e, 14, $noreg 352 353 bb.2.j.us.us (align 4): 354 successors: %bb.3(0x40000000), %bb.2(0x40000000) 355 liveins: $lr, $r2, $r3, $r12 356 357 tCMPhir renamable $r3, renamable $lr, 14, $noreg, implicit-def $cpsr 358 renamable $r1 = tLDRi renamable $r2, 0, 14, $noreg :: (dereferenceable load (s32) from @e) 359 renamable $r0 = t2CSINC $zr, $zr, 10, implicit killed $cpsr 360 tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr 361 renamable $r0 = t2ANDrr killed renamable $r0, killed renamable $r1, 14, $noreg, $noreg 362 tSTRi killed renamable $r0, renamable $r2, 0, 14, $noreg :: (store (s32) into @e) 363 t2Bcc %bb.2, 1, killed $cpsr 364 365 bb.3.if.end.us.us.us: 366 successors: %bb.4(0x40000000), %bb.2(0x40000000) 367 liveins: $lr, $r2, $r12 368 369 INLINEASM &"", 1 370 renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load (s32) from @d) 371 tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr 372 t2Bcc %bb.2, 1, killed $cpsr 373 374 bb.4.if.end.us.us.us.1: 375 successors: %bb.5(0x40000000), %bb.2(0x40000000) 376 liveins: $lr, $r2, $r12 377 378 INLINEASM &"", 1 379 renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load (s32) from @d) 380 tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr 381 t2Bcc %bb.2, 1, killed $cpsr 382 383 bb.5.if.end.us.us.us.2: 384 successors: %bb.6(0x40000000), %bb.2(0x40000000) 385 liveins: $lr, $r2, $r12 386 387 INLINEASM &"", 1 388 renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load (s32) from @d) 389 tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr 390 t2Bcc %bb.2, 1, killed $cpsr 391 392 bb.6.if.end.us.us.us.3: 393 successors: %bb.7(0x40000000), %bb.2(0x40000000) 394 liveins: $lr, $r2, $r12 395 396 INLINEASM &"", 1 397 renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load (s32) from @d) 398 tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr 399 t2Bcc %bb.2, 1, killed $cpsr 400 401 bb.7.if.end.us.us.us.4: 402 successors: %bb.8(0x40000000), %bb.2(0x40000000) 403 liveins: $lr, $r2, $r12 404 405 INLINEASM &"", 1 406 renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load (s32) from @d) 407 tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr 408 t2Bcc %bb.2, 1, killed $cpsr 409 410 bb.8.if.end.us.us.us.5: 411 successors: %bb.9(0x40000000), %bb.2(0x40000000) 412 liveins: $lr, $r2, $r12 413 414 INLINEASM &"", 1 415 renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load (s32) from @d) 416 tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr 417 t2Bcc %bb.2, 1, killed $cpsr 418 419 bb.9.if.end.us.us.us.6: 420 successors: %bb.10(0x04000000), %bb.2(0x7c000000) 421 liveins: $lr, $r2, $r12 422 423 INLINEASM &"", 1 424 renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load (s32) from @d) 425 tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr 426 t2Bcc %bb.2, 1, killed $cpsr 427 428 bb.10.if.end.us.us.us.7: 429 INLINEASM &"", 1 430 tPOP_RET 14, $noreg, def $r7, def $pc 431 432 bb.15.j.us27.preheader: 433 successors: %bb.16(0x80000000) 434 435 $r0 = t2MOVi16 target-flags(arm-lo16) @d, 14, $noreg 436 $r1 = t2MOVi16 target-flags(arm-lo16) @a, 14, $noreg 437 $r0 = t2MOVTi16 killed $r0, target-flags(arm-hi16) @d, 14, $noreg 438 $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @a, 14, $noreg 439 renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (dereferenceable load (s32) from @d) 440 tCMPr renamable $r0, killed renamable $r1, 14, $noreg, implicit-def $cpsr 441 $r1 = t2MOVi16 target-flags(arm-lo16) @e, 14, $noreg 442 $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @e, 14, $noreg 443 renamable $r2 = t2CSINC $zr, $zr, 10, implicit killed $cpsr 444 renamable $r3 = tLDRi renamable $r1, 0, 14, $noreg :: (dereferenceable load (s32) from @e) 445 446 bb.16.j.us27 (align 4): 447 successors: %bb.17(0x04000000), %bb.16(0x7c000000) 448 liveins: $r0, $r1, $r2, $r3 449 450 renamable $r3, dead $cpsr = tAND killed renamable $r3, renamable $r2, 14, $noreg 451 tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr 452 t2Bcc %bb.16, 1, killed $cpsr 453 454 bb.17.if.end.us38: 455 liveins: $r1, $r3 456 457 tSTRi killed renamable $r3, killed renamable $r1, 0, 14, $noreg :: (store (s32) into @e) 458 INLINEASM &"", 1 459 tPOP_RET 14, $noreg, def $r7, def $pc 460 461... 462