1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -tail-predication=enabled %s -o - | FileCheck %s 3 4define dso_local arm_aapcs_vfpcc i32 @minmaxval4(i32* nocapture readonly %x, i32* nocapture %minp) { 5; CHECK-LABEL: minmaxval4: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: push {r7, lr} 8; CHECK-NEXT: vmov.i32 q0, #0x80000000 9; CHECK-NEXT: vmvn.i32 q1, #0x80000000 10; CHECK-NEXT: movs r2, #10 11; CHECK-NEXT: dlstp.32 lr, r2 12; CHECK-NEXT: .LBB0_1: @ %vector.body 13; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 14; CHECK-NEXT: vldrw.u32 q2, [r0], #16 15; CHECK-NEXT: vpt.s32 gt, q2, q0 16; CHECK-NEXT: vmovt q0, q2 17; CHECK-NEXT: vpt.s32 gt, q1, q2 18; CHECK-NEXT: vmovt q1, q2 19; CHECK-NEXT: letp lr, .LBB0_1 20; CHECK-NEXT: @ %bb.2: @ %middle.block 21; CHECK-NEXT: mvn r0, #-2147483648 22; CHECK-NEXT: vminv.s32 r0, q1 23; CHECK-NEXT: str r0, [r1] 24; CHECK-NEXT: mov.w r0, #-2147483648 25; CHECK-NEXT: vmaxv.s32 r0, q0 26; CHECK-NEXT: pop {r7, pc} 27entry: 28 br label %vector.body 29 30vector.body: ; preds = %vector.body, %entry 31 %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ] 32 %vec.phi = phi <4 x i32> [ <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>, %entry ], [ %5, %vector.body ] 33 %vec.phi29 = phi <4 x i32> [ <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %entry ], [ %7, %vector.body ] 34 %0 = getelementptr inbounds i32, i32* %x, i32 %index 35 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 10) 36 %1 = bitcast i32* %0 to <4 x i32>* 37 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %1, i32 4, <4 x i1> %active.lane.mask, <4 x i32> undef) 38 %2 = icmp sgt <4 x i32> %wide.masked.load, %vec.phi29 39 %3 = icmp slt <4 x i32> %wide.masked.load, %vec.phi 40 %4 = and <4 x i1> %active.lane.mask, %3 41 %5 = select <4 x i1> %4, <4 x i32> %wide.masked.load, <4 x i32> %vec.phi 42 %6 = and <4 x i1> %active.lane.mask, %2 43 %7 = select <4 x i1> %6, <4 x i32> %wide.masked.load, <4 x i32> %vec.phi29 44 %index.next = add i32 %index, 4 45 %8 = icmp eq i32 %index.next, 12 46 br i1 %8, label %middle.block, label %vector.body 47 48middle.block: ; preds = %vector.body 49 %9 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %7) 50 %10 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %5) 51 store i32 %10, i32* %minp, align 4 52 ret i32 %9 53} 54 55declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32) #1 56declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>) #2 57declare i32 @llvm.vector.reduce.smin.v4i32(<4 x i32>) #3 58declare i32 @llvm.vector.reduce.smax.v4i32(<4 x i32>) #3 59 60