1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE 3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX 4 5declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32) nounwind readnone 6declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32) nounwind readnone 7 8declare {<4 x i32>, <4 x i1>} @llvm.sadd.with.overflow.v4i32(<4 x i32>, <4 x i32>) nounwind readnone 9declare {<4 x i32>, <4 x i1>} @llvm.uadd.with.overflow.v4i32(<4 x i32>, <4 x i32>) nounwind readnone 10 11; fold (sadd x, 0) -> x 12define i32 @combine_sadd_zero(i32 %a0, i32 %a1) { 13; SSE-LABEL: combine_sadd_zero: 14; SSE: # %bb.0: 15; SSE-NEXT: movl %edi, %eax 16; SSE-NEXT: retq 17; 18; AVX-LABEL: combine_sadd_zero: 19; AVX: # %bb.0: 20; AVX-NEXT: movl %edi, %eax 21; AVX-NEXT: retq 22 %1 = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a0, i32 zeroinitializer) 23 %2 = extractvalue {i32, i1} %1, 0 24 %3 = extractvalue {i32, i1} %1, 1 25 %4 = select i1 %3, i32 %a1, i32 %2 26 ret i32 %4 27} 28 29define <4 x i32> @combine_vec_sadd_zero(<4 x i32> %a0, <4 x i32> %a1) { 30; SSE-LABEL: combine_vec_sadd_zero: 31; SSE: # %bb.0: 32; SSE-NEXT: retq 33; 34; AVX-LABEL: combine_vec_sadd_zero: 35; AVX: # %bb.0: 36; AVX-NEXT: retq 37 %1 = call {<4 x i32>, <4 x i1>} @llvm.sadd.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> zeroinitializer) 38 %2 = extractvalue {<4 x i32>, <4 x i1>} %1, 0 39 %3 = extractvalue {<4 x i32>, <4 x i1>} %1, 1 40 %4 = select <4 x i1> %3, <4 x i32> %a1, <4 x i32> %2 41 ret <4 x i32> %4 42} 43 44; fold (uadd x, 0) -> x 45define i32 @combine_uadd_zero(i32 %a0, i32 %a1) { 46; SSE-LABEL: combine_uadd_zero: 47; SSE: # %bb.0: 48; SSE-NEXT: movl %edi, %eax 49; SSE-NEXT: retq 50; 51; AVX-LABEL: combine_uadd_zero: 52; AVX: # %bb.0: 53; AVX-NEXT: movl %edi, %eax 54; AVX-NEXT: retq 55 %1 = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a0, i32 zeroinitializer) 56 %2 = extractvalue {i32, i1} %1, 0 57 %3 = extractvalue {i32, i1} %1, 1 58 %4 = select i1 %3, i32 %a1, i32 %2 59 ret i32 %4 60} 61 62define <4 x i32> @combine_vec_uadd_zero(<4 x i32> %a0, <4 x i32> %a1) { 63; SSE-LABEL: combine_vec_uadd_zero: 64; SSE: # %bb.0: 65; SSE-NEXT: retq 66; 67; AVX-LABEL: combine_vec_uadd_zero: 68; AVX: # %bb.0: 69; AVX-NEXT: retq 70 %1 = call {<4 x i32>, <4 x i1>} @llvm.uadd.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> zeroinitializer) 71 %2 = extractvalue {<4 x i32>, <4 x i1>} %1, 0 72 %3 = extractvalue {<4 x i32>, <4 x i1>} %1, 1 73 %4 = select <4 x i1> %3, <4 x i32> %a1, <4 x i32> %2 74 ret <4 x i32> %4 75} 76 77; fold (uadd (xor a, -1), 1) -> (usub 0, a) and flip carry 78define i32 @combine_uadd_not(i32 %a0, i32 %a1) { 79; SSE-LABEL: combine_uadd_not: 80; SSE: # %bb.0: 81; SSE-NEXT: movl %edi, %eax 82; SSE-NEXT: negl %eax 83; SSE-NEXT: cmovael %esi, %eax 84; SSE-NEXT: retq 85; 86; AVX-LABEL: combine_uadd_not: 87; AVX: # %bb.0: 88; AVX-NEXT: movl %edi, %eax 89; AVX-NEXT: negl %eax 90; AVX-NEXT: cmovael %esi, %eax 91; AVX-NEXT: retq 92 %1 = xor i32 %a0, -1 93 %2 = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %1, i32 1) 94 %3 = extractvalue {i32, i1} %2, 0 95 %4 = extractvalue {i32, i1} %2, 1 96 %5 = select i1 %4, i32 %a1, i32 %3 97 ret i32 %5 98} 99 100define <4 x i32> @combine_vec_uadd_not(<4 x i32> %a0, <4 x i32> %a1) { 101; SSE-LABEL: combine_vec_uadd_not: 102; SSE: # %bb.0: 103; SSE-NEXT: pxor %xmm2, %xmm2 104; SSE-NEXT: psubd %xmm0, %xmm2 105; SSE-NEXT: movdqa {{.*#+}} xmm0 = [1,1,1,1] 106; SSE-NEXT: pmaxud %xmm2, %xmm0 107; SSE-NEXT: pcmpeqd %xmm2, %xmm0 108; SSE-NEXT: blendvps %xmm0, %xmm2, %xmm1 109; SSE-NEXT: movaps %xmm1, %xmm0 110; SSE-NEXT: retq 111; 112; AVX-LABEL: combine_vec_uadd_not: 113; AVX: # %bb.0: 114; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 115; AVX-NEXT: vpsubd %xmm0, %xmm2, %xmm0 116; AVX-NEXT: vpbroadcastd {{.*#+}} xmm2 = [1,1,1,1] 117; AVX-NEXT: vpmaxud %xmm2, %xmm0, %xmm2 118; AVX-NEXT: vpcmpeqd %xmm2, %xmm0, %xmm2 119; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 120; AVX-NEXT: retq 121 %1 = xor <4 x i32> %a0, <i32 -1, i32 -1, i32 -1, i32 -1> 122 %2 = call {<4 x i32>, <4 x i1>} @llvm.uadd.with.overflow.v4i32(<4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>) 123 %3 = extractvalue {<4 x i32>, <4 x i1>} %2, 0 124 %4 = extractvalue {<4 x i32>, <4 x i1>} %2, 1 125 %5 = select <4 x i1> %4, <4 x i32> %a1, <4 x i32> %3 126 ret <4 x i32> %5 127} 128 129; if uaddo never overflows, replace with add 130define i32 @combine_uadd_no_overflow(i32 %a0, i32 %a1, i32 %a2) { 131; SSE-LABEL: combine_uadd_no_overflow: 132; SSE: # %bb.0: 133; SSE-NEXT: # kill: def $edx killed $edx def $rdx 134; SSE-NEXT: # kill: def $esi killed $esi def $rsi 135; SSE-NEXT: shrl $16, %esi 136; SSE-NEXT: shrl $16, %edx 137; SSE-NEXT: leal (%rdx,%rsi), %eax 138; SSE-NEXT: retq 139; 140; AVX-LABEL: combine_uadd_no_overflow: 141; AVX: # %bb.0: 142; AVX-NEXT: # kill: def $edx killed $edx def $rdx 143; AVX-NEXT: # kill: def $esi killed $esi def $rsi 144; AVX-NEXT: shrl $16, %esi 145; AVX-NEXT: shrl $16, %edx 146; AVX-NEXT: leal (%rdx,%rsi), %eax 147; AVX-NEXT: retq 148 %1 = lshr i32 %a1, 16 149 %2 = lshr i32 %a2, 16 150 %3 = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %1, i32 %2) 151 %4 = extractvalue {i32, i1} %3, 0 152 %5 = extractvalue {i32, i1} %3, 1 153 %6 = select i1 %5, i32 %a2, i32 %4 154 ret i32 %4 155} 156 157define <4 x i32> @combine_vec_uadd_no_overflow(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2) { 158; SSE-LABEL: combine_vec_uadd_no_overflow: 159; SSE: # %bb.0: 160; SSE-NEXT: movdqa %xmm2, %xmm0 161; SSE-NEXT: psrld $16, %xmm1 162; SSE-NEXT: psrld $16, %xmm0 163; SSE-NEXT: paddd %xmm1, %xmm0 164; SSE-NEXT: retq 165; 166; AVX-LABEL: combine_vec_uadd_no_overflow: 167; AVX: # %bb.0: 168; AVX-NEXT: vpsrld $16, %xmm1, %xmm0 169; AVX-NEXT: vpsrld $16, %xmm2, %xmm1 170; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0 171; AVX-NEXT: retq 172 %1 = lshr <4 x i32> %a1, <i32 16, i32 16, i32 16, i32 16> 173 %2 = lshr <4 x i32> %a2, <i32 16, i32 16, i32 16, i32 16> 174 %3 = call {<4 x i32>, <4 x i1>} @llvm.uadd.with.overflow.v4i32(<4 x i32> %1, <4 x i32> %2) 175 %4 = extractvalue {<4 x i32>, <4 x i1>} %3, 0 176 %5 = extractvalue {<4 x i32>, <4 x i1>} %3, 1 177 %6 = select <4 x i1> %5, <4 x i32> %a2, <4 x i32> %4 178 ret <4 x i32> %4 179} 180