1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown -mattr=+sse4.1,-slow-unaligned-mem-16 | FileCheck %s 3 4define <8 x i16> @commute_fold_pblendw(<8 x i16> %a, <8 x i16>* %b) { 5; CHECK-LABEL: commute_fold_pblendw: 6; CHECK: # %bb.0: 7; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],mem[1,2,3],xmm0[4],mem[5,6,7] 8; CHECK-NEXT: retq 9 %1 = load <8 x i16>, <8 x i16>* %b 10 %2 = call <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16> %1, <8 x i16> %a, i8 17) 11 ret <8 x i16> %2 12} 13declare <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16>, <8 x i16>, i8) nounwind readnone 14 15define <4 x float> @commute_fold_blendps(<4 x float> %a, <4 x float>* %b) { 16; CHECK-LABEL: commute_fold_blendps: 17; CHECK: # %bb.0: 18; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3] 19; CHECK-NEXT: retq 20 %1 = load <4 x float>, <4 x float>* %b 21 %2 = call <4 x float> @llvm.x86.sse41.blendps(<4 x float> %1, <4 x float> %a, i8 5) 22 ret <4 x float> %2 23} 24declare <4 x float> @llvm.x86.sse41.blendps(<4 x float>, <4 x float>, i8) nounwind readnone 25 26define <2 x double> @commute_fold_blendpd(<2 x double> %a, <2 x double>* %b) { 27; CHECK-LABEL: commute_fold_blendpd: 28; CHECK: # %bb.0: 29; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],mem[2,3] 30; CHECK-NEXT: retq 31 %1 = load <2 x double>, <2 x double>* %b 32 %2 = call <2 x double> @llvm.x86.sse41.blendpd(<2 x double> %1, <2 x double> %a, i8 1) 33 ret <2 x double> %2 34} 35declare <2 x double> @llvm.x86.sse41.blendpd(<2 x double>, <2 x double>, i8) nounwind readnone 36 37define <4 x i32> @commute_fold_blend_v4i32(<4 x i32>* %a, <4 x i32> %b) { 38; CHECK-LABEL: commute_fold_blend_v4i32: 39; CHECK: # %bb.0: 40; CHECK-NEXT: paddd %xmm0, %xmm0 41; CHECK-NEXT: pblendw {{.*#+}} xmm0 = mem[0,1,2,3,4,5],xmm0[6,7] 42; CHECK-NEXT: retq 43 %1 = load <4 x i32>, <4 x i32>* %a 44 %2 = add <4 x i32> %b, %b ; force integer domain 45 %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 7> 46 ret <4 x i32> %3 47} 48 49; Test case for a crash that occurred due to blendi being commuted to 50; movsd during two address instruction pass. The change in number of operands 51; caused a bad call to getOperand. This caused the revert in r354713. 52%struct.spam = type { i64, i64 } 53 54define void @baz(<2 x i64>* %arg, %struct.spam* %arg1) optsize { 55; CHECK-LABEL: baz: 56; CHECK: # %bb.0: # %bb 57; CHECK-NEXT: movaps (%rdi), %xmm0 58; CHECK-NEXT: movaps {{.*#+}} xmm1 = [3,3] 59; CHECK-NEXT: andps %xmm0, %xmm1 60; CHECK-NEXT: blendps {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3] 61; CHECK-NEXT: movups %xmm1, (%rsi) 62; CHECK-NEXT: retq 63bb: 64 %tmp = load <2 x i64>, <2 x i64>* %arg, align 16 65 %tmp2 = and <2 x i64> %tmp, <i64 3, i64 3> 66 %tmp3 = getelementptr inbounds %struct.spam, %struct.spam* %arg1, i64 0, i32 0 67 %tmp4 = extractelement <2 x i64> %tmp, i32 0 68 store i64 %tmp4, i64* %tmp3, align 8 69 %tmp5 = getelementptr inbounds %struct.spam, %struct.spam* %arg1, i64 0, i32 1 70 %tmp6 = extractelement <2 x i64> %tmp2, i32 1 71 store i64 %tmp6, i64* %tmp5, align 8 72 ret void 73} 74