1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-linux -mcpu=core2 -verify-machineinstrs | FileCheck %s
3
4; We were miscompiling this and using %ax instead of %cx in the movw
5; in the following sequence:
6;	movswl	%cx, %ecx
7;	movw	%cx, (%rsi)
8;	movslq	%ecx, %rcx
9;
10; We can't produce the above sequence without special SD-level
11; heuristics. Now we produce this:
12
13define i32 @f(i1 %foo, i16* %tm_year2, i8* %bar, i16 %zed, i32 %zed2) {
14; CHECK-LABEL: f:
15; CHECK:       # %bb.0: # %entry
16; CHECK-NEXT:    movl $-1, %eax
17; CHECK-NEXT:    testb $1, %dil
18; CHECK-NEXT:    jne .LBB0_2
19; CHECK-NEXT:  # %bb.1: # %if.end
20; CHECK-NEXT:    movslq %r8d, %rax
21; CHECK-NEXT:    imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
22; CHECK-NEXT:    movq %rcx, %rdi
23; CHECK-NEXT:    shrq $63, %rdi
24; CHECK-NEXT:    sarq $37, %rcx
25; CHECK-NEXT:    addl %edi, %ecx
26; CHECK-NEXT:    imull $100, %ecx, %ecx
27; CHECK-NEXT:    subl %ecx, %eax
28; CHECK-NEXT:    movw %ax, (%rsi)
29; CHECK-NEXT:    cwtl
30; CHECK-NEXT:    cltq
31; CHECK-NEXT:    imulq $1717986919, %rax, %rax # imm = 0x66666667
32; CHECK-NEXT:    movq %rax, %rcx
33; CHECK-NEXT:    shrq $63, %rcx
34; CHECK-NEXT:    shrq $34, %rax
35; CHECK-NEXT:    addl %ecx, %eax
36; CHECK-NEXT:    movb %al, (%rdx)
37; CHECK-NEXT:    xorl %eax, %eax
38; CHECK-NEXT:  .LBB0_2: # %return
39; CHECK-NEXT:    retq
40entry:
41  br i1 %foo, label %return, label %if.end
42
43if.end:
44  %rem = srem i32 %zed2, 100
45  %conv3 = trunc i32 %rem to i16
46  store i16 %conv3, i16* %tm_year2
47  %sext = shl i32 %rem, 16
48  %conv5 = ashr exact i32 %sext, 16
49  %div = sdiv i32 %conv5, 10
50  %conv6 = trunc i32 %div to i8
51  store i8 %conv6, i8* %bar
52  br label %return
53
54return:
55  %retval.0 = phi i32 [ 0, %if.end ], [ -1, %entry ]
56  ret i32 %retval.0
57}
58