1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE
3; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX
4; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl | FileCheck %s --check-prefixes=CHECK,AVX
5
6; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/sse2-builtins.c
7
8define i64 @test_mm_cvtsd_si64(<2 x double> %a0) nounwind {
9; SSE-LABEL: test_mm_cvtsd_si64:
10; SSE:       # %bb.0:
11; SSE-NEXT:    cvtsd2si %xmm0, %rax
12; SSE-NEXT:    retq
13;
14; AVX-LABEL: test_mm_cvtsd_si64:
15; AVX:       # %bb.0:
16; AVX-NEXT:    vcvtsd2si %xmm0, %rax
17; AVX-NEXT:    retq
18  %res = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %a0)
19  ret i64 %res
20}
21declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>) nounwind readnone
22
23define i64 @test_mm_cvtsi128_si64(<2 x i64> %a0) nounwind {
24; SSE-LABEL: test_mm_cvtsi128_si64:
25; SSE:       # %bb.0:
26; SSE-NEXT:    movq %xmm0, %rax
27; SSE-NEXT:    retq
28;
29; AVX-LABEL: test_mm_cvtsi128_si64:
30; AVX:       # %bb.0:
31; AVX-NEXT:    vmovq %xmm0, %rax
32; AVX-NEXT:    retq
33  %res = extractelement <2 x i64> %a0, i32 0
34  ret i64 %res
35}
36
37define <2 x double> @test_mm_cvtsi64_sd(<2 x double> %a0, i64 %a1) nounwind {
38; SSE-LABEL: test_mm_cvtsi64_sd:
39; SSE:       # %bb.0:
40; SSE-NEXT:    cvtsi2sd %rdi, %xmm0
41; SSE-NEXT:    retq
42;
43; AVX-LABEL: test_mm_cvtsi64_sd:
44; AVX:       # %bb.0:
45; AVX-NEXT:    vcvtsi2sd %rdi, %xmm0, %xmm0
46; AVX-NEXT:    retq
47  %res = call <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double> %a0, i64 %a1)
48  ret <2 x double> %res
49}
50declare <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double>, i64) nounwind readnone
51
52define <2 x i64> @test_mm_cvtsi64_si128(i64 %a0) nounwind {
53; SSE-LABEL: test_mm_cvtsi64_si128:
54; SSE:       # %bb.0:
55; SSE-NEXT:    movq %rdi, %xmm0
56; SSE-NEXT:    retq
57;
58; AVX-LABEL: test_mm_cvtsi64_si128:
59; AVX:       # %bb.0:
60; AVX-NEXT:    vmovq %rdi, %xmm0
61; AVX-NEXT:    retq
62  %res0 = insertelement <2 x i64> undef, i64 %a0, i32 0
63  %res1 = insertelement <2 x i64> %res0, i64 0, i32 1
64  ret <2 x i64> %res1
65}
66
67define i64 @test_mm_cvttsd_si64(<2 x double> %a0) nounwind {
68; SSE-LABEL: test_mm_cvttsd_si64:
69; SSE:       # %bb.0:
70; SSE-NEXT:    cvttsd2si %xmm0, %rax
71; SSE-NEXT:    retq
72;
73; AVX-LABEL: test_mm_cvttsd_si64:
74; AVX:       # %bb.0:
75; AVX-NEXT:    vcvttsd2si %xmm0, %rax
76; AVX-NEXT:    retq
77  %res = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %a0)
78  ret i64 %res
79}
80declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) nounwind readnone
81
82define <2 x i64> @test_mm_loadu_si64(i64* %a0) nounwind {
83; SSE-LABEL: test_mm_loadu_si64:
84; SSE:       # %bb.0:
85; SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
86; SSE-NEXT:    retq
87;
88; AVX-LABEL: test_mm_loadu_si64:
89; AVX:       # %bb.0:
90; AVX-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
91; AVX-NEXT:    retq
92  %ld = load i64, i64* %a0, align 1
93  %res0 = insertelement <2 x i64> undef, i64 %ld, i32 0
94  %res1 = insertelement <2 x i64> %res0, i64 0, i32 1
95  ret <2 x i64> %res1
96}
97
98define void @test_mm_stream_si64(i64 *%a0, i64 %a1) {
99; CHECK-LABEL: test_mm_stream_si64:
100; CHECK:       # %bb.0:
101; CHECK-NEXT:    movntiq %rsi, (%rdi)
102; CHECK-NEXT:    retq
103  store i64 %a1, i64* %a0, align 1, !nontemporal !0
104  ret void
105}
106
107!0 = !{i64 1}
108