1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse | FileCheck %s --check-prefix=X32-SSE --check-prefix=X32-SSE1 3; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32-SSE --check-prefix=X32-SSE2 4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-sse2 | FileCheck %s --check-prefix=X64-SSE --check-prefix=X64-SSE1 5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64-SSE --check-prefix=X64-SSE2 6 7; FNEG is defined as subtraction from -0.0. 8 9; This test verifies that we use an xor with a constant to flip the sign bits; no subtraction needed. 10define <4 x float> @t1(<4 x float> %Q) nounwind { 11; X32-SSE-LABEL: t1: 12; X32-SSE: # %bb.0: 13; X32-SSE-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 14; X32-SSE-NEXT: retl 15; 16; X64-SSE-LABEL: t1: 17; X64-SSE: # %bb.0: 18; X64-SSE-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 19; X64-SSE-NEXT: retq 20 %tmp = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %Q 21 ret <4 x float> %tmp 22} 23 24; Possibly misplaced test, but since we're checking undef scenarios... 25 26define float @scalar_fsub_neg0_undef(float %x) nounwind { 27; X32-SSE-LABEL: scalar_fsub_neg0_undef: 28; X32-SSE: # %bb.0: 29; X32-SSE-NEXT: fldz 30; X32-SSE-NEXT: retl 31; 32; X64-SSE-LABEL: scalar_fsub_neg0_undef: 33; X64-SSE: # %bb.0: 34; X64-SSE-NEXT: retq 35 %r = fsub float -0.0, undef 36 ret float %r 37} 38 39define float @scalar_fneg_undef(float %x) nounwind { 40; X32-SSE-LABEL: scalar_fneg_undef: 41; X32-SSE: # %bb.0: 42; X32-SSE-NEXT: fldz 43; X32-SSE-NEXT: retl 44; 45; X64-SSE-LABEL: scalar_fneg_undef: 46; X64-SSE: # %bb.0: 47; X64-SSE-NEXT: retq 48 %r = fneg float undef 49 ret float %r 50} 51 52define <4 x float> @fsub_neg0_undef(<4 x float> %Q) nounwind { 53; X32-SSE-LABEL: fsub_neg0_undef: 54; X32-SSE: # %bb.0: 55; X32-SSE-NEXT: retl 56; 57; X64-SSE-LABEL: fsub_neg0_undef: 58; X64-SSE: # %bb.0: 59; X64-SSE-NEXT: retq 60 %r = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, undef 61 ret <4 x float> %r 62} 63 64define <4 x float> @fneg_undef(<4 x float> %Q) nounwind { 65; X32-SSE-LABEL: fneg_undef: 66; X32-SSE: # %bb.0: 67; X32-SSE-NEXT: retl 68; 69; X64-SSE-LABEL: fneg_undef: 70; X64-SSE: # %bb.0: 71; X64-SSE-NEXT: retq 72 %r = fneg <4 x float> undef 73 ret <4 x float> %r 74} 75 76define <4 x float> @fsub_neg0_undef_elts_undef(<4 x float> %x) { 77; X32-SSE-LABEL: fsub_neg0_undef_elts_undef: 78; X32-SSE: # %bb.0: 79; X32-SSE-NEXT: retl 80; 81; X64-SSE-LABEL: fsub_neg0_undef_elts_undef: 82; X64-SSE: # %bb.0: 83; X64-SSE-NEXT: retq 84 %r = fsub <4 x float> <float -0.0, float undef, float undef, float -0.0>, undef 85 ret <4 x float> %r 86} 87 88; This test verifies that we generate an FP subtraction because "0.0 - x" is not an fneg. 89define <4 x float> @t2(<4 x float> %Q) nounwind { 90; X32-SSE-LABEL: t2: 91; X32-SSE: # %bb.0: 92; X32-SSE-NEXT: xorps %xmm1, %xmm1 93; X32-SSE-NEXT: subps %xmm0, %xmm1 94; X32-SSE-NEXT: movaps %xmm1, %xmm0 95; X32-SSE-NEXT: retl 96; 97; X64-SSE-LABEL: t2: 98; X64-SSE: # %bb.0: 99; X64-SSE-NEXT: xorps %xmm1, %xmm1 100; X64-SSE-NEXT: subps %xmm0, %xmm1 101; X64-SSE-NEXT: movaps %xmm1, %xmm0 102; X64-SSE-NEXT: retq 103 %tmp = fsub <4 x float> zeroinitializer, %Q 104 ret <4 x float> %tmp 105} 106 107; If we're bitcasting an integer to an FP vector, we should avoid the FPU/vector unit entirely. 108; Make sure that we're flipping the sign bit and only the sign bit of each float. 109; So instead of something like this: 110; movd %rdi, %xmm0 111; xorps .LCPI2_0(%rip), %xmm0 112; 113; We should generate: 114; movabsq (put sign bit mask in integer register)) 115; xorq (flip sign bits) 116; movd (move to xmm return register) 117 118define <2 x float> @fneg_bitcast(i64 %i) nounwind { 119; X32-SSE1-LABEL: fneg_bitcast: 120; X32-SSE1: # %bb.0: 121; X32-SSE1-NEXT: pushl %ebp 122; X32-SSE1-NEXT: movl %esp, %ebp 123; X32-SSE1-NEXT: andl $-16, %esp 124; X32-SSE1-NEXT: subl $16, %esp 125; X32-SSE1-NEXT: movl $-2147483648, %eax # imm = 0x80000000 126; X32-SSE1-NEXT: movl 12(%ebp), %ecx 127; X32-SSE1-NEXT: xorl %eax, %ecx 128; X32-SSE1-NEXT: movl %ecx, {{[0-9]+}}(%esp) 129; X32-SSE1-NEXT: xorl 8(%ebp), %eax 130; X32-SSE1-NEXT: movl %eax, (%esp) 131; X32-SSE1-NEXT: movaps (%esp), %xmm0 132; X32-SSE1-NEXT: movl %ebp, %esp 133; X32-SSE1-NEXT: popl %ebp 134; X32-SSE1-NEXT: retl 135; 136; X32-SSE2-LABEL: fneg_bitcast: 137; X32-SSE2: # %bb.0: 138; X32-SSE2-NEXT: movl $-2147483648, %eax # imm = 0x80000000 139; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx 140; X32-SSE2-NEXT: xorl %eax, %ecx 141; X32-SSE2-NEXT: movd %ecx, %xmm1 142; X32-SSE2-NEXT: xorl {{[0-9]+}}(%esp), %eax 143; X32-SSE2-NEXT: movd %eax, %xmm0 144; X32-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] 145; X32-SSE2-NEXT: retl 146; 147; X64-SSE1-LABEL: fneg_bitcast: 148; X64-SSE1: # %bb.0: 149; X64-SSE1-NEXT: movabsq $-9223372034707292160, %rax # imm = 0x8000000080000000 150; X64-SSE1-NEXT: xorq %rdi, %rax 151; X64-SSE1-NEXT: movq %rax, -{{[0-9]+}}(%rsp) 152; X64-SSE1-NEXT: movaps -{{[0-9]+}}(%rsp), %xmm0 153; X64-SSE1-NEXT: retq 154; 155; X64-SSE2-LABEL: fneg_bitcast: 156; X64-SSE2: # %bb.0: 157; X64-SSE2-NEXT: movabsq $-9223372034707292160, %rax # imm = 0x8000000080000000 158; X64-SSE2-NEXT: xorq %rdi, %rax 159; X64-SSE2-NEXT: movq %rax, %xmm0 160; X64-SSE2-NEXT: retq 161 %bitcast = bitcast i64 %i to <2 x float> 162 %fneg = fsub <2 x float> <float -0.0, float -0.0>, %bitcast 163 ret <2 x float> %fneg 164} 165 166define <4 x float> @fneg_undef_elts_v4f32(<4 x float> %x) { 167; X32-SSE-LABEL: fneg_undef_elts_v4f32: 168; X32-SSE: # %bb.0: 169; X32-SSE-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 170; X32-SSE-NEXT: retl 171; 172; X64-SSE-LABEL: fneg_undef_elts_v4f32: 173; X64-SSE: # %bb.0: 174; X64-SSE-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 175; X64-SSE-NEXT: retq 176 %r = fsub <4 x float> <float -0.0, float undef, float undef, float -0.0>, %x 177 ret <4 x float> %r 178} 179 180; This isn't fneg, but similarly check that (X - 0.0) is simplified. 181 182define <4 x float> @fsub0_undef_elts_v4f32(<4 x float> %x) { 183; X32-SSE-LABEL: fsub0_undef_elts_v4f32: 184; X32-SSE: # %bb.0: 185; X32-SSE-NEXT: retl 186; 187; X64-SSE-LABEL: fsub0_undef_elts_v4f32: 188; X64-SSE: # %bb.0: 189; X64-SSE-NEXT: retq 190 %r = fsub <4 x float> %x, <float 0.0, float undef, float 0.0, float undef> 191 ret <4 x float> %r 192} 193 194define <4 x float> @fneg(<4 x float> %Q) nounwind { 195; X32-SSE-LABEL: fneg: 196; X32-SSE: # %bb.0: 197; X32-SSE-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 198; X32-SSE-NEXT: retl 199; 200; X64-SSE-LABEL: fneg: 201; X64-SSE: # %bb.0: 202; X64-SSE-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 203; X64-SSE-NEXT: retq 204 %tmp = fneg <4 x float> %Q 205 ret <4 x float> %tmp 206} 207 208 209