1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ssse3 | FileCheck %s --check-prefix=SSE --check-prefix=SSSE3
4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41
5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
7
8define <4 x i32> @load_zmov_4i32_to_0zzz(<4 x i32> *%ptr) {
9; SSE-LABEL: load_zmov_4i32_to_0zzz:
10; SSE:       # %bb.0: # %entry
11; SSE-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
12; SSE-NEXT:    retq
13;
14; AVX-LABEL: load_zmov_4i32_to_0zzz:
15; AVX:       # %bb.0: # %entry
16; AVX-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
17; AVX-NEXT:    retq
18entry:
19  %X = load <4 x i32>, <4 x i32>* %ptr
20  %Y = shufflevector <4 x i32> %X, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 4, i32 4, i32 4>
21  ret <4 x i32>%Y
22}
23
24define <2 x i64> @load_zmov_2i64_to_0z(<2 x i64> *%ptr) {
25; SSE-LABEL: load_zmov_2i64_to_0z:
26; SSE:       # %bb.0: # %entry
27; SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
28; SSE-NEXT:    retq
29;
30; AVX-LABEL: load_zmov_2i64_to_0z:
31; AVX:       # %bb.0: # %entry
32; AVX-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
33; AVX-NEXT:    retq
34entry:
35  %X = load <2 x i64>, <2 x i64>* %ptr
36  %Y = shufflevector <2 x i64> %X, <2 x i64> zeroinitializer, <2 x i32> <i32 0, i32 2>
37  ret <2 x i64>%Y
38}
39
40define <4 x i32> @load_zmov_4i32_to_0zzz_volatile(<4 x i32> *%ptr) {
41; SSE2-LABEL: load_zmov_4i32_to_0zzz_volatile:
42; SSE2:       # %bb.0: # %entry
43; SSE2-NEXT:    movaps (%rdi), %xmm1
44; SSE2-NEXT:    xorps %xmm0, %xmm0
45; SSE2-NEXT:    movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
46; SSE2-NEXT:    retq
47;
48; SSSE3-LABEL: load_zmov_4i32_to_0zzz_volatile:
49; SSSE3:       # %bb.0: # %entry
50; SSSE3-NEXT:    movaps (%rdi), %xmm1
51; SSSE3-NEXT:    xorps %xmm0, %xmm0
52; SSSE3-NEXT:    movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
53; SSSE3-NEXT:    retq
54;
55; SSE41-LABEL: load_zmov_4i32_to_0zzz_volatile:
56; SSE41:       # %bb.0: # %entry
57; SSE41-NEXT:    movaps (%rdi), %xmm1
58; SSE41-NEXT:    xorps %xmm0, %xmm0
59; SSE41-NEXT:    blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
60; SSE41-NEXT:    retq
61;
62; AVX-LABEL: load_zmov_4i32_to_0zzz_volatile:
63; AVX:       # %bb.0: # %entry
64; AVX-NEXT:    vmovaps (%rdi), %xmm0
65; AVX-NEXT:    vxorps %xmm1, %xmm1, %xmm1
66; AVX-NEXT:    vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
67; AVX-NEXT:    retq
68entry:
69  %X = load volatile <4 x i32>, <4 x i32>* %ptr
70  %Y = shufflevector <4 x i32> %X, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 4, i32 4, i32 4>
71  ret <4 x i32>%Y
72}
73
74define <2 x i64> @load_zmov_2i64_to_0z_volatile(<2 x i64> *%ptr) {
75; SSE-LABEL: load_zmov_2i64_to_0z_volatile:
76; SSE:       # %bb.0: # %entry
77; SSE-NEXT:    movdqa (%rdi), %xmm0
78; SSE-NEXT:    movq {{.*#+}} xmm0 = xmm0[0],zero
79; SSE-NEXT:    retq
80;
81; AVX-LABEL: load_zmov_2i64_to_0z_volatile:
82; AVX:       # %bb.0: # %entry
83; AVX-NEXT:    vmovdqa (%rdi), %xmm0
84; AVX-NEXT:    vmovq {{.*#+}} xmm0 = xmm0[0],zero
85; AVX-NEXT:    retq
86entry:
87  %X = load volatile <2 x i64>, <2 x i64>* %ptr
88  %Y = shufflevector <2 x i64> %X, <2 x i64> zeroinitializer, <2 x i32> <i32 0, i32 2>
89  ret <2 x i64>%Y
90}
91