1// RUN: not llvm-mc -triple=thumbv7 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V7 %s
2// RUN: not llvm-mc -triple=thumbv8 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V8 %s
3
4        // Tests to check handling of sp and pc in thumb mov instructions. We
5        // have to be careful about the order of things, as stdout/stderr
6        // buffering means the errors appear before the non-error output, so
7        // we have to put all the error checks at the top.
8
9        // First check instructions that are never valid. These are thumb2
10        // instructions that uses pc
11
12        // t2MOVr selected because no thumb1 movs that can access high regs
13        movs pc, r0
14        movs r0, pc
15        movs pc, pc
16// CHECK: error: invalid instruction, any one of the following would fix this:
17// CHECK-NEXT: movs pc, r0
18// CHECK: note: operand must be a register in range [r0, r14]
19// CHECK: note: invalid operand for instruction
20// CHECK: error: invalid instruction, any one of the following would fix this:
21// CHECK-NEXT: movs r0, pc
22// CHECK: note: operand must be a register in range [r0, r14]
23// CHECK: note: invalid operand for instruction
24// CHECK: error: invalid operand for instruction
25// CHECK-NEXT: movs pc, pc
26
27        // mov.w selects t2MOVr
28        mov.w pc, r0
29        mov.w r0, pc
30        mov.w pc, pc
31// CHECK: error: operand must be a register in range [r0, r14]
32// CHECK-NEXT: mov.w pc, r0
33// CHECK: note: operand must be a register in range [r0, r14]
34// CHECK-NEXT: mov.w r0, pc
35// CHECK: note: invalid operand for instruction
36// CHECK-NEXT: mov.w r0, pc
37// CHECK: error: invalid instruction
38// CHECK-NEXT: mov.w pc, pc
39
40        // movs.w selects t2MOVr
41        movs.w pc, r0
42        movs.w r0, pc
43        movs.w pc, pc
44// CHECK: error: invalid instruction, any one of the following would fix this:
45// CHECK-NEXT: movs.w pc, r0
46// CHECK: note: operand must be a register in range [r0, r14]
47// CHECK: note: invalid operand for instruction
48// CHECK: error: invalid instruction, any one of the following would fix this:
49// CHECK-NEXT: movs.w r0, pc
50// CHECK: note: operand must be a register in range [r0, r14]
51// CHECK: note: invalid operand for instruction
52// CHECK: error: invalid operand for instruction
53// CHECK-NEXT: movs.w pc, pc
54
55
56        // Now check instructions that are invalid before ARMv8 due to SP usage
57
58        movs sp, r0
59        movs r0, sp
60        movs sp, sp
61// CHECK-V7: error: instruction variant requires ARMv8 or later
62// CHECK-V7-NEXT: movs sp, r0
63// CHECK-V7: instruction variant requires ARMv8 or later
64// CHECK-V7-NEXT: movs r0, sp
65// CHECK-V7: error: instruction variant requires ARMv8 or later
66// CHECK-V7-NEXT: movs sp, sp
67// CHECK-V8: movs.w sp, r0            @ encoding: [0x5f,0xea,0x00,0x0d]
68// CHECK-V8: movs.w r0, sp            @ encoding: [0x5f,0xea,0x0d,0x00]
69// CHECK-V8: movs.w sp, sp            @ encoding: [0x5f,0xea,0x0d,0x0d]
70
71        mov.w sp, sp
72// CHECK-V7: error: instruction variant requires ARMv8 or later
73// CHECK-V7-NEXT: mov.w sp, sp
74// CHECK-V8: mov.w sp, sp             @ encoding: [0x4f,0xea,0x0d,0x0d]
75
76        movs.w sp, r0
77        movs.w r0, sp
78        movs.w sp, sp
79// CHECK-V7: error: instruction variant requires ARMv8 or later
80// CHECK-V7-NEXT: movs.w sp, r0
81// CHECK-V7: instruction variant requires ARMv8 or later
82// CHECK-V7-NEXT: movs.w r0, sp
83// CHECK-V7: error: instruction variant requires ARMv8 or later
84// CHECK-V7-NEXT: movs.w sp, sp
85// CHECK-V8: movs.w sp, r0            @ encoding: [0x5f,0xea,0x00,0x0d]
86// CHECK-V8: movs.w r0, sp            @ encoding: [0x5f,0xea,0x0d,0x00]
87// CHECK-V8: movs.w sp, sp            @ encoding: [0x5f,0xea,0x0d,0x0d]
88
89
90        // Now instructions that are always valid
91
92        // mov selects tMOVr, where sp and pc are allowed
93        mov sp, r0
94        mov r0, sp
95        mov sp, sp
96        mov pc, r0
97        mov r0, pc
98        mov pc, pc
99// CHECK: mov sp, r0                  @ encoding: [0x85,0x46]
100// CHECK: mov r0, sp                  @ encoding: [0x68,0x46]
101// CHECK: mov sp, sp                  @ encoding: [0xed,0x46]
102// CHECK: mov pc, r0                  @ encoding: [0x87,0x46]
103// CHECK: mov r0, pc                  @ encoding: [0x78,0x46]
104// CHECK: mov pc, pc                  @ encoding: [0xff,0x46]
105
106        // sp allowed in non-flags-setting t2MOVr
107        mov.w sp, r0
108        mov.w r0, sp
109// CHECK: mov.w sp, r0                @ encoding: [0x4f,0xea,0x00,0x0d]
110// CHECK: mov.w r0, sp                @ encoding: [0x4f,0xea,0x0d,0x00]
111
112        // `movs pc, lr` is an alias for `subs pc, lr, #0`/`eret`.
113        movs   pc, lr
114        movs.w pc, lr
115// CHECK-V7: subs pc, lr, #0             @ encoding: [0xde,0xf3,0x00,0x8f]
116// CHECK-V7: subs pc, lr, #0             @ encoding: [0xde,0xf3,0x00,0x8f]
117// CHECK-V8: eret                        @ encoding: [0xde,0xf3,0x00,0x8f]
118// CHECK-V8: eret                        @ encoding: [0xde,0xf3,0x00,0x8f]
119