1//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the ARM instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// ARM specific DAG Nodes. 16// 17 18// Type profiles. 19def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>, 20 SDTCisVT<1, i32> ]>; 21def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; 22def SDT_ARMStructByVal : SDTypeProfile<0, 4, 23 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 24 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 25 26def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; 27 28def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 29 30def SDT_ARMCMov : SDTypeProfile<1, 3, 31 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 32 SDTCisVT<3, i32>]>; 33 34def SDT_ARMBrcond : SDTypeProfile<0, 2, 35 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 36 37def SDT_ARMBrJT : SDTypeProfile<0, 2, 38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; 39 40def SDT_ARMBr2JT : SDTypeProfile<0, 3, 41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 42 SDTCisVT<2, i32>]>; 43 44def SDT_ARMBCC_i64 : SDTypeProfile<0, 6, 45 [SDTCisVT<0, i32>, 46 SDTCisVT<1, i32>, SDTCisVT<2, i32>, 47 SDTCisVT<3, i32>, SDTCisVT<4, i32>, 48 SDTCisVT<5, OtherVT>]>; 49 50def SDT_ARMAnd : SDTypeProfile<1, 2, 51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 52 SDTCisVT<2, i32>]>; 53 54def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 55def SDT_ARMFCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, 56 SDTCisVT<2, i32>]>; 57 58def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 59 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>; 60 61def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 62def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>, 63 SDTCisInt<2>]>; 64def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>; 65def SDT_ARMEH_SJLJ_SetupDispatch: SDTypeProfile<0, 0, []>; 66 67def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 68 69def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, 70 SDTCisInt<1>]>; 71 72def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 73 74def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 75 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 76 77def SDT_WIN__DBZCHK : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 78 79def SDT_ARMMEMCPY : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 80 SDTCisVT<2, i32>, SDTCisVT<3, i32>, 81 SDTCisVT<4, i32>]>; 82 83def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 84 [SDTCisSameAs<0, 2>, 85 SDTCisSameAs<0, 3>, 86 SDTCisInt<0>, SDTCisVT<1, i32>]>; 87 88// SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR 89def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 90 [SDTCisSameAs<0, 2>, 91 SDTCisSameAs<0, 3>, 92 SDTCisInt<0>, 93 SDTCisVT<1, i32>, 94 SDTCisVT<4, i32>]>; 95 96def SDT_LongMac : SDTypeProfile<2, 4, [SDTCisVT<0, i32>, 97 SDTCisSameAs<0, 1>, 98 SDTCisSameAs<0, 2>, 99 SDTCisSameAs<0, 3>, 100 SDTCisSameAs<0, 4>, 101 SDTCisSameAs<0, 5>]>; 102 103def ARMSmlald : SDNode<"ARMISD::SMLALD", SDT_LongMac>; 104def ARMSmlaldx : SDNode<"ARMISD::SMLALDX", SDT_LongMac>; 105def ARMSmlsld : SDNode<"ARMISD::SMLSLD", SDT_LongMac>; 106def ARMSmlsldx : SDNode<"ARMISD::SMLSLDX", SDT_LongMac>; 107 108def SDT_MulHSR : SDTypeProfile<1, 3, [SDTCisVT<0,i32>, 109 SDTCisSameAs<0, 1>, 110 SDTCisSameAs<0, 2>, 111 SDTCisSameAs<0, 3>]>; 112 113def ARMsmmlar : SDNode<"ARMISD::SMMLAR", SDT_MulHSR>; 114def ARMsmmlsr : SDNode<"ARMISD::SMMLSR", SDT_MulHSR>; 115 116// Node definitions. 117def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; 118def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>; 119def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntUnaryOp>; 120 121def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart, 122 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 123def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd, 124 [SDNPHasChain, SDNPSideEffect, 125 SDNPOptInGlue, SDNPOutGlue]>; 126def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" , 127 SDT_ARMStructByVal, 128 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 129 SDNPMayStore, SDNPMayLoad]>; 130 131def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, 132 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 133 SDNPVariadic]>; 134def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall, 135 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 136 SDNPVariadic]>; 137def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, 138 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 139 SDNPVariadic]>; 140 141def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, 142 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 143def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall, 144 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 145def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, 146 [SDNPInGlue]>; 147 148def ARMssatnoshift : SDNode<"ARMISD::SSAT", SDTIntSatNoShOp, []>; 149 150def ARMusatnoshift : SDNode<"ARMISD::USAT", SDTIntSatNoShOp, []>; 151 152def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond, 153 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 154 155def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT, 156 [SDNPHasChain]>; 157def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT, 158 [SDNPHasChain]>; 159 160def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64, 161 [SDNPHasChain]>; 162 163def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, 164 [SDNPOutGlue]>; 165 166def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp, 167 [SDNPOutGlue]>; 168 169def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp, 170 [SDNPOutGlue, SDNPCommutative]>; 171 172def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>; 173 174def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 175def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 176def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>; 177 178def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags, 179 [SDNPCommutative]>; 180def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>; 181def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>; 182def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>; 183 184def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; 185def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", 186 SDT_ARMEH_SJLJ_Setjmp, 187 [SDNPHasChain, SDNPSideEffect]>; 188def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP", 189 SDT_ARMEH_SJLJ_Longjmp, 190 [SDNPHasChain, SDNPSideEffect]>; 191def ARMeh_sjlj_setup_dispatch: SDNode<"ARMISD::EH_SJLJ_SETUP_DISPATCH", 192 SDT_ARMEH_SJLJ_SetupDispatch, 193 [SDNPHasChain, SDNPSideEffect]>; 194 195def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER, 196 [SDNPHasChain, SDNPSideEffect]>; 197def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH, 198 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; 199 200def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET, 201 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 202 203def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>; 204 205def ARMmemcopy : SDNode<"ARMISD::MEMCPY", SDT_ARMMEMCPY, 206 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 207 SDNPMayStore, SDNPMayLoad]>; 208 209def ARMsmulwb : SDNode<"ARMISD::SMULWB", SDTIntBinOp, []>; 210def ARMsmulwt : SDNode<"ARMISD::SMULWT", SDTIntBinOp, []>; 211def ARMsmlalbb : SDNode<"ARMISD::SMLALBB", SDT_LongMac, []>; 212def ARMsmlalbt : SDNode<"ARMISD::SMLALBT", SDT_LongMac, []>; 213def ARMsmlaltb : SDNode<"ARMISD::SMLALTB", SDT_LongMac, []>; 214def ARMsmlaltt : SDNode<"ARMISD::SMLALTT", SDT_LongMac, []>; 215 216//===----------------------------------------------------------------------===// 217// ARM Instruction Predicate Definitions. 218// 219def HasV4T : Predicate<"Subtarget->hasV4TOps()">, 220 AssemblerPredicate<"HasV4TOps", "armv4t">; 221def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; 222def HasV5T : Predicate<"Subtarget->hasV5TOps()">, 223 AssemblerPredicate<"HasV5TOps", "armv5t">; 224def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, 225 AssemblerPredicate<"HasV5TEOps", "armv5te">; 226def HasV6 : Predicate<"Subtarget->hasV6Ops()">, 227 AssemblerPredicate<"HasV6Ops", "armv6">; 228def NoV6 : Predicate<"!Subtarget->hasV6Ops()">; 229def HasV6M : Predicate<"Subtarget->hasV6MOps()">, 230 AssemblerPredicate<"HasV6MOps", 231 "armv6m or armv6t2">; 232def HasV8MBaseline : Predicate<"Subtarget->hasV8MBaselineOps()">, 233 AssemblerPredicate<"HasV8MBaselineOps", 234 "armv8m.base">; 235def HasV8MMainline : Predicate<"Subtarget->hasV8MMainlineOps()">, 236 AssemblerPredicate<"HasV8MMainlineOps", 237 "armv8m.main">; 238def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, 239 AssemblerPredicate<"HasV6T2Ops", "armv6t2">; 240def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">; 241def HasV6K : Predicate<"Subtarget->hasV6KOps()">, 242 AssemblerPredicate<"HasV6KOps", "armv6k">; 243def NoV6K : Predicate<"!Subtarget->hasV6KOps()">; 244def HasV7 : Predicate<"Subtarget->hasV7Ops()">, 245 AssemblerPredicate<"HasV7Ops", "armv7">; 246def HasV8 : Predicate<"Subtarget->hasV8Ops()">, 247 AssemblerPredicate<"HasV8Ops", "armv8">; 248def PreV8 : Predicate<"!Subtarget->hasV8Ops()">, 249 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">; 250def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">, 251 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">; 252def HasV8_2a : Predicate<"Subtarget->hasV8_2aOps()">, 253 AssemblerPredicate<"HasV8_2aOps", "armv8.2a">; 254def HasV8_3a : Predicate<"Subtarget->hasV8_3aOps()">, 255 AssemblerPredicate<"HasV8_3aOps", "armv8.3a">; 256def HasV8_4a : Predicate<"Subtarget->hasV8_4aOps()">, 257 AssemblerPredicate<"HasV8_4aOps", "armv8.4a">; 258def NoVFP : Predicate<"!Subtarget->hasVFP2()">; 259def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, 260 AssemblerPredicate<"FeatureVFP2", "VFP2">; 261def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, 262 AssemblerPredicate<"FeatureVFP3", "VFP3">; 263def HasVFP4 : Predicate<"Subtarget->hasVFP4()">, 264 AssemblerPredicate<"FeatureVFP4", "VFP4">; 265def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">, 266 AssemblerPredicate<"!FeatureVFPOnlySP", 267 "double precision VFP">; 268def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">, 269 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">; 270def HasNEON : Predicate<"Subtarget->hasNEON()">, 271 AssemblerPredicate<"FeatureNEON", "NEON">; 272def HasSHA2 : Predicate<"Subtarget->hasSHA2()">, 273 AssemblerPredicate<"FeatureSHA2", "sha2">; 274def HasAES : Predicate<"Subtarget->hasAES()">, 275 AssemblerPredicate<"FeatureAES", "aes">; 276def HasCrypto : Predicate<"Subtarget->hasCrypto()">, 277 AssemblerPredicate<"FeatureCrypto", "crypto">; 278def HasDotProd : Predicate<"Subtarget->hasDotProd()">, 279 AssemblerPredicate<"FeatureDotProd", "dotprod">; 280def HasCRC : Predicate<"Subtarget->hasCRC()">, 281 AssemblerPredicate<"FeatureCRC", "crc">; 282def HasRAS : Predicate<"Subtarget->hasRAS()">, 283 AssemblerPredicate<"FeatureRAS", "ras">; 284def HasFP16 : Predicate<"Subtarget->hasFP16()">, 285 AssemblerPredicate<"FeatureFP16","half-float conversions">; 286def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">, 287 AssemblerPredicate<"FeatureFullFP16","full half-float">; 288def HasDivideInThumb : Predicate<"Subtarget->hasDivideInThumbMode()">, 289 AssemblerPredicate<"FeatureHWDivThumb", "divide in THUMB">; 290def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">, 291 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">; 292def HasDSP : Predicate<"Subtarget->hasDSP()">, 293 AssemblerPredicate<"FeatureDSP", "dsp">; 294def HasDB : Predicate<"Subtarget->hasDataBarrier()">, 295 AssemblerPredicate<"FeatureDB", 296 "data-barriers">; 297def HasDFB : Predicate<"Subtarget->hasFullDataBarrier()">, 298 AssemblerPredicate<"FeatureDFB", 299 "full-data-barrier">; 300def HasV7Clrex : Predicate<"Subtarget->hasV7Clrex()">, 301 AssemblerPredicate<"FeatureV7Clrex", 302 "v7 clrex">; 303def HasAcquireRelease : Predicate<"Subtarget->hasAcquireRelease()">, 304 AssemblerPredicate<"FeatureAcquireRelease", 305 "acquire/release">; 306def HasMP : Predicate<"Subtarget->hasMPExtension()">, 307 AssemblerPredicate<"FeatureMP", 308 "mp-extensions">; 309def HasVirtualization: Predicate<"false">, 310 AssemblerPredicate<"FeatureVirtualization", 311 "virtualization-extensions">; 312def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">, 313 AssemblerPredicate<"FeatureTrustZone", 314 "TrustZone">; 315def Has8MSecExt : Predicate<"Subtarget->has8MSecExt()">, 316 AssemblerPredicate<"Feature8MSecExt", 317 "ARMv8-M Security Extensions">; 318def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">; 319def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; 320def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; 321def IsThumb : Predicate<"Subtarget->isThumb()">, 322 AssemblerPredicate<"ModeThumb", "thumb">; 323def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; 324def IsThumb2 : Predicate<"Subtarget->isThumb2()">, 325 AssemblerPredicate<"ModeThumb,FeatureThumb2", 326 "thumb2">; 327def IsMClass : Predicate<"Subtarget->isMClass()">, 328 AssemblerPredicate<"FeatureMClass", "armv*m">; 329def IsNotMClass : Predicate<"!Subtarget->isMClass()">, 330 AssemblerPredicate<"!FeatureMClass", 331 "!armv*m">; 332def IsARM : Predicate<"!Subtarget->isThumb()">, 333 AssemblerPredicate<"!ModeThumb", "arm-mode">; 334def IsMachO : Predicate<"Subtarget->isTargetMachO()">; 335def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">; 336def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; 337def IsWindows : Predicate<"Subtarget->isTargetWindows()">; 338def IsNotWindows : Predicate<"!Subtarget->isTargetWindows()">; 339def IsReadTPHard : Predicate<"Subtarget->isReadTPHard()">; 340def IsReadTPSoft : Predicate<"!Subtarget->isReadTPHard()">; 341def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">, 342 AssemblerPredicate<"FeatureNaClTrap", "NaCl">; 343def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">; 344 345def UseNegativeImmediates : 346 Predicate<"false">, 347 AssemblerPredicate<"!FeatureNoNegativeImmediates", 348 "NegativeImmediates">; 349 350// FIXME: Eventually this will be just "hasV6T2Ops". 351let RecomputePerFunction = 1 in { 352 def UseMovt : Predicate<"Subtarget->useMovt(*MF)">; 353 def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">; 354 def UseMovtInPic : Predicate<"Subtarget->useMovt(*MF) && Subtarget->allowPositionIndependentMovt()">; 355 def DontUseMovtInPic : Predicate<"!Subtarget->useMovt(*MF) || !Subtarget->allowPositionIndependentMovt()">; 356} 357def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">; 358def UseMulOps : Predicate<"Subtarget->useMulOps()">; 359 360// Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available. 361// But only select them if more precision in FP computation is allowed. 362// Do not use them for Darwin platforms. 363def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion ==" 364 " FPOpFusion::Fast && " 365 " Subtarget->hasVFP4()) && " 366 "!Subtarget->isTargetDarwin()">; 367def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion ==" 368 " FPOpFusion::Fast &&" 369 " Subtarget->hasVFP4()) || " 370 "Subtarget->isTargetDarwin()">; 371 372def HasFastVGETLNi32 : Predicate<"!Subtarget->hasSlowVGETLNi32()">; 373def HasSlowVGETLNi32 : Predicate<"Subtarget->hasSlowVGETLNi32()">; 374 375def HasFastVDUP32 : Predicate<"!Subtarget->hasSlowVDUP32()">; 376def HasSlowVDUP32 : Predicate<"Subtarget->hasSlowVDUP32()">; 377 378def UseVMOVSR : Predicate<"Subtarget->preferVMOVSR() ||" 379 "!Subtarget->useNEONForSinglePrecisionFP()">; 380def DontUseVMOVSR : Predicate<"!Subtarget->preferVMOVSR() &&" 381 "Subtarget->useNEONForSinglePrecisionFP()">; 382 383let RecomputePerFunction = 1 in { 384 def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">; 385 def IsBE : Predicate<"MF->getDataLayout().isBigEndian()">; 386} 387 388def GenExecuteOnly : Predicate<"Subtarget->genExecuteOnly()">; 389 390//===----------------------------------------------------------------------===// 391// ARM Flag Definitions. 392 393class RegConstraint<string C> { 394 string Constraints = C; 395} 396 397//===----------------------------------------------------------------------===// 398// ARM specific transformation functions and pattern fragments. 399// 400 401// imm_neg_XFORM - Return the negation of an i32 immediate value. 402def imm_neg_XFORM : SDNodeXForm<imm, [{ 403 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32); 404}]>; 405 406// imm_not_XFORM - Return the complement of a i32 immediate value. 407def imm_not_XFORM : SDNodeXForm<imm, [{ 408 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32); 409}]>; 410 411/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. 412def imm16_31 : ImmLeaf<i32, [{ 413 return (int32_t)Imm >= 16 && (int32_t)Imm < 32; 414}]>; 415 416// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. 417def sext_16_node : PatLeaf<(i32 GPR:$a), [{ 418 if (CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17) 419 return true; 420 421 if (N->getOpcode() != ISD::SRA) 422 return false; 423 if (N->getOperand(0).getOpcode() != ISD::SHL) 424 return false; 425 426 auto *ShiftVal = dyn_cast<ConstantSDNode>(N->getOperand(1)); 427 if (!ShiftVal || ShiftVal->getZExtValue() != 16) 428 return false; 429 430 ShiftVal = dyn_cast<ConstantSDNode>(N->getOperand(0)->getOperand(1)); 431 if (!ShiftVal || ShiftVal->getZExtValue() != 16) 432 return false; 433 434 return true; 435}]>; 436 437/// Split a 32-bit immediate into two 16 bit parts. 438def hi16 : SDNodeXForm<imm, [{ 439 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N), 440 MVT::i32); 441}]>; 442 443def lo16AllZero : PatLeaf<(i32 imm), [{ 444 // Returns true if all low 16-bits are 0. 445 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0; 446}], hi16>; 447 448class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; 449class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>; 450 451// An 'and' node with a single use. 452def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 453 return N->hasOneUse(); 454}]>; 455 456// An 'xor' node with a single use. 457def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{ 458 return N->hasOneUse(); 459}]>; 460 461// An 'fmul' node with a single use. 462def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{ 463 return N->hasOneUse(); 464}]>; 465 466// An 'fadd' node which checks for single non-hazardous use. 467def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{ 468 return hasNoVMLxHazardUse(N); 469}]>; 470 471// An 'fsub' node which checks for single non-hazardous use. 472def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{ 473 return hasNoVMLxHazardUse(N); 474}]>; 475 476//===----------------------------------------------------------------------===// 477// Operand Definitions. 478// 479 480// Immediate operands with a shared generic asm render method. 481class ImmAsmOperand<int Low, int High> : AsmOperandClass { 482 let RenderMethod = "addImmOperands"; 483 let PredicateMethod = "isImmediate<" # Low # "," # High # ">"; 484 let DiagnosticString = "operand must be an immediate in the range [" # Low # "," # High # "]"; 485} 486 487class ImmAsmOperandMinusOne<int Low, int High> : AsmOperandClass { 488 let PredicateMethod = "isImmediate<" # Low # "," # High # ">"; 489 let DiagnosticType = "ImmRange" # Low # "_" # High; 490 let DiagnosticString = "operand must be an immediate in the range [" # Low # "," # High # "]"; 491} 492 493// Operands that are part of a memory addressing mode. 494class MemOperand : Operand<i32> { let OperandType = "OPERAND_MEMORY"; } 495 496// Branch target. 497// FIXME: rename brtarget to t2_brtarget 498def brtarget : Operand<OtherVT> { 499 let EncoderMethod = "getBranchTargetOpValue"; 500 let OperandType = "OPERAND_PCREL"; 501 let DecoderMethod = "DecodeT2BROperand"; 502} 503 504// Branches targeting ARM-mode must be divisible by 4 if they're a raw 505// immediate. 506def ARMBranchTarget : AsmOperandClass { 507 let Name = "ARMBranchTarget"; 508} 509 510// Branches targeting Thumb-mode must be divisible by 2 if they're a raw 511// immediate. 512def ThumbBranchTarget : AsmOperandClass { 513 let Name = "ThumbBranchTarget"; 514} 515 516def arm_br_target : Operand<OtherVT> { 517 let ParserMatchClass = ARMBranchTarget; 518 let EncoderMethod = "getARMBranchTargetOpValue"; 519 let OperandType = "OPERAND_PCREL"; 520} 521 522// Call target for ARM. Handles conditional/unconditional 523// FIXME: rename bl_target to t2_bltarget? 524def arm_bl_target : Operand<i32> { 525 let ParserMatchClass = ARMBranchTarget; 526 let EncoderMethod = "getARMBLTargetOpValue"; 527 let OperandType = "OPERAND_PCREL"; 528} 529 530// Target for BLX *from* ARM mode. 531def arm_blx_target : Operand<i32> { 532 let ParserMatchClass = ThumbBranchTarget; 533 let EncoderMethod = "getARMBLXTargetOpValue"; 534 let OperandType = "OPERAND_PCREL"; 535} 536 537// A list of registers separated by comma. Used by load/store multiple. 538def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; } 539def reglist : Operand<i32> { 540 let EncoderMethod = "getRegisterListOpValue"; 541 let ParserMatchClass = RegListAsmOperand; 542 let PrintMethod = "printRegisterList"; 543 let DecoderMethod = "DecodeRegListOperand"; 544} 545 546def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">; 547 548def DPRRegListAsmOperand : AsmOperandClass { 549 let Name = "DPRRegList"; 550 let DiagnosticType = "DPR_RegList"; 551} 552def dpr_reglist : Operand<i32> { 553 let EncoderMethod = "getRegisterListOpValue"; 554 let ParserMatchClass = DPRRegListAsmOperand; 555 let PrintMethod = "printRegisterList"; 556 let DecoderMethod = "DecodeDPRRegListOperand"; 557} 558 559def SPRRegListAsmOperand : AsmOperandClass { 560 let Name = "SPRRegList"; 561 let DiagnosticString = "operand must be a list of registers in range [s0, s31]"; 562} 563def spr_reglist : Operand<i32> { 564 let EncoderMethod = "getRegisterListOpValue"; 565 let ParserMatchClass = SPRRegListAsmOperand; 566 let PrintMethod = "printRegisterList"; 567 let DecoderMethod = "DecodeSPRRegListOperand"; 568} 569 570// An operand for the CONSTPOOL_ENTRY pseudo-instruction. 571def cpinst_operand : Operand<i32> { 572 let PrintMethod = "printCPInstOperand"; 573} 574 575// Local PC labels. 576def pclabel : Operand<i32> { 577 let PrintMethod = "printPCLabel"; 578} 579 580// ADR instruction labels. 581def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; } 582def adrlabel : Operand<i32> { 583 let EncoderMethod = "getAdrLabelOpValue"; 584 let ParserMatchClass = AdrLabelAsmOperand; 585 let PrintMethod = "printAdrLabelOperand<0>"; 586} 587 588def neon_vcvt_imm32 : Operand<i32> { 589 let EncoderMethod = "getNEONVcvtImm32OpValue"; 590 let DecoderMethod = "DecodeVCVTImmOperand"; 591} 592 593// rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24. 594def rot_imm_XFORM: SDNodeXForm<imm, [{ 595 switch (N->getZExtValue()){ 596 default: llvm_unreachable(nullptr); 597 case 0: return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32); 598 case 8: return CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32); 599 case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32); 600 case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32); 601 } 602}]>; 603def RotImmAsmOperand : AsmOperandClass { 604 let Name = "RotImm"; 605 let ParserMethod = "parseRotImm"; 606} 607def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{ 608 int32_t v = N->getZExtValue(); 609 return v == 8 || v == 16 || v == 24; }], 610 rot_imm_XFORM> { 611 let PrintMethod = "printRotImmOperand"; 612 let ParserMatchClass = RotImmAsmOperand; 613} 614 615// shift_imm: An integer that encodes a shift amount and the type of shift 616// (asr or lsl). The 6-bit immediate encodes as: 617// {5} 0 ==> lsl 618// 1 asr 619// {4-0} imm5 shift amount. 620// asr #32 encoded as imm5 == 0. 621def ShifterImmAsmOperand : AsmOperandClass { 622 let Name = "ShifterImm"; 623 let ParserMethod = "parseShifterImm"; 624} 625def shift_imm : Operand<i32> { 626 let PrintMethod = "printShiftImmOperand"; 627 let ParserMatchClass = ShifterImmAsmOperand; 628} 629 630// shifter_operand operands: so_reg_reg, so_reg_imm, and mod_imm. 631def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; } 632def so_reg_reg : Operand<i32>, // reg reg imm 633 ComplexPattern<i32, 3, "SelectRegShifterOperand", 634 [shl, srl, sra, rotr]> { 635 let EncoderMethod = "getSORegRegOpValue"; 636 let PrintMethod = "printSORegRegOperand"; 637 let DecoderMethod = "DecodeSORegRegOperand"; 638 let ParserMatchClass = ShiftedRegAsmOperand; 639 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm); 640} 641 642def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; } 643def so_reg_imm : Operand<i32>, // reg imm 644 ComplexPattern<i32, 2, "SelectImmShifterOperand", 645 [shl, srl, sra, rotr]> { 646 let EncoderMethod = "getSORegImmOpValue"; 647 let PrintMethod = "printSORegImmOperand"; 648 let DecoderMethod = "DecodeSORegImmOperand"; 649 let ParserMatchClass = ShiftedImmAsmOperand; 650 let MIOperandInfo = (ops GPR, i32imm); 651} 652 653// FIXME: Does this need to be distinct from so_reg? 654def shift_so_reg_reg : Operand<i32>, // reg reg imm 655 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand", 656 [shl,srl,sra,rotr]> { 657 let EncoderMethod = "getSORegRegOpValue"; 658 let PrintMethod = "printSORegRegOperand"; 659 let DecoderMethod = "DecodeSORegRegOperand"; 660 let ParserMatchClass = ShiftedRegAsmOperand; 661 let MIOperandInfo = (ops GPR, GPR, i32imm); 662} 663 664// FIXME: Does this need to be distinct from so_reg? 665def shift_so_reg_imm : Operand<i32>, // reg reg imm 666 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand", 667 [shl,srl,sra,rotr]> { 668 let EncoderMethod = "getSORegImmOpValue"; 669 let PrintMethod = "printSORegImmOperand"; 670 let DecoderMethod = "DecodeSORegImmOperand"; 671 let ParserMatchClass = ShiftedImmAsmOperand; 672 let MIOperandInfo = (ops GPR, i32imm); 673} 674 675// mod_imm: match a 32-bit immediate operand, which can be encoded into 676// a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM 677// - "Modified Immediate Constants"). Within the MC layer we keep this 678// immediate in its encoded form. 679def ModImmAsmOperand: AsmOperandClass { 680 let Name = "ModImm"; 681 let ParserMethod = "parseModImm"; 682} 683def mod_imm : Operand<i32>, ImmLeaf<i32, [{ 684 return ARM_AM::getSOImmVal(Imm) != -1; 685 }]> { 686 let EncoderMethod = "getModImmOpValue"; 687 let PrintMethod = "printModImmOperand"; 688 let ParserMatchClass = ModImmAsmOperand; 689} 690 691// Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder 692// method and such, as they are only used on aliases (Pat<> and InstAlias<>). 693// The actual parsing, encoding, decoding are handled by the destination 694// instructions, which use mod_imm. 695 696def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; } 697def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{ 698 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1; 699 }], imm_not_XFORM> { 700 let ParserMatchClass = ModImmNotAsmOperand; 701} 702 703def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; } 704def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{ 705 unsigned Value = -(unsigned)N->getZExtValue(); 706 return Value && ARM_AM::getSOImmVal(Value) != -1; 707 }], imm_neg_XFORM> { 708 let ParserMatchClass = ModImmNegAsmOperand; 709} 710 711/// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal() 712def arm_i32imm : PatLeaf<(imm), [{ 713 if (Subtarget->useMovt(*MF)) 714 return true; 715 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); 716}]>; 717 718/// imm0_1 predicate - Immediate in the range [0,1]. 719def Imm0_1AsmOperand: ImmAsmOperand<0,1> { let Name = "Imm0_1"; } 720def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; } 721 722/// imm0_3 predicate - Immediate in the range [0,3]. 723def Imm0_3AsmOperand: ImmAsmOperand<0,3> { let Name = "Imm0_3"; } 724def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; } 725 726/// imm0_7 predicate - Immediate in the range [0,7]. 727def Imm0_7AsmOperand: ImmAsmOperand<0,7> { 728 let Name = "Imm0_7"; 729} 730def imm0_7 : Operand<i32>, ImmLeaf<i32, [{ 731 return Imm >= 0 && Imm < 8; 732}]> { 733 let ParserMatchClass = Imm0_7AsmOperand; 734} 735 736/// imm8_255 predicate - Immediate in the range [8,255]. 737def Imm8_255AsmOperand: ImmAsmOperand<8,255> { let Name = "Imm8_255"; } 738def imm8_255 : Operand<i32>, ImmLeaf<i32, [{ 739 return Imm >= 8 && Imm < 256; 740}]> { 741 let ParserMatchClass = Imm8_255AsmOperand; 742} 743 744/// imm8 predicate - Immediate is exactly 8. 745def Imm8AsmOperand: ImmAsmOperand<8,8> { let Name = "Imm8"; } 746def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> { 747 let ParserMatchClass = Imm8AsmOperand; 748} 749 750/// imm16 predicate - Immediate is exactly 16. 751def Imm16AsmOperand: ImmAsmOperand<16,16> { let Name = "Imm16"; } 752def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> { 753 let ParserMatchClass = Imm16AsmOperand; 754} 755 756/// imm32 predicate - Immediate is exactly 32. 757def Imm32AsmOperand: ImmAsmOperand<32,32> { let Name = "Imm32"; } 758def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> { 759 let ParserMatchClass = Imm32AsmOperand; 760} 761 762def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>; 763 764/// imm1_7 predicate - Immediate in the range [1,7]. 765def Imm1_7AsmOperand: ImmAsmOperand<1,7> { let Name = "Imm1_7"; } 766def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> { 767 let ParserMatchClass = Imm1_7AsmOperand; 768} 769 770/// imm1_15 predicate - Immediate in the range [1,15]. 771def Imm1_15AsmOperand: ImmAsmOperand<1,15> { let Name = "Imm1_15"; } 772def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> { 773 let ParserMatchClass = Imm1_15AsmOperand; 774} 775 776/// imm1_31 predicate - Immediate in the range [1,31]. 777def Imm1_31AsmOperand: ImmAsmOperand<1,31> { let Name = "Imm1_31"; } 778def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> { 779 let ParserMatchClass = Imm1_31AsmOperand; 780} 781 782/// imm0_15 predicate - Immediate in the range [0,15]. 783def Imm0_15AsmOperand: ImmAsmOperand<0,15> { 784 let Name = "Imm0_15"; 785} 786def imm0_15 : Operand<i32>, ImmLeaf<i32, [{ 787 return Imm >= 0 && Imm < 16; 788}]> { 789 let ParserMatchClass = Imm0_15AsmOperand; 790} 791 792/// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31]. 793def Imm0_31AsmOperand: ImmAsmOperand<0,31> { let Name = "Imm0_31"; } 794def imm0_31 : Operand<i32>, ImmLeaf<i32, [{ 795 return Imm >= 0 && Imm < 32; 796}]> { 797 let ParserMatchClass = Imm0_31AsmOperand; 798} 799 800/// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32]. 801def Imm0_32AsmOperand: ImmAsmOperand<0,32> { let Name = "Imm0_32"; } 802def imm0_32 : Operand<i32>, ImmLeaf<i32, [{ 803 return Imm >= 0 && Imm < 33; 804}]> { 805 let ParserMatchClass = Imm0_32AsmOperand; 806} 807 808/// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63]. 809def Imm0_63AsmOperand: ImmAsmOperand<0,63> { let Name = "Imm0_63"; } 810def imm0_63 : Operand<i32>, ImmLeaf<i32, [{ 811 return Imm >= 0 && Imm < 64; 812}]> { 813 let ParserMatchClass = Imm0_63AsmOperand; 814} 815 816/// imm0_239 predicate - Immediate in the range [0,239]. 817def Imm0_239AsmOperand : ImmAsmOperand<0,239> { 818 let Name = "Imm0_239"; 819} 820def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> { 821 let ParserMatchClass = Imm0_239AsmOperand; 822} 823 824/// imm0_255 predicate - Immediate in the range [0,255]. 825def Imm0_255AsmOperand : ImmAsmOperand<0,255> { let Name = "Imm0_255"; } 826def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> { 827 let ParserMatchClass = Imm0_255AsmOperand; 828} 829 830/// imm0_65535 - An immediate is in the range [0,65535]. 831def Imm0_65535AsmOperand: ImmAsmOperand<0,65535> { let Name = "Imm0_65535"; } 832def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{ 833 return Imm >= 0 && Imm < 65536; 834}]> { 835 let ParserMatchClass = Imm0_65535AsmOperand; 836} 837 838// imm0_65535_neg - An immediate whose negative value is in the range [0.65535]. 839def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{ 840 return -Imm >= 0 && -Imm < 65536; 841}]>; 842 843// imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference 844// a relocatable expression. 845// 846// FIXME: This really needs a Thumb version separate from the ARM version. 847// While the range is the same, and can thus use the same match class, 848// the encoding is different so it should have a different encoder method. 849def Imm0_65535ExprAsmOperand: AsmOperandClass { 850 let Name = "Imm0_65535Expr"; 851 let RenderMethod = "addImmOperands"; 852 let DiagnosticString = "operand must be an immediate in the range [0,0xffff] or a relocatable expression"; 853} 854 855def imm0_65535_expr : Operand<i32> { 856 let EncoderMethod = "getHiLo16ImmOpValue"; 857 let ParserMatchClass = Imm0_65535ExprAsmOperand; 858} 859 860def Imm256_65535ExprAsmOperand: ImmAsmOperand<256,65535> { let Name = "Imm256_65535Expr"; } 861def imm256_65535_expr : Operand<i32> { 862 let ParserMatchClass = Imm256_65535ExprAsmOperand; 863} 864 865/// imm24b - True if the 32-bit immediate is encodable in 24 bits. 866def Imm24bitAsmOperand: ImmAsmOperand<0,0xffffff> { 867 let Name = "Imm24bit"; 868 let DiagnosticString = "operand must be an immediate in the range [0,0xffffff]"; 869} 870def imm24b : Operand<i32>, ImmLeaf<i32, [{ 871 return Imm >= 0 && Imm <= 0xffffff; 872}]> { 873 let ParserMatchClass = Imm24bitAsmOperand; 874} 875 876 877/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield 878/// e.g., 0xf000ffff 879def BitfieldAsmOperand : AsmOperandClass { 880 let Name = "Bitfield"; 881 let ParserMethod = "parseBitfield"; 882} 883 884def bf_inv_mask_imm : Operand<i32>, 885 PatLeaf<(imm), [{ 886 return ARM::isBitFieldInvertedMask(N->getZExtValue()); 887}] > { 888 let EncoderMethod = "getBitfieldInvertedMaskOpValue"; 889 let PrintMethod = "printBitfieldInvMaskImmOperand"; 890 let DecoderMethod = "DecodeBitfieldMaskOperand"; 891 let ParserMatchClass = BitfieldAsmOperand; 892 let GISelPredicateCode = [{ 893 // There's better methods of implementing this check. IntImmLeaf<> would be 894 // equivalent and have less boilerplate but we need a test for C++ 895 // predicates and this one causes new rules to be imported into GlobalISel 896 // without requiring additional features first. 897 const auto &MO = MI.getOperand(1); 898 if (!MO.isCImm()) 899 return false; 900 return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue()); 901 }]; 902} 903 904def imm1_32_XFORM: SDNodeXForm<imm, [{ 905 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), 906 MVT::i32); 907}]>; 908def Imm1_32AsmOperand: ImmAsmOperandMinusOne<1,32> { 909 let Name = "Imm1_32"; 910} 911def imm1_32 : Operand<i32>, PatLeaf<(imm), [{ 912 uint64_t Imm = N->getZExtValue(); 913 return Imm > 0 && Imm <= 32; 914 }], 915 imm1_32_XFORM> { 916 let PrintMethod = "printImmPlusOneOperand"; 917 let ParserMatchClass = Imm1_32AsmOperand; 918} 919 920def imm1_16_XFORM: SDNodeXForm<imm, [{ 921 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), 922 MVT::i32); 923}]>; 924def Imm1_16AsmOperand: ImmAsmOperandMinusOne<1,16> { let Name = "Imm1_16"; } 925def imm1_16 : Operand<i32>, ImmLeaf<i32, [{ 926 return Imm > 0 && Imm <= 16; 927 }], 928 imm1_16_XFORM> { 929 let PrintMethod = "printImmPlusOneOperand"; 930 let ParserMatchClass = Imm1_16AsmOperand; 931} 932 933// Define ARM specific addressing modes. 934// addrmode_imm12 := reg +/- imm12 935// 936def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; } 937class AddrMode_Imm12 : MemOperand, 938 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> { 939 // 12-bit immediate operand. Note that instructions using this encode 940 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other 941 // immediate values are as normal. 942 943 let EncoderMethod = "getAddrModeImm12OpValue"; 944 let DecoderMethod = "DecodeAddrModeImm12Operand"; 945 let ParserMatchClass = MemImm12OffsetAsmOperand; 946 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 947} 948 949def addrmode_imm12 : AddrMode_Imm12 { 950 let PrintMethod = "printAddrModeImm12Operand<false>"; 951} 952 953def addrmode_imm12_pre : AddrMode_Imm12 { 954 let PrintMethod = "printAddrModeImm12Operand<true>"; 955} 956 957// ldst_so_reg := reg +/- reg shop imm 958// 959def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; } 960def ldst_so_reg : MemOperand, 961 ComplexPattern<i32, 3, "SelectLdStSOReg", []> { 962 let EncoderMethod = "getLdStSORegOpValue"; 963 // FIXME: Simplify the printer 964 let PrintMethod = "printAddrMode2Operand"; 965 let DecoderMethod = "DecodeSORegMemOperand"; 966 let ParserMatchClass = MemRegOffsetAsmOperand; 967 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift); 968} 969 970// postidx_imm8 := +/- [0,255] 971// 972// 9 bit value: 973// {8} 1 is imm8 is non-negative. 0 otherwise. 974// {7-0} [0,255] imm8 value. 975def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; } 976def postidx_imm8 : MemOperand { 977 let PrintMethod = "printPostIdxImm8Operand"; 978 let ParserMatchClass = PostIdxImm8AsmOperand; 979 let MIOperandInfo = (ops i32imm); 980} 981 982// postidx_imm8s4 := +/- [0,1020] 983// 984// 9 bit value: 985// {8} 1 is imm8 is non-negative. 0 otherwise. 986// {7-0} [0,255] imm8 value, scaled by 4. 987def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; } 988def postidx_imm8s4 : MemOperand { 989 let PrintMethod = "printPostIdxImm8s4Operand"; 990 let ParserMatchClass = PostIdxImm8s4AsmOperand; 991 let MIOperandInfo = (ops i32imm); 992} 993 994 995// postidx_reg := +/- reg 996// 997def PostIdxRegAsmOperand : AsmOperandClass { 998 let Name = "PostIdxReg"; 999 let ParserMethod = "parsePostIdxReg"; 1000} 1001def postidx_reg : MemOperand { 1002 let EncoderMethod = "getPostIdxRegOpValue"; 1003 let DecoderMethod = "DecodePostIdxReg"; 1004 let PrintMethod = "printPostIdxRegOperand"; 1005 let ParserMatchClass = PostIdxRegAsmOperand; 1006 let MIOperandInfo = (ops GPRnopc, i32imm); 1007} 1008 1009def PostIdxRegShiftedAsmOperand : AsmOperandClass { 1010 let Name = "PostIdxRegShifted"; 1011 let ParserMethod = "parsePostIdxReg"; 1012} 1013def am2offset_reg : MemOperand, 1014 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg", 1015 [], [SDNPWantRoot]> { 1016 let EncoderMethod = "getAddrMode2OffsetOpValue"; 1017 let PrintMethod = "printAddrMode2OffsetOperand"; 1018 // When using this for assembly, it's always as a post-index offset. 1019 let ParserMatchClass = PostIdxRegShiftedAsmOperand; 1020 let MIOperandInfo = (ops GPRnopc, i32imm); 1021} 1022 1023// FIXME: am2offset_imm should only need the immediate, not the GPR. Having 1024// the GPR is purely vestigal at this point. 1025def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; } 1026def am2offset_imm : MemOperand, 1027 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm", 1028 [], [SDNPWantRoot]> { 1029 let EncoderMethod = "getAddrMode2OffsetOpValue"; 1030 let PrintMethod = "printAddrMode2OffsetOperand"; 1031 let ParserMatchClass = AM2OffsetImmAsmOperand; 1032 let MIOperandInfo = (ops GPRnopc, i32imm); 1033} 1034 1035 1036// addrmode3 := reg +/- reg 1037// addrmode3 := reg +/- imm8 1038// 1039// FIXME: split into imm vs. reg versions. 1040def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; } 1041class AddrMode3 : MemOperand, 1042 ComplexPattern<i32, 3, "SelectAddrMode3", []> { 1043 let EncoderMethod = "getAddrMode3OpValue"; 1044 let ParserMatchClass = AddrMode3AsmOperand; 1045 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 1046} 1047 1048def addrmode3 : AddrMode3 1049{ 1050 let PrintMethod = "printAddrMode3Operand<false>"; 1051} 1052 1053def addrmode3_pre : AddrMode3 1054{ 1055 let PrintMethod = "printAddrMode3Operand<true>"; 1056} 1057 1058// FIXME: split into imm vs. reg versions. 1059// FIXME: parser method to handle +/- register. 1060def AM3OffsetAsmOperand : AsmOperandClass { 1061 let Name = "AM3Offset"; 1062 let ParserMethod = "parseAM3Offset"; 1063} 1064def am3offset : MemOperand, 1065 ComplexPattern<i32, 2, "SelectAddrMode3Offset", 1066 [], [SDNPWantRoot]> { 1067 let EncoderMethod = "getAddrMode3OffsetOpValue"; 1068 let PrintMethod = "printAddrMode3OffsetOperand"; 1069 let ParserMatchClass = AM3OffsetAsmOperand; 1070 let MIOperandInfo = (ops GPR, i32imm); 1071} 1072 1073// ldstm_mode := {ia, ib, da, db} 1074// 1075def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> { 1076 let EncoderMethod = "getLdStmModeOpValue"; 1077 let PrintMethod = "printLdStmModeOperand"; 1078} 1079 1080// addrmode5 := reg +/- imm8*4 1081// 1082def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; } 1083class AddrMode5 : MemOperand, 1084 ComplexPattern<i32, 2, "SelectAddrMode5", []> { 1085 let EncoderMethod = "getAddrMode5OpValue"; 1086 let DecoderMethod = "DecodeAddrMode5Operand"; 1087 let ParserMatchClass = AddrMode5AsmOperand; 1088 let MIOperandInfo = (ops GPR:$base, i32imm); 1089} 1090 1091def addrmode5 : AddrMode5 { 1092 let PrintMethod = "printAddrMode5Operand<false>"; 1093} 1094 1095def addrmode5_pre : AddrMode5 { 1096 let PrintMethod = "printAddrMode5Operand<true>"; 1097} 1098 1099// addrmode5fp16 := reg +/- imm8*2 1100// 1101def AddrMode5FP16AsmOperand : AsmOperandClass { let Name = "AddrMode5FP16"; } 1102class AddrMode5FP16 : Operand<i32>, 1103 ComplexPattern<i32, 2, "SelectAddrMode5FP16", []> { 1104 let EncoderMethod = "getAddrMode5FP16OpValue"; 1105 let DecoderMethod = "DecodeAddrMode5FP16Operand"; 1106 let ParserMatchClass = AddrMode5FP16AsmOperand; 1107 let MIOperandInfo = (ops GPR:$base, i32imm); 1108} 1109 1110def addrmode5fp16 : AddrMode5FP16 { 1111 let PrintMethod = "printAddrMode5FP16Operand<false>"; 1112} 1113 1114// addrmode6 := reg with optional alignment 1115// 1116def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; } 1117def addrmode6 : MemOperand, 1118 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1119 let PrintMethod = "printAddrMode6Operand"; 1120 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 1121 let EncoderMethod = "getAddrMode6AddressOpValue"; 1122 let DecoderMethod = "DecodeAddrMode6Operand"; 1123 let ParserMatchClass = AddrMode6AsmOperand; 1124} 1125 1126def am6offset : MemOperand, 1127 ComplexPattern<i32, 1, "SelectAddrMode6Offset", 1128 [], [SDNPWantRoot]> { 1129 let PrintMethod = "printAddrMode6OffsetOperand"; 1130 let MIOperandInfo = (ops GPR); 1131 let EncoderMethod = "getAddrMode6OffsetOpValue"; 1132 let DecoderMethod = "DecodeGPRRegisterClass"; 1133} 1134 1135// Special version of addrmode6 to handle alignment encoding for VST1/VLD1 1136// (single element from one lane) for size 32. 1137def addrmode6oneL32 : MemOperand, 1138 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1139 let PrintMethod = "printAddrMode6Operand"; 1140 let MIOperandInfo = (ops GPR:$addr, i32imm); 1141 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue"; 1142} 1143 1144// Base class for addrmode6 with specific alignment restrictions. 1145class AddrMode6Align : MemOperand, 1146 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1147 let PrintMethod = "printAddrMode6Operand"; 1148 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 1149 let EncoderMethod = "getAddrMode6AddressOpValue"; 1150 let DecoderMethod = "DecodeAddrMode6Operand"; 1151} 1152 1153// Special version of addrmode6 to handle no allowed alignment encoding for 1154// VLD/VST instructions and checking the alignment is not specified. 1155def AddrMode6AlignNoneAsmOperand : AsmOperandClass { 1156 let Name = "AlignedMemoryNone"; 1157 let DiagnosticString = "alignment must be omitted"; 1158} 1159def addrmode6alignNone : AddrMode6Align { 1160 // The alignment specifier can only be omitted. 1161 let ParserMatchClass = AddrMode6AlignNoneAsmOperand; 1162} 1163 1164// Special version of addrmode6 to handle 16-bit alignment encoding for 1165// VLD/VST instructions and checking the alignment value. 1166def AddrMode6Align16AsmOperand : AsmOperandClass { 1167 let Name = "AlignedMemory16"; 1168 let DiagnosticString = "alignment must be 16 or omitted"; 1169} 1170def addrmode6align16 : AddrMode6Align { 1171 // The alignment specifier can only be 16 or omitted. 1172 let ParserMatchClass = AddrMode6Align16AsmOperand; 1173} 1174 1175// Special version of addrmode6 to handle 32-bit alignment encoding for 1176// VLD/VST instructions and checking the alignment value. 1177def AddrMode6Align32AsmOperand : AsmOperandClass { 1178 let Name = "AlignedMemory32"; 1179 let DiagnosticString = "alignment must be 32 or omitted"; 1180} 1181def addrmode6align32 : AddrMode6Align { 1182 // The alignment specifier can only be 32 or omitted. 1183 let ParserMatchClass = AddrMode6Align32AsmOperand; 1184} 1185 1186// Special version of addrmode6 to handle 64-bit alignment encoding for 1187// VLD/VST instructions and checking the alignment value. 1188def AddrMode6Align64AsmOperand : AsmOperandClass { 1189 let Name = "AlignedMemory64"; 1190 let DiagnosticString = "alignment must be 64 or omitted"; 1191} 1192def addrmode6align64 : AddrMode6Align { 1193 // The alignment specifier can only be 64 or omitted. 1194 let ParserMatchClass = AddrMode6Align64AsmOperand; 1195} 1196 1197// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1198// for VLD/VST instructions and checking the alignment value. 1199def AddrMode6Align64or128AsmOperand : AsmOperandClass { 1200 let Name = "AlignedMemory64or128"; 1201 let DiagnosticString = "alignment must be 64, 128 or omitted"; 1202} 1203def addrmode6align64or128 : AddrMode6Align { 1204 // The alignment specifier can only be 64, 128 or omitted. 1205 let ParserMatchClass = AddrMode6Align64or128AsmOperand; 1206} 1207 1208// Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment 1209// encoding for VLD/VST instructions and checking the alignment value. 1210def AddrMode6Align64or128or256AsmOperand : AsmOperandClass { 1211 let Name = "AlignedMemory64or128or256"; 1212 let DiagnosticString = "alignment must be 64, 128, 256 or omitted"; 1213} 1214def addrmode6align64or128or256 : AddrMode6Align { 1215 // The alignment specifier can only be 64, 128, 256 or omitted. 1216 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand; 1217} 1218 1219// Special version of addrmode6 to handle alignment encoding for VLD-dup 1220// instructions, specifically VLD4-dup. 1221def addrmode6dup : MemOperand, 1222 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1223 let PrintMethod = "printAddrMode6Operand"; 1224 let MIOperandInfo = (ops GPR:$addr, i32imm); 1225 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1226 // FIXME: This is close, but not quite right. The alignment specifier is 1227 // different. 1228 let ParserMatchClass = AddrMode6AsmOperand; 1229} 1230 1231// Base class for addrmode6dup with specific alignment restrictions. 1232class AddrMode6DupAlign : MemOperand, 1233 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1234 let PrintMethod = "printAddrMode6Operand"; 1235 let MIOperandInfo = (ops GPR:$addr, i32imm); 1236 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1237} 1238 1239// Special version of addrmode6 to handle no allowed alignment encoding for 1240// VLD-dup instruction and checking the alignment is not specified. 1241def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass { 1242 let Name = "DupAlignedMemoryNone"; 1243 let DiagnosticString = "alignment must be omitted"; 1244} 1245def addrmode6dupalignNone : AddrMode6DupAlign { 1246 // The alignment specifier can only be omitted. 1247 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand; 1248} 1249 1250// Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup 1251// instruction and checking the alignment value. 1252def AddrMode6dupAlign16AsmOperand : AsmOperandClass { 1253 let Name = "DupAlignedMemory16"; 1254 let DiagnosticString = "alignment must be 16 or omitted"; 1255} 1256def addrmode6dupalign16 : AddrMode6DupAlign { 1257 // The alignment specifier can only be 16 or omitted. 1258 let ParserMatchClass = AddrMode6dupAlign16AsmOperand; 1259} 1260 1261// Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup 1262// instruction and checking the alignment value. 1263def AddrMode6dupAlign32AsmOperand : AsmOperandClass { 1264 let Name = "DupAlignedMemory32"; 1265 let DiagnosticString = "alignment must be 32 or omitted"; 1266} 1267def addrmode6dupalign32 : AddrMode6DupAlign { 1268 // The alignment specifier can only be 32 or omitted. 1269 let ParserMatchClass = AddrMode6dupAlign32AsmOperand; 1270} 1271 1272// Special version of addrmode6 to handle 64-bit alignment encoding for VLD 1273// instructions and checking the alignment value. 1274def AddrMode6dupAlign64AsmOperand : AsmOperandClass { 1275 let Name = "DupAlignedMemory64"; 1276 let DiagnosticString = "alignment must be 64 or omitted"; 1277} 1278def addrmode6dupalign64 : AddrMode6DupAlign { 1279 // The alignment specifier can only be 64 or omitted. 1280 let ParserMatchClass = AddrMode6dupAlign64AsmOperand; 1281} 1282 1283// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1284// for VLD instructions and checking the alignment value. 1285def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass { 1286 let Name = "DupAlignedMemory64or128"; 1287 let DiagnosticString = "alignment must be 64, 128 or omitted"; 1288} 1289def addrmode6dupalign64or128 : AddrMode6DupAlign { 1290 // The alignment specifier can only be 64, 128 or omitted. 1291 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand; 1292} 1293 1294// addrmodepc := pc + reg 1295// 1296def addrmodepc : MemOperand, 1297 ComplexPattern<i32, 2, "SelectAddrModePC", []> { 1298 let PrintMethod = "printAddrModePCOperand"; 1299 let MIOperandInfo = (ops GPR, i32imm); 1300} 1301 1302// addr_offset_none := reg 1303// 1304def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; } 1305def addr_offset_none : MemOperand, 1306 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> { 1307 let PrintMethod = "printAddrMode7Operand"; 1308 let DecoderMethod = "DecodeAddrMode7Operand"; 1309 let ParserMatchClass = MemNoOffsetAsmOperand; 1310 let MIOperandInfo = (ops GPR:$base); 1311} 1312 1313def nohash_imm : Operand<i32> { 1314 let PrintMethod = "printNoHashImmediate"; 1315} 1316 1317def CoprocNumAsmOperand : AsmOperandClass { 1318 let Name = "CoprocNum"; 1319 let ParserMethod = "parseCoprocNumOperand"; 1320} 1321def p_imm : Operand<i32> { 1322 let PrintMethod = "printPImmediate"; 1323 let ParserMatchClass = CoprocNumAsmOperand; 1324 let DecoderMethod = "DecodeCoprocessor"; 1325} 1326 1327def CoprocRegAsmOperand : AsmOperandClass { 1328 let Name = "CoprocReg"; 1329 let ParserMethod = "parseCoprocRegOperand"; 1330} 1331def c_imm : Operand<i32> { 1332 let PrintMethod = "printCImmediate"; 1333 let ParserMatchClass = CoprocRegAsmOperand; 1334} 1335def CoprocOptionAsmOperand : AsmOperandClass { 1336 let Name = "CoprocOption"; 1337 let ParserMethod = "parseCoprocOptionOperand"; 1338} 1339def coproc_option_imm : Operand<i32> { 1340 let PrintMethod = "printCoprocOptionImm"; 1341 let ParserMatchClass = CoprocOptionAsmOperand; 1342} 1343 1344//===----------------------------------------------------------------------===// 1345 1346include "ARMInstrFormats.td" 1347 1348//===----------------------------------------------------------------------===// 1349// Multiclass helpers... 1350// 1351 1352/// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a 1353/// binop that produces a value. 1354let TwoOperandAliasConstraint = "$Rn = $Rd" in 1355multiclass AsI1_bin_irs<bits<4> opcod, string opc, 1356 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1357 SDPatternOperator opnode, bit Commutable = 0> { 1358 // The register-immediate version is re-materializable. This is useful 1359 // in particular for taking the address of a local. 1360 let isReMaterializable = 1 in { 1361 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm, 1362 iii, opc, "\t$Rd, $Rn, $imm", 1363 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>, 1364 Sched<[WriteALU, ReadALU]> { 1365 bits<4> Rd; 1366 bits<4> Rn; 1367 bits<12> imm; 1368 let Inst{25} = 1; 1369 let Inst{19-16} = Rn; 1370 let Inst{15-12} = Rd; 1371 let Inst{11-0} = imm; 1372 } 1373 } 1374 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1375 iir, opc, "\t$Rd, $Rn, $Rm", 1376 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>, 1377 Sched<[WriteALU, ReadALU, ReadALU]> { 1378 bits<4> Rd; 1379 bits<4> Rn; 1380 bits<4> Rm; 1381 let Inst{25} = 0; 1382 let isCommutable = Commutable; 1383 let Inst{19-16} = Rn; 1384 let Inst{15-12} = Rd; 1385 let Inst{11-4} = 0b00000000; 1386 let Inst{3-0} = Rm; 1387 } 1388 1389 def rsi : AsI1<opcod, (outs GPR:$Rd), 1390 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1391 iis, opc, "\t$Rd, $Rn, $shift", 1392 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>, 1393 Sched<[WriteALUsi, ReadALU]> { 1394 bits<4> Rd; 1395 bits<4> Rn; 1396 bits<12> shift; 1397 let Inst{25} = 0; 1398 let Inst{19-16} = Rn; 1399 let Inst{15-12} = Rd; 1400 let Inst{11-5} = shift{11-5}; 1401 let Inst{4} = 0; 1402 let Inst{3-0} = shift{3-0}; 1403 } 1404 1405 def rsr : AsI1<opcod, (outs GPR:$Rd), 1406 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1407 iis, opc, "\t$Rd, $Rn, $shift", 1408 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>, 1409 Sched<[WriteALUsr, ReadALUsr]> { 1410 bits<4> Rd; 1411 bits<4> Rn; 1412 bits<12> shift; 1413 let Inst{25} = 0; 1414 let Inst{19-16} = Rn; 1415 let Inst{15-12} = Rd; 1416 let Inst{11-8} = shift{11-8}; 1417 let Inst{7} = 0; 1418 let Inst{6-5} = shift{6-5}; 1419 let Inst{4} = 1; 1420 let Inst{3-0} = shift{3-0}; 1421 } 1422} 1423 1424/// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are 1425/// reversed. The 'rr' form is only defined for the disassembler; for codegen 1426/// it is equivalent to the AsI1_bin_irs counterpart. 1427let TwoOperandAliasConstraint = "$Rn = $Rd" in 1428multiclass AsI1_rbin_irs<bits<4> opcod, string opc, 1429 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1430 SDNode opnode, bit Commutable = 0> { 1431 // The register-immediate version is re-materializable. This is useful 1432 // in particular for taking the address of a local. 1433 let isReMaterializable = 1 in { 1434 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm, 1435 iii, opc, "\t$Rd, $Rn, $imm", 1436 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>, 1437 Sched<[WriteALU, ReadALU]> { 1438 bits<4> Rd; 1439 bits<4> Rn; 1440 bits<12> imm; 1441 let Inst{25} = 1; 1442 let Inst{19-16} = Rn; 1443 let Inst{15-12} = Rd; 1444 let Inst{11-0} = imm; 1445 } 1446 } 1447 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1448 iir, opc, "\t$Rd, $Rn, $Rm", 1449 [/* pattern left blank */]>, 1450 Sched<[WriteALU, ReadALU, ReadALU]> { 1451 bits<4> Rd; 1452 bits<4> Rn; 1453 bits<4> Rm; 1454 let Inst{11-4} = 0b00000000; 1455 let Inst{25} = 0; 1456 let Inst{3-0} = Rm; 1457 let Inst{15-12} = Rd; 1458 let Inst{19-16} = Rn; 1459 } 1460 1461 def rsi : AsI1<opcod, (outs GPR:$Rd), 1462 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1463 iis, opc, "\t$Rd, $Rn, $shift", 1464 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>, 1465 Sched<[WriteALUsi, ReadALU]> { 1466 bits<4> Rd; 1467 bits<4> Rn; 1468 bits<12> shift; 1469 let Inst{25} = 0; 1470 let Inst{19-16} = Rn; 1471 let Inst{15-12} = Rd; 1472 let Inst{11-5} = shift{11-5}; 1473 let Inst{4} = 0; 1474 let Inst{3-0} = shift{3-0}; 1475 } 1476 1477 def rsr : AsI1<opcod, (outs GPR:$Rd), 1478 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1479 iis, opc, "\t$Rd, $Rn, $shift", 1480 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>, 1481 Sched<[WriteALUsr, ReadALUsr]> { 1482 bits<4> Rd; 1483 bits<4> Rn; 1484 bits<12> shift; 1485 let Inst{25} = 0; 1486 let Inst{19-16} = Rn; 1487 let Inst{15-12} = Rd; 1488 let Inst{11-8} = shift{11-8}; 1489 let Inst{7} = 0; 1490 let Inst{6-5} = shift{6-5}; 1491 let Inst{4} = 1; 1492 let Inst{3-0} = shift{3-0}; 1493 } 1494} 1495 1496/// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default. 1497/// 1498/// These opcodes will be converted to the real non-S opcodes by 1499/// AdjustInstrPostInstrSelection after giving them an optional CPSR operand. 1500let hasPostISelHook = 1, Defs = [CPSR] in { 1501multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir, 1502 InstrItinClass iis, SDNode opnode, 1503 bit Commutable = 0> { 1504 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p), 1505 4, iii, 1506 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>, 1507 Sched<[WriteALU, ReadALU]>; 1508 1509 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p), 1510 4, iir, 1511 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>, 1512 Sched<[WriteALU, ReadALU, ReadALU]> { 1513 let isCommutable = Commutable; 1514 } 1515 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1516 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1517 4, iis, 1518 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1519 so_reg_imm:$shift))]>, 1520 Sched<[WriteALUsi, ReadALU]>; 1521 1522 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1523 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1524 4, iis, 1525 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1526 so_reg_reg:$shift))]>, 1527 Sched<[WriteALUSsr, ReadALUsr]>; 1528} 1529} 1530 1531/// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG 1532/// operands are reversed. 1533let hasPostISelHook = 1, Defs = [CPSR] in { 1534multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir, 1535 InstrItinClass iis, SDNode opnode, 1536 bit Commutable = 0> { 1537 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p), 1538 4, iii, 1539 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>, 1540 Sched<[WriteALU, ReadALU]>; 1541 1542 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1543 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1544 4, iis, 1545 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, 1546 GPR:$Rn))]>, 1547 Sched<[WriteALUsi, ReadALU]>; 1548 1549 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1550 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1551 4, iis, 1552 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, 1553 GPR:$Rn))]>, 1554 Sched<[WriteALUSsr, ReadALUsr]>; 1555} 1556} 1557 1558/// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test 1559/// patterns. Similar to AsI1_bin_irs except the instruction does not produce 1560/// a explicit result, only implicitly set CPSR. 1561let isCompare = 1, Defs = [CPSR] in { 1562multiclass AI1_cmp_irs<bits<4> opcod, string opc, 1563 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1564 SDPatternOperator opnode, bit Commutable = 0, 1565 string rrDecoderMethod = ""> { 1566 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii, 1567 opc, "\t$Rn, $imm", 1568 [(opnode GPR:$Rn, mod_imm:$imm)]>, 1569 Sched<[WriteCMP, ReadALU]> { 1570 bits<4> Rn; 1571 bits<12> imm; 1572 let Inst{25} = 1; 1573 let Inst{20} = 1; 1574 let Inst{19-16} = Rn; 1575 let Inst{15-12} = 0b0000; 1576 let Inst{11-0} = imm; 1577 1578 let Unpredictable{15-12} = 0b1111; 1579 } 1580 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir, 1581 opc, "\t$Rn, $Rm", 1582 [(opnode GPR:$Rn, GPR:$Rm)]>, 1583 Sched<[WriteCMP, ReadALU, ReadALU]> { 1584 bits<4> Rn; 1585 bits<4> Rm; 1586 let isCommutable = Commutable; 1587 let Inst{25} = 0; 1588 let Inst{20} = 1; 1589 let Inst{19-16} = Rn; 1590 let Inst{15-12} = 0b0000; 1591 let Inst{11-4} = 0b00000000; 1592 let Inst{3-0} = Rm; 1593 let DecoderMethod = rrDecoderMethod; 1594 1595 let Unpredictable{15-12} = 0b1111; 1596 } 1597 def rsi : AI1<opcod, (outs), 1598 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis, 1599 opc, "\t$Rn, $shift", 1600 [(opnode GPR:$Rn, so_reg_imm:$shift)]>, 1601 Sched<[WriteCMPsi, ReadALU]> { 1602 bits<4> Rn; 1603 bits<12> shift; 1604 let Inst{25} = 0; 1605 let Inst{20} = 1; 1606 let Inst{19-16} = Rn; 1607 let Inst{15-12} = 0b0000; 1608 let Inst{11-5} = shift{11-5}; 1609 let Inst{4} = 0; 1610 let Inst{3-0} = shift{3-0}; 1611 1612 let Unpredictable{15-12} = 0b1111; 1613 } 1614 def rsr : AI1<opcod, (outs), 1615 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis, 1616 opc, "\t$Rn, $shift", 1617 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>, 1618 Sched<[WriteCMPsr, ReadALU]> { 1619 bits<4> Rn; 1620 bits<12> shift; 1621 let Inst{25} = 0; 1622 let Inst{20} = 1; 1623 let Inst{19-16} = Rn; 1624 let Inst{15-12} = 0b0000; 1625 let Inst{11-8} = shift{11-8}; 1626 let Inst{7} = 0; 1627 let Inst{6-5} = shift{6-5}; 1628 let Inst{4} = 1; 1629 let Inst{3-0} = shift{3-0}; 1630 1631 let Unpredictable{15-12} = 0b1111; 1632 } 1633 1634} 1635} 1636 1637/// AI_ext_rrot - A unary operation with two forms: one whose operand is a 1638/// register and one whose operand is a register rotated by 8/16/24. 1639/// FIXME: Remove the 'r' variant. Its rot_imm is zero. 1640class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> 1641 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1642 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", 1643 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1644 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1645 bits<4> Rd; 1646 bits<4> Rm; 1647 bits<2> rot; 1648 let Inst{19-16} = 0b1111; 1649 let Inst{15-12} = Rd; 1650 let Inst{11-10} = rot; 1651 let Inst{3-0} = Rm; 1652} 1653 1654class AI_ext_rrot_np<bits<8> opcod, string opc> 1655 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1656 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>, 1657 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1658 bits<2> rot; 1659 let Inst{19-16} = 0b1111; 1660 let Inst{11-10} = rot; 1661 } 1662 1663/// AI_exta_rrot - A binary operation with two forms: one whose operand is a 1664/// register and one whose operand is a register rotated by 8/16/24. 1665class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> 1666 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1667 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", 1668 [(set GPRnopc:$Rd, (opnode GPR:$Rn, 1669 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1670 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1671 bits<4> Rd; 1672 bits<4> Rm; 1673 bits<4> Rn; 1674 bits<2> rot; 1675 let Inst{19-16} = Rn; 1676 let Inst{15-12} = Rd; 1677 let Inst{11-10} = rot; 1678 let Inst{9-4} = 0b000111; 1679 let Inst{3-0} = Rm; 1680} 1681 1682class AI_exta_rrot_np<bits<8> opcod, string opc> 1683 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1684 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>, 1685 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1686 bits<4> Rn; 1687 bits<2> rot; 1688 let Inst{19-16} = Rn; 1689 let Inst{11-10} = rot; 1690} 1691 1692/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube. 1693let TwoOperandAliasConstraint = "$Rn = $Rd" in 1694multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, SDNode opnode, 1695 bit Commutable = 0> { 1696 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1697 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), 1698 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1699 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>, 1700 Requires<[IsARM]>, 1701 Sched<[WriteALU, ReadALU]> { 1702 bits<4> Rd; 1703 bits<4> Rn; 1704 bits<12> imm; 1705 let Inst{25} = 1; 1706 let Inst{15-12} = Rd; 1707 let Inst{19-16} = Rn; 1708 let Inst{11-0} = imm; 1709 } 1710 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1711 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1712 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>, 1713 Requires<[IsARM]>, 1714 Sched<[WriteALU, ReadALU, ReadALU]> { 1715 bits<4> Rd; 1716 bits<4> Rn; 1717 bits<4> Rm; 1718 let Inst{11-4} = 0b00000000; 1719 let Inst{25} = 0; 1720 let isCommutable = Commutable; 1721 let Inst{3-0} = Rm; 1722 let Inst{15-12} = Rd; 1723 let Inst{19-16} = Rn; 1724 } 1725 def rsi : AsI1<opcod, (outs GPR:$Rd), 1726 (ins GPR:$Rn, so_reg_imm:$shift), 1727 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1728 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>, 1729 Requires<[IsARM]>, 1730 Sched<[WriteALUsi, ReadALU]> { 1731 bits<4> Rd; 1732 bits<4> Rn; 1733 bits<12> shift; 1734 let Inst{25} = 0; 1735 let Inst{19-16} = Rn; 1736 let Inst{15-12} = Rd; 1737 let Inst{11-5} = shift{11-5}; 1738 let Inst{4} = 0; 1739 let Inst{3-0} = shift{3-0}; 1740 } 1741 def rsr : AsI1<opcod, (outs GPRnopc:$Rd), 1742 (ins GPRnopc:$Rn, so_reg_reg:$shift), 1743 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1744 [(set GPRnopc:$Rd, CPSR, 1745 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>, 1746 Requires<[IsARM]>, 1747 Sched<[WriteALUsr, ReadALUsr]> { 1748 bits<4> Rd; 1749 bits<4> Rn; 1750 bits<12> shift; 1751 let Inst{25} = 0; 1752 let Inst{19-16} = Rn; 1753 let Inst{15-12} = Rd; 1754 let Inst{11-8} = shift{11-8}; 1755 let Inst{7} = 0; 1756 let Inst{6-5} = shift{6-5}; 1757 let Inst{4} = 1; 1758 let Inst{3-0} = shift{3-0}; 1759 } 1760 } 1761} 1762 1763/// AI1_rsc_irs - Define instructions and patterns for rsc 1764let TwoOperandAliasConstraint = "$Rn = $Rd" in 1765multiclass AI1_rsc_irs<bits<4> opcod, string opc, SDNode opnode> { 1766 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1767 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), 1768 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1769 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>, 1770 Requires<[IsARM]>, 1771 Sched<[WriteALU, ReadALU]> { 1772 bits<4> Rd; 1773 bits<4> Rn; 1774 bits<12> imm; 1775 let Inst{25} = 1; 1776 let Inst{15-12} = Rd; 1777 let Inst{19-16} = Rn; 1778 let Inst{11-0} = imm; 1779 } 1780 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1781 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1782 [/* pattern left blank */]>, 1783 Sched<[WriteALU, ReadALU, ReadALU]> { 1784 bits<4> Rd; 1785 bits<4> Rn; 1786 bits<4> Rm; 1787 let Inst{11-4} = 0b00000000; 1788 let Inst{25} = 0; 1789 let Inst{3-0} = Rm; 1790 let Inst{15-12} = Rd; 1791 let Inst{19-16} = Rn; 1792 } 1793 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift), 1794 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1795 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>, 1796 Requires<[IsARM]>, 1797 Sched<[WriteALUsi, ReadALU]> { 1798 bits<4> Rd; 1799 bits<4> Rn; 1800 bits<12> shift; 1801 let Inst{25} = 0; 1802 let Inst{19-16} = Rn; 1803 let Inst{15-12} = Rd; 1804 let Inst{11-5} = shift{11-5}; 1805 let Inst{4} = 0; 1806 let Inst{3-0} = shift{3-0}; 1807 } 1808 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift), 1809 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1810 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>, 1811 Requires<[IsARM]>, 1812 Sched<[WriteALUsr, ReadALUsr]> { 1813 bits<4> Rd; 1814 bits<4> Rn; 1815 bits<12> shift; 1816 let Inst{25} = 0; 1817 let Inst{19-16} = Rn; 1818 let Inst{15-12} = Rd; 1819 let Inst{11-8} = shift{11-8}; 1820 let Inst{7} = 0; 1821 let Inst{6-5} = shift{6-5}; 1822 let Inst{4} = 1; 1823 let Inst{3-0} = shift{3-0}; 1824 } 1825 } 1826} 1827 1828let canFoldAsLoad = 1, isReMaterializable = 1 in { 1829multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii, 1830 InstrItinClass iir, PatFrag opnode> { 1831 // Note: We use the complex addrmode_imm12 rather than just an input 1832 // GPR and a constrained immediate so that we can use this to match 1833 // frame index references and avoid matching constant pool references. 1834 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 1835 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1836 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> { 1837 bits<4> Rt; 1838 bits<17> addr; 1839 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1840 let Inst{19-16} = addr{16-13}; // Rn 1841 let Inst{15-12} = Rt; 1842 let Inst{11-0} = addr{11-0}; // imm12 1843 } 1844 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift), 1845 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1846 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> { 1847 bits<4> Rt; 1848 bits<17> shift; 1849 let shift{4} = 0; // Inst{4} = 0 1850 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1851 let Inst{19-16} = shift{16-13}; // Rn 1852 let Inst{15-12} = Rt; 1853 let Inst{11-0} = shift{11-0}; 1854 } 1855} 1856} 1857 1858let canFoldAsLoad = 1, isReMaterializable = 1 in { 1859multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii, 1860 InstrItinClass iir, PatFrag opnode> { 1861 // Note: We use the complex addrmode_imm12 rather than just an input 1862 // GPR and a constrained immediate so that we can use this to match 1863 // frame index references and avoid matching constant pool references. 1864 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), 1865 (ins addrmode_imm12:$addr), 1866 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1867 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> { 1868 bits<4> Rt; 1869 bits<17> addr; 1870 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1871 let Inst{19-16} = addr{16-13}; // Rn 1872 let Inst{15-12} = Rt; 1873 let Inst{11-0} = addr{11-0}; // imm12 1874 } 1875 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), 1876 (ins ldst_so_reg:$shift), 1877 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1878 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> { 1879 bits<4> Rt; 1880 bits<17> shift; 1881 let shift{4} = 0; // Inst{4} = 0 1882 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1883 let Inst{19-16} = shift{16-13}; // Rn 1884 let Inst{15-12} = Rt; 1885 let Inst{11-0} = shift{11-0}; 1886 } 1887} 1888} 1889 1890 1891multiclass AI_str1<bit isByte, string opc, InstrItinClass iii, 1892 InstrItinClass iir, PatFrag opnode> { 1893 // Note: We use the complex addrmode_imm12 rather than just an input 1894 // GPR and a constrained immediate so that we can use this to match 1895 // frame index references and avoid matching constant pool references. 1896 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1897 (ins GPR:$Rt, addrmode_imm12:$addr), 1898 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1899 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> { 1900 bits<4> Rt; 1901 bits<17> addr; 1902 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1903 let Inst{19-16} = addr{16-13}; // Rn 1904 let Inst{15-12} = Rt; 1905 let Inst{11-0} = addr{11-0}; // imm12 1906 } 1907 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift), 1908 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1909 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> { 1910 bits<4> Rt; 1911 bits<17> shift; 1912 let shift{4} = 0; // Inst{4} = 0 1913 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1914 let Inst{19-16} = shift{16-13}; // Rn 1915 let Inst{15-12} = Rt; 1916 let Inst{11-0} = shift{11-0}; 1917 } 1918} 1919 1920multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii, 1921 InstrItinClass iir, PatFrag opnode> { 1922 // Note: We use the complex addrmode_imm12 rather than just an input 1923 // GPR and a constrained immediate so that we can use this to match 1924 // frame index references and avoid matching constant pool references. 1925 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1926 (ins GPRnopc:$Rt, addrmode_imm12:$addr), 1927 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1928 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> { 1929 bits<4> Rt; 1930 bits<17> addr; 1931 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1932 let Inst{19-16} = addr{16-13}; // Rn 1933 let Inst{15-12} = Rt; 1934 let Inst{11-0} = addr{11-0}; // imm12 1935 } 1936 def rs : AI2ldst<0b011, 0, isByte, (outs), 1937 (ins GPRnopc:$Rt, ldst_so_reg:$shift), 1938 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1939 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> { 1940 bits<4> Rt; 1941 bits<17> shift; 1942 let shift{4} = 0; // Inst{4} = 0 1943 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1944 let Inst{19-16} = shift{16-13}; // Rn 1945 let Inst{15-12} = Rt; 1946 let Inst{11-0} = shift{11-0}; 1947 } 1948} 1949 1950 1951//===----------------------------------------------------------------------===// 1952// Instructions 1953//===----------------------------------------------------------------------===// 1954 1955//===----------------------------------------------------------------------===// 1956// Miscellaneous Instructions. 1957// 1958 1959/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in 1960/// the function. The first operand is the ID# for this instruction, the second 1961/// is the index into the MachineConstantPool that this is, the third is the 1962/// size in bytes of this constant pool entry. 1963let hasSideEffects = 0, isNotDuplicable = 1 in 1964def CONSTPOOL_ENTRY : 1965PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1966 i32imm:$size), NoItinerary, []>; 1967 1968/// A jumptable consisting of direct 32-bit addresses of the destination basic 1969/// blocks (either absolute, or relative to the start of the jump-table in PIC 1970/// mode). Used mostly in ARM and Thumb-1 modes. 1971def JUMPTABLE_ADDRS : 1972PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1973 i32imm:$size), NoItinerary, []>; 1974 1975/// A jumptable consisting of 32-bit jump instructions. Used for Thumb-2 tables 1976/// that cannot be optimised to use TBB or TBH. 1977def JUMPTABLE_INSTS : 1978PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1979 i32imm:$size), NoItinerary, []>; 1980 1981/// A jumptable consisting of 8-bit unsigned integers representing offsets from 1982/// a TBB instruction. 1983def JUMPTABLE_TBB : 1984PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1985 i32imm:$size), NoItinerary, []>; 1986 1987/// A jumptable consisting of 16-bit unsigned integers representing offsets from 1988/// a TBH instruction. 1989def JUMPTABLE_TBH : 1990PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1991 i32imm:$size), NoItinerary, []>; 1992 1993 1994// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 1995// from removing one half of the matched pairs. That breaks PEI, which assumes 1996// these will always be in pairs, and asserts if it finds otherwise. Better way? 1997let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 1998def ADJCALLSTACKUP : 1999PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, 2000 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>; 2001 2002def ADJCALLSTACKDOWN : 2003PseudoInst<(outs), (ins i32imm:$amt, i32imm:$amt2, pred:$p), NoItinerary, 2004 [(ARMcallseq_start timm:$amt, timm:$amt2)]>; 2005} 2006 2007def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary, 2008 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>, 2009 Requires<[IsARM, HasV6]> { 2010 bits<8> imm; 2011 let Inst{27-8} = 0b00110010000011110000; 2012 let Inst{7-0} = imm; 2013 let DecoderMethod = "DecodeHINTInstruction"; 2014} 2015 2016def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>; 2017def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>; 2018def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>; 2019def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>; 2020def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>; 2021def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>; 2022def : InstAlias<"esb$p", (HINT 16, pred:$p)>, Requires<[IsARM, HasRAS]>; 2023def : InstAlias<"csdb$p", (HINT 20, pred:$p)>, Requires<[IsARM, HasV6K]>; 2024 2025def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel", 2026 "\t$Rd, $Rn, $Rm", 2027 [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))]>, 2028 Requires<[IsARM, HasV6]> { 2029 bits<4> Rd; 2030 bits<4> Rn; 2031 bits<4> Rm; 2032 let Inst{3-0} = Rm; 2033 let Inst{15-12} = Rd; 2034 let Inst{19-16} = Rn; 2035 let Inst{27-20} = 0b01101000; 2036 let Inst{7-4} = 0b1011; 2037 let Inst{11-8} = 0b1111; 2038 let Unpredictable{11-8} = 0b1111; 2039} 2040 2041// The 16-bit operand $val can be used by a debugger to store more information 2042// about the breakpoint. 2043def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 2044 "bkpt", "\t$val", []>, Requires<[IsARM]> { 2045 bits<16> val; 2046 let Inst{3-0} = val{3-0}; 2047 let Inst{19-8} = val{15-4}; 2048 let Inst{27-20} = 0b00010010; 2049 let Inst{31-28} = 0xe; // AL 2050 let Inst{7-4} = 0b0111; 2051} 2052// default immediate for breakpoint mnemonic 2053def : InstAlias<"bkpt", (BKPT 0), 0>, Requires<[IsARM]>; 2054 2055def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 2056 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> { 2057 bits<16> val; 2058 let Inst{3-0} = val{3-0}; 2059 let Inst{19-8} = val{15-4}; 2060 let Inst{27-20} = 0b00010000; 2061 let Inst{31-28} = 0xe; // AL 2062 let Inst{7-4} = 0b0111; 2063} 2064 2065// Change Processor State 2066// FIXME: We should use InstAlias to handle the optional operands. 2067class CPS<dag iops, string asm_ops> 2068 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops), 2069 []>, Requires<[IsARM]> { 2070 bits<2> imod; 2071 bits<3> iflags; 2072 bits<5> mode; 2073 bit M; 2074 2075 let Inst{31-28} = 0b1111; 2076 let Inst{27-20} = 0b00010000; 2077 let Inst{19-18} = imod; 2078 let Inst{17} = M; // Enabled if mode is set; 2079 let Inst{16-9} = 0b00000000; 2080 let Inst{8-6} = iflags; 2081 let Inst{5} = 0; 2082 let Inst{4-0} = mode; 2083} 2084 2085let DecoderMethod = "DecodeCPSInstruction" in { 2086let M = 1 in 2087 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode), 2088 "$imod\t$iflags, $mode">; 2089let mode = 0, M = 0 in 2090 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">; 2091 2092let imod = 0, iflags = 0, M = 1 in 2093 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">; 2094} 2095 2096// Preload signals the memory system of possible future data/instruction access. 2097multiclass APreLoad<bits<1> read, bits<1> data, string opc> { 2098 2099 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm, 2100 IIC_Preload, !strconcat(opc, "\t$addr"), 2101 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>, 2102 Sched<[WritePreLd]> { 2103 bits<4> Rt; 2104 bits<17> addr; 2105 let Inst{31-26} = 0b111101; 2106 let Inst{25} = 0; // 0 for immediate form 2107 let Inst{24} = data; 2108 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2109 let Inst{22} = read; 2110 let Inst{21-20} = 0b01; 2111 let Inst{19-16} = addr{16-13}; // Rn 2112 let Inst{15-12} = 0b1111; 2113 let Inst{11-0} = addr{11-0}; // imm12 2114 } 2115 2116 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload, 2117 !strconcat(opc, "\t$shift"), 2118 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>, 2119 Sched<[WritePreLd]> { 2120 bits<17> shift; 2121 let Inst{31-26} = 0b111101; 2122 let Inst{25} = 1; // 1 for register form 2123 let Inst{24} = data; 2124 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 2125 let Inst{22} = read; 2126 let Inst{21-20} = 0b01; 2127 let Inst{19-16} = shift{16-13}; // Rn 2128 let Inst{15-12} = 0b1111; 2129 let Inst{11-0} = shift{11-0}; 2130 let Inst{4} = 0; 2131 } 2132} 2133 2134defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>; 2135defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>; 2136defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>; 2137 2138def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary, 2139 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> { 2140 bits<1> end; 2141 let Inst{31-10} = 0b1111000100000001000000; 2142 let Inst{9} = end; 2143 let Inst{8-0} = 0; 2144} 2145 2146def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", 2147 [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> { 2148 bits<4> opt; 2149 let Inst{27-4} = 0b001100100000111100001111; 2150 let Inst{3-0} = opt; 2151} 2152 2153// A8.8.247 UDF - Undefined (Encoding A1) 2154def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary, 2155 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> { 2156 bits<16> imm16; 2157 let Inst{31-28} = 0b1110; // AL 2158 let Inst{27-25} = 0b011; 2159 let Inst{24-20} = 0b11111; 2160 let Inst{19-8} = imm16{15-4}; 2161 let Inst{7-4} = 0b1111; 2162 let Inst{3-0} = imm16{3-0}; 2163} 2164 2165/* 2166 * A5.4 Permanently UNDEFINED instructions. 2167 * 2168 * For most targets use UDF #65006, for which the OS will generate SIGTRAP. 2169 * Other UDF encodings generate SIGILL. 2170 * 2171 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb. 2172 * Encoding A1: 2173 * 1110 0111 1111 iiii iiii iiii 1111 iiii 2174 * Encoding T1: 2175 * 1101 1110 iiii iiii 2176 * It uses the following encoding: 2177 * 1110 0111 1111 1110 1101 1110 1111 0000 2178 * - In ARM: UDF #60896; 2179 * - In Thumb: UDF #254 followed by a branch-to-self. 2180 */ 2181let isBarrier = 1, isTerminator = 1 in 2182def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary, 2183 "trap", [(trap)]>, 2184 Requires<[IsARM,UseNaClTrap]> { 2185 let Inst = 0xe7fedef0; 2186} 2187let isBarrier = 1, isTerminator = 1 in 2188def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary, 2189 "trap", [(trap)]>, 2190 Requires<[IsARM,DontUseNaClTrap]> { 2191 let Inst = 0xe7ffdefe; 2192} 2193 2194// Address computation and loads and stores in PIC mode. 2195let isNotDuplicable = 1 in { 2196def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), 2197 4, IIC_iALUr, 2198 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>, 2199 Sched<[WriteALU, ReadALU]>; 2200 2201let AddedComplexity = 10 in { 2202def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 2203 4, IIC_iLoad_r, 2204 [(set GPR:$dst, (load addrmodepc:$addr))]>; 2205 2206def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2207 4, IIC_iLoad_bh_r, 2208 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>; 2209 2210def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2211 4, IIC_iLoad_bh_r, 2212 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>; 2213 2214def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2215 4, IIC_iLoad_bh_r, 2216 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>; 2217 2218def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2219 4, IIC_iLoad_bh_r, 2220 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>; 2221} 2222let AddedComplexity = 10 in { 2223def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2224 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>; 2225 2226def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2227 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src, 2228 addrmodepc:$addr)]>; 2229 2230def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2231 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; 2232} 2233} // isNotDuplicable = 1 2234 2235 2236// LEApcrel - Load a pc-relative address into a register without offending the 2237// assembler. 2238let hasSideEffects = 0, isReMaterializable = 1 in 2239// The 'adr' mnemonic encodes differently if the label is before or after 2240// the instruction. The {24-21} opcode bits are set by the fixup, as we don't 2241// know until then which form of the instruction will be used. 2242def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label), 2243 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>, 2244 Sched<[WriteALU, ReadALU]> { 2245 bits<4> Rd; 2246 bits<14> label; 2247 let Inst{27-25} = 0b001; 2248 let Inst{24} = 0; 2249 let Inst{23-22} = label{13-12}; 2250 let Inst{21} = 0; 2251 let Inst{20} = 0; 2252 let Inst{19-16} = 0b1111; 2253 let Inst{15-12} = Rd; 2254 let Inst{11-0} = label{11-0}; 2255} 2256 2257let hasSideEffects = 1 in { 2258def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p), 2259 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2260 2261def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd), 2262 (ins i32imm:$label, pred:$p), 2263 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2264} 2265 2266//===----------------------------------------------------------------------===// 2267// Control Flow Instructions. 2268// 2269 2270let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 2271 // ARMV4T and above 2272 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2273 "bx", "\tlr", [(ARMretflag)]>, 2274 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2275 let Inst{27-0} = 0b0001001011111111111100011110; 2276 } 2277 2278 // ARMV4 only 2279 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2280 "mov", "\tpc, lr", [(ARMretflag)]>, 2281 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> { 2282 let Inst{27-0} = 0b0001101000001111000000001110; 2283 } 2284 2285 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets 2286 // the user-space one). 2287 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p), 2288 4, IIC_Br, 2289 [(ARMintretflag imm:$offset)]>; 2290} 2291 2292// Indirect branches 2293let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 2294 // ARMV4T and above 2295 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst", 2296 [(brind GPR:$dst)]>, 2297 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2298 bits<4> dst; 2299 let Inst{31-4} = 0b1110000100101111111111110001; 2300 let Inst{3-0} = dst; 2301 } 2302 2303 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, 2304 "bx", "\t$dst", [/* pattern left blank */]>, 2305 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2306 bits<4> dst; 2307 let Inst{27-4} = 0b000100101111111111110001; 2308 let Inst{3-0} = dst; 2309 } 2310} 2311 2312// SP is marked as a use to prevent stack-pointer assignments that appear 2313// immediately before calls from potentially appearing dead. 2314let isCall = 1, 2315 // FIXME: Do we really need a non-predicated version? If so, it should 2316 // at least be a pseudo instruction expanding to the predicated version 2317 // at MC lowering time. 2318 Defs = [LR], Uses = [SP] in { 2319 def BL : ABXI<0b1011, (outs), (ins arm_bl_target:$func), 2320 IIC_Br, "bl\t$func", 2321 [(ARMcall tglobaladdr:$func)]>, 2322 Requires<[IsARM]>, Sched<[WriteBrL]> { 2323 let Inst{31-28} = 0b1110; 2324 bits<24> func; 2325 let Inst{23-0} = func; 2326 let DecoderMethod = "DecodeBranchImmInstruction"; 2327 } 2328 2329 def BL_pred : ABI<0b1011, (outs), (ins arm_bl_target:$func), 2330 IIC_Br, "bl", "\t$func", 2331 [(ARMcall_pred tglobaladdr:$func)]>, 2332 Requires<[IsARM]>, Sched<[WriteBrL]> { 2333 bits<24> func; 2334 let Inst{23-0} = func; 2335 let DecoderMethod = "DecodeBranchImmInstruction"; 2336 } 2337 2338 // ARMv5T and above 2339 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm, 2340 IIC_Br, "blx\t$func", 2341 [(ARMcall GPR:$func)]>, 2342 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2343 bits<4> func; 2344 let Inst{31-4} = 0b1110000100101111111111110011; 2345 let Inst{3-0} = func; 2346 } 2347 2348 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm, 2349 IIC_Br, "blx", "\t$func", 2350 [(ARMcall_pred GPR:$func)]>, 2351 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2352 bits<4> func; 2353 let Inst{27-4} = 0b000100101111111111110011; 2354 let Inst{3-0} = func; 2355 } 2356 2357 // ARMv4T 2358 // Note: Restrict $func to the tGPR regclass to prevent it being in LR. 2359 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2360 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2361 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>; 2362 2363 // ARMv4 2364 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2365 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2366 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 2367 2368 // mov lr, pc; b if callee is marked noreturn to avoid confusing the 2369 // return stack predictor. 2370 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins arm_bl_target:$func), 2371 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>, 2372 Requires<[IsARM]>, Sched<[WriteBr]>; 2373} 2374 2375let isBranch = 1, isTerminator = 1 in { 2376 // FIXME: should be able to write a pattern for ARMBrcond, but can't use 2377 // a two-value operand where a dag node expects two operands. :( 2378 def Bcc : ABI<0b1010, (outs), (ins arm_br_target:$target), 2379 IIC_Br, "b", "\t$target", 2380 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>, 2381 Sched<[WriteBr]> { 2382 bits<24> target; 2383 let Inst{23-0} = target; 2384 let DecoderMethod = "DecodeBranchImmInstruction"; 2385 } 2386 2387 let isBarrier = 1 in { 2388 // B is "predicable" since it's just a Bcc with an 'always' condition. 2389 let isPredicable = 1 in 2390 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly 2391 // should be sufficient. 2392 // FIXME: Is B really a Barrier? That doesn't seem right. 2393 def B : ARMPseudoExpand<(outs), (ins arm_br_target:$target), 4, IIC_Br, 2394 [(br bb:$target)], (Bcc arm_br_target:$target, 2395 (ops 14, zero_reg))>, 2396 Sched<[WriteBr]>; 2397 2398 let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in { 2399 def BR_JTr : ARMPseudoInst<(outs), 2400 (ins GPR:$target, i32imm:$jt), 2401 0, IIC_Br, 2402 [(ARMbrjt GPR:$target, tjumptable:$jt)]>, 2403 Sched<[WriteBr]>; 2404 def BR_JTm_i12 : ARMPseudoInst<(outs), 2405 (ins addrmode_imm12:$target, i32imm:$jt), 2406 0, IIC_Br, 2407 [(ARMbrjt (i32 (load addrmode_imm12:$target)), 2408 tjumptable:$jt)]>, Sched<[WriteBrTbl]>; 2409 def BR_JTm_rs : ARMPseudoInst<(outs), 2410 (ins ldst_so_reg:$target, i32imm:$jt), 2411 0, IIC_Br, 2412 [(ARMbrjt (i32 (load ldst_so_reg:$target)), 2413 tjumptable:$jt)]>, Sched<[WriteBrTbl]>; 2414 def BR_JTadd : ARMPseudoInst<(outs), 2415 (ins GPR:$target, GPR:$idx, i32imm:$jt), 2416 0, IIC_Br, 2417 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>, 2418 Sched<[WriteBrTbl]>; 2419 } // isNotDuplicable = 1, isIndirectBranch = 1 2420 } // isBarrier = 1 2421 2422} 2423 2424// BLX (immediate) 2425def BLXi : AXI<(outs), (ins arm_blx_target:$target), BrMiscFrm, NoItinerary, 2426 "blx\t$target", []>, 2427 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2428 let Inst{31-25} = 0b1111101; 2429 bits<25> target; 2430 let Inst{23-0} = target{24-1}; 2431 let Inst{24} = target{0}; 2432 let isCall = 1; 2433} 2434 2435// Branch and Exchange Jazelle 2436def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func", 2437 [/* pattern left blank */]>, Sched<[WriteBr]> { 2438 bits<4> func; 2439 let Inst{23-20} = 0b0010; 2440 let Inst{19-8} = 0xfff; 2441 let Inst{7-4} = 0b0010; 2442 let Inst{3-0} = func; 2443 let isBranch = 1; 2444} 2445 2446// Tail calls. 2447 2448let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in { 2449 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>, 2450 Sched<[WriteBr]>; 2451 2452 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>, 2453 Sched<[WriteBr]>; 2454 2455 def TAILJMPd : ARMPseudoExpand<(outs), (ins arm_br_target:$dst), 2456 4, IIC_Br, [], 2457 (Bcc arm_br_target:$dst, (ops 14, zero_reg))>, 2458 Requires<[IsARM]>, Sched<[WriteBr]>; 2459 2460 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst), 2461 4, IIC_Br, [], 2462 (BX GPR:$dst)>, Sched<[WriteBr]>, 2463 Requires<[IsARM, HasV4T]>; 2464} 2465 2466// Secure Monitor Call is a system instruction. 2467def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", 2468 []>, Requires<[IsARM, HasTrustZone]> { 2469 bits<4> opt; 2470 let Inst{23-4} = 0b01100000000000000111; 2471 let Inst{3-0} = opt; 2472} 2473def : MnemonicAlias<"smi", "smc">; 2474 2475// Supervisor Call (Software Interrupt) 2476let isCall = 1, Uses = [SP] in { 2477def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>, 2478 Sched<[WriteBr]> { 2479 bits<24> svc; 2480 let Inst{23-0} = svc; 2481} 2482} 2483 2484// Store Return State 2485class SRSI<bit wb, string asm> 2486 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm, 2487 NoItinerary, asm, "", []> { 2488 bits<5> mode; 2489 let Inst{31-28} = 0b1111; 2490 let Inst{27-25} = 0b100; 2491 let Inst{22} = 1; 2492 let Inst{21} = wb; 2493 let Inst{20} = 0; 2494 let Inst{19-16} = 0b1101; // SP 2495 let Inst{15-5} = 0b00000101000; 2496 let Inst{4-0} = mode; 2497} 2498 2499def SRSDA : SRSI<0, "srsda\tsp, $mode"> { 2500 let Inst{24-23} = 0; 2501} 2502def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> { 2503 let Inst{24-23} = 0; 2504} 2505def SRSDB : SRSI<0, "srsdb\tsp, $mode"> { 2506 let Inst{24-23} = 0b10; 2507} 2508def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> { 2509 let Inst{24-23} = 0b10; 2510} 2511def SRSIA : SRSI<0, "srsia\tsp, $mode"> { 2512 let Inst{24-23} = 0b01; 2513} 2514def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> { 2515 let Inst{24-23} = 0b01; 2516} 2517def SRSIB : SRSI<0, "srsib\tsp, $mode"> { 2518 let Inst{24-23} = 0b11; 2519} 2520def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> { 2521 let Inst{24-23} = 0b11; 2522} 2523 2524def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>; 2525def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>; 2526 2527def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>; 2528def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>; 2529 2530def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>; 2531def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>; 2532 2533def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>; 2534def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>; 2535 2536// Return From Exception 2537class RFEI<bit wb, string asm> 2538 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm, 2539 NoItinerary, asm, "", []> { 2540 bits<4> Rn; 2541 let Inst{31-28} = 0b1111; 2542 let Inst{27-25} = 0b100; 2543 let Inst{22} = 0; 2544 let Inst{21} = wb; 2545 let Inst{20} = 1; 2546 let Inst{19-16} = Rn; 2547 let Inst{15-0} = 0xa00; 2548} 2549 2550def RFEDA : RFEI<0, "rfeda\t$Rn"> { 2551 let Inst{24-23} = 0; 2552} 2553def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> { 2554 let Inst{24-23} = 0; 2555} 2556def RFEDB : RFEI<0, "rfedb\t$Rn"> { 2557 let Inst{24-23} = 0b10; 2558} 2559def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> { 2560 let Inst{24-23} = 0b10; 2561} 2562def RFEIA : RFEI<0, "rfeia\t$Rn"> { 2563 let Inst{24-23} = 0b01; 2564} 2565def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> { 2566 let Inst{24-23} = 0b01; 2567} 2568def RFEIB : RFEI<0, "rfeib\t$Rn"> { 2569 let Inst{24-23} = 0b11; 2570} 2571def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> { 2572 let Inst{24-23} = 0b11; 2573} 2574 2575// Hypervisor Call is a system instruction 2576let isCall = 1 in { 2577def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary, 2578 "hvc", "\t$imm", []>, 2579 Requires<[IsARM, HasVirtualization]> { 2580 bits<16> imm; 2581 2582 // Even though HVC isn't predicable, it's encoding includes a condition field. 2583 // The instruction is undefined if the condition field is 0xf otherwise it is 2584 // unpredictable if it isn't condition AL (0xe). 2585 let Inst{31-28} = 0b1110; 2586 let Unpredictable{31-28} = 0b1111; 2587 let Inst{27-24} = 0b0001; 2588 let Inst{23-20} = 0b0100; 2589 let Inst{19-8} = imm{15-4}; 2590 let Inst{7-4} = 0b0111; 2591 let Inst{3-0} = imm{3-0}; 2592} 2593} 2594 2595// Return from exception in Hypervisor mode. 2596let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in 2597def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>, 2598 Requires<[IsARM, HasVirtualization]> { 2599 let Inst{23-0} = 0b011000000000000001101110; 2600} 2601 2602//===----------------------------------------------------------------------===// 2603// Load / Store Instructions. 2604// 2605 2606// Load 2607 2608 2609defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si, load>; 2610defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si, 2611 zextloadi8>; 2612defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si, store>; 2613defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si, 2614 truncstorei8>; 2615 2616// Special LDR for loads from non-pc-relative constpools. 2617let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0, 2618 isReMaterializable = 1, isCodeGenOnly = 1 in 2619def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 2620 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", 2621 []> { 2622 bits<4> Rt; 2623 bits<17> addr; 2624 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2625 let Inst{19-16} = 0b1111; 2626 let Inst{15-12} = Rt; 2627 let Inst{11-0} = addr{11-0}; // imm12 2628} 2629 2630// Loads with zero extension 2631def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2632 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr", 2633 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>; 2634 2635// Loads with sign extension 2636def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2637 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr", 2638 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>; 2639 2640def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2641 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr", 2642 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>; 2643 2644let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in { 2645 // Load doubleword 2646 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr), 2647 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>, 2648 Requires<[IsARM, HasV5TE]>; 2649} 2650 2651def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2652 NoItinerary, "lda", "\t$Rt, $addr", []>; 2653def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2654 NoItinerary, "ldab", "\t$Rt, $addr", []>; 2655def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2656 NoItinerary, "ldah", "\t$Rt, $addr", []>; 2657 2658// Indexed loads 2659multiclass AI2_ldridx<bit isByte, string opc, 2660 InstrItinClass iii, InstrItinClass iir> { 2661 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2662 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii, 2663 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2664 bits<17> addr; 2665 let Inst{25} = 0; 2666 let Inst{23} = addr{12}; 2667 let Inst{19-16} = addr{16-13}; 2668 let Inst{11-0} = addr{11-0}; 2669 let DecoderMethod = "DecodeLDRPreImm"; 2670 } 2671 2672 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2673 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir, 2674 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2675 bits<17> addr; 2676 let Inst{25} = 1; 2677 let Inst{23} = addr{12}; 2678 let Inst{19-16} = addr{16-13}; 2679 let Inst{11-0} = addr{11-0}; 2680 let Inst{4} = 0; 2681 let DecoderMethod = "DecodeLDRPreReg"; 2682 } 2683 2684 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2685 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2686 IndexModePost, LdFrm, iir, 2687 opc, "\t$Rt, $addr, $offset", 2688 "$addr.base = $Rn_wb", []> { 2689 // {12} isAdd 2690 // {11-0} imm12/Rm 2691 bits<14> offset; 2692 bits<4> addr; 2693 let Inst{25} = 1; 2694 let Inst{23} = offset{12}; 2695 let Inst{19-16} = addr; 2696 let Inst{11-0} = offset{11-0}; 2697 let Inst{4} = 0; 2698 2699 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2700 } 2701 2702 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2703 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2704 IndexModePost, LdFrm, iii, 2705 opc, "\t$Rt, $addr, $offset", 2706 "$addr.base = $Rn_wb", []> { 2707 // {12} isAdd 2708 // {11-0} imm12/Rm 2709 bits<14> offset; 2710 bits<4> addr; 2711 let Inst{25} = 0; 2712 let Inst{23} = offset{12}; 2713 let Inst{19-16} = addr; 2714 let Inst{11-0} = offset{11-0}; 2715 2716 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2717 } 2718 2719} 2720 2721let mayLoad = 1, hasSideEffects = 0 in { 2722// FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or 2723// IIC_iLoad_siu depending on whether it the offset register is shifted. 2724defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>; 2725defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>; 2726} 2727 2728multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> { 2729 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2730 (ins addrmode3_pre:$addr), IndexModePre, 2731 LdMiscFrm, itin, 2732 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2733 bits<14> addr; 2734 let Inst{23} = addr{8}; // U bit 2735 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2736 let Inst{19-16} = addr{12-9}; // Rn 2737 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2738 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2739 let DecoderMethod = "DecodeAddrMode3Instruction"; 2740 } 2741 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2742 (ins addr_offset_none:$addr, am3offset:$offset), 2743 IndexModePost, LdMiscFrm, itin, 2744 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", 2745 []> { 2746 bits<10> offset; 2747 bits<4> addr; 2748 let Inst{23} = offset{8}; // U bit 2749 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2750 let Inst{19-16} = addr; 2751 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2752 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2753 let DecoderMethod = "DecodeAddrMode3Instruction"; 2754 } 2755} 2756 2757let mayLoad = 1, hasSideEffects = 0 in { 2758defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>; 2759defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>; 2760defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>; 2761let hasExtraDefRegAllocReq = 1 in { 2762def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2763 (ins addrmode3_pre:$addr), IndexModePre, 2764 LdMiscFrm, IIC_iLoad_d_ru, 2765 "ldrd", "\t$Rt, $Rt2, $addr!", 2766 "$addr.base = $Rn_wb", []> { 2767 bits<14> addr; 2768 let Inst{23} = addr{8}; // U bit 2769 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2770 let Inst{19-16} = addr{12-9}; // Rn 2771 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2772 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2773 let DecoderMethod = "DecodeAddrMode3Instruction"; 2774} 2775def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2776 (ins addr_offset_none:$addr, am3offset:$offset), 2777 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru, 2778 "ldrd", "\t$Rt, $Rt2, $addr, $offset", 2779 "$addr.base = $Rn_wb", []> { 2780 bits<10> offset; 2781 bits<4> addr; 2782 let Inst{23} = offset{8}; // U bit 2783 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2784 let Inst{19-16} = addr; 2785 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2786 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2787 let DecoderMethod = "DecodeAddrMode3Instruction"; 2788} 2789} // hasExtraDefRegAllocReq = 1 2790} // mayLoad = 1, hasSideEffects = 0 2791 2792// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT. 2793let mayLoad = 1, hasSideEffects = 0 in { 2794def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2795 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2796 IndexModePost, LdFrm, IIC_iLoad_ru, 2797 "ldrt", "\t$Rt, $addr, $offset", 2798 "$addr.base = $Rn_wb", []> { 2799 // {12} isAdd 2800 // {11-0} imm12/Rm 2801 bits<14> offset; 2802 bits<4> addr; 2803 let Inst{25} = 1; 2804 let Inst{23} = offset{12}; 2805 let Inst{21} = 1; // overwrite 2806 let Inst{19-16} = addr; 2807 let Inst{11-5} = offset{11-5}; 2808 let Inst{4} = 0; 2809 let Inst{3-0} = offset{3-0}; 2810 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2811} 2812 2813def LDRT_POST_IMM 2814 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2815 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2816 IndexModePost, LdFrm, IIC_iLoad_ru, 2817 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2818 // {12} isAdd 2819 // {11-0} imm12/Rm 2820 bits<14> offset; 2821 bits<4> addr; 2822 let Inst{25} = 0; 2823 let Inst{23} = offset{12}; 2824 let Inst{21} = 1; // overwrite 2825 let Inst{19-16} = addr; 2826 let Inst{11-0} = offset{11-0}; 2827 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2828} 2829 2830def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2831 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2832 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2833 "ldrbt", "\t$Rt, $addr, $offset", 2834 "$addr.base = $Rn_wb", []> { 2835 // {12} isAdd 2836 // {11-0} imm12/Rm 2837 bits<14> offset; 2838 bits<4> addr; 2839 let Inst{25} = 1; 2840 let Inst{23} = offset{12}; 2841 let Inst{21} = 1; // overwrite 2842 let Inst{19-16} = addr; 2843 let Inst{11-5} = offset{11-5}; 2844 let Inst{4} = 0; 2845 let Inst{3-0} = offset{3-0}; 2846 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2847} 2848 2849def LDRBT_POST_IMM 2850 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2851 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2852 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2853 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2854 // {12} isAdd 2855 // {11-0} imm12/Rm 2856 bits<14> offset; 2857 bits<4> addr; 2858 let Inst{25} = 0; 2859 let Inst{23} = offset{12}; 2860 let Inst{21} = 1; // overwrite 2861 let Inst{19-16} = addr; 2862 let Inst{11-0} = offset{11-0}; 2863 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2864} 2865 2866multiclass AI3ldrT<bits<4> op, string opc> { 2867 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb), 2868 (ins addr_offset_none:$addr, postidx_imm8:$offset), 2869 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2870 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 2871 bits<9> offset; 2872 let Inst{23} = offset{8}; 2873 let Inst{22} = 1; 2874 let Inst{11-8} = offset{7-4}; 2875 let Inst{3-0} = offset{3-0}; 2876 } 2877 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb), 2878 (ins addr_offset_none:$addr, postidx_reg:$Rm), 2879 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2880 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 2881 bits<5> Rm; 2882 let Inst{23} = Rm{4}; 2883 let Inst{22} = 0; 2884 let Inst{11-8} = 0; 2885 let Unpredictable{11-8} = 0b1111; 2886 let Inst{3-0} = Rm{3-0}; 2887 let DecoderMethod = "DecodeLDR"; 2888 } 2889} 2890 2891defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">; 2892defm LDRHT : AI3ldrT<0b1011, "ldrht">; 2893defm LDRSHT : AI3ldrT<0b1111, "ldrsht">; 2894} 2895 2896def LDRT_POST 2897 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 2898 (outs GPR:$Rt)>; 2899 2900def LDRBT_POST 2901 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 2902 (outs GPR:$Rt)>; 2903 2904// Pseudo instruction ldr Rt, =immediate 2905def LDRConstPool 2906 : ARMAsmPseudo<"ldr${q} $Rt, $immediate", 2907 (ins const_pool_asm_imm:$immediate, pred:$q), 2908 (outs GPR:$Rt)>; 2909 2910// Store 2911 2912// Stores with truncate 2913def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm, 2914 IIC_iStore_bh_r, "strh", "\t$Rt, $addr", 2915 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>; 2916 2917// Store doubleword 2918let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { 2919 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr), 2920 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>, 2921 Requires<[IsARM, HasV5TE]> { 2922 let Inst{21} = 0; 2923 } 2924} 2925 2926// Indexed stores 2927multiclass AI2_stridx<bit isByte, string opc, 2928 InstrItinClass iii, InstrItinClass iir> { 2929 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2930 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre, 2931 StFrm, iii, 2932 opc, "\t$Rt, $addr!", 2933 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2934 bits<17> addr; 2935 let Inst{25} = 0; 2936 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2937 let Inst{19-16} = addr{16-13}; // Rn 2938 let Inst{11-0} = addr{11-0}; // imm12 2939 let DecoderMethod = "DecodeSTRPreImm"; 2940 } 2941 2942 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2943 (ins GPR:$Rt, ldst_so_reg:$addr), 2944 IndexModePre, StFrm, iir, 2945 opc, "\t$Rt, $addr!", 2946 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2947 bits<17> addr; 2948 let Inst{25} = 1; 2949 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2950 let Inst{19-16} = addr{16-13}; // Rn 2951 let Inst{11-0} = addr{11-0}; 2952 let Inst{4} = 0; // Inst{4} = 0 2953 let DecoderMethod = "DecodeSTRPreReg"; 2954 } 2955 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2956 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 2957 IndexModePost, StFrm, iir, 2958 opc, "\t$Rt, $addr, $offset", 2959 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2960 // {12} isAdd 2961 // {11-0} imm12/Rm 2962 bits<14> offset; 2963 bits<4> addr; 2964 let Inst{25} = 1; 2965 let Inst{23} = offset{12}; 2966 let Inst{19-16} = addr; 2967 let Inst{11-0} = offset{11-0}; 2968 let Inst{4} = 0; 2969 2970 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2971 } 2972 2973 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2974 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 2975 IndexModePost, StFrm, iii, 2976 opc, "\t$Rt, $addr, $offset", 2977 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2978 // {12} isAdd 2979 // {11-0} imm12/Rm 2980 bits<14> offset; 2981 bits<4> addr; 2982 let Inst{25} = 0; 2983 let Inst{23} = offset{12}; 2984 let Inst{19-16} = addr; 2985 let Inst{11-0} = offset{11-0}; 2986 2987 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2988 } 2989} 2990 2991let mayStore = 1, hasSideEffects = 0 in { 2992// FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or 2993// IIC_iStore_siu depending on whether it the offset register is shifted. 2994defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>; 2995defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>; 2996} 2997 2998def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 2999 am2offset_reg:$offset), 3000 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr, 3001 am2offset_reg:$offset)>; 3002def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 3003 am2offset_imm:$offset), 3004 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr, 3005 am2offset_imm:$offset)>; 3006def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 3007 am2offset_reg:$offset), 3008 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr, 3009 am2offset_reg:$offset)>; 3010def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 3011 am2offset_imm:$offset), 3012 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr, 3013 am2offset_imm:$offset)>; 3014 3015// Pseudo-instructions for pattern matching the pre-indexed stores. We can't 3016// put the patterns on the instruction definitions directly as ISel wants 3017// the address base and offset to be separate operands, not a single 3018// complex operand like we represent the instructions themselves. The 3019// pseudos map between the two. 3020let usesCustomInserter = 1, 3021 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in { 3022def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3023 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 3024 4, IIC_iStore_ru, 3025 [(set GPR:$Rn_wb, 3026 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 3027def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3028 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 3029 4, IIC_iStore_ru, 3030 [(set GPR:$Rn_wb, 3031 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 3032def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3033 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 3034 4, IIC_iStore_ru, 3035 [(set GPR:$Rn_wb, 3036 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 3037def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3038 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 3039 4, IIC_iStore_ru, 3040 [(set GPR:$Rn_wb, 3041 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 3042def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3043 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p), 3044 4, IIC_iStore_ru, 3045 [(set GPR:$Rn_wb, 3046 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>; 3047} 3048 3049 3050 3051def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb), 3052 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre, 3053 StMiscFrm, IIC_iStore_bh_ru, 3054 "strh", "\t$Rt, $addr!", 3055 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 3056 bits<14> addr; 3057 let Inst{23} = addr{8}; // U bit 3058 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 3059 let Inst{19-16} = addr{12-9}; // Rn 3060 let Inst{11-8} = addr{7-4}; // imm7_4/zero 3061 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 3062 let DecoderMethod = "DecodeAddrMode3Instruction"; 3063} 3064 3065def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb), 3066 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset), 3067 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, 3068 "strh", "\t$Rt, $addr, $offset", 3069 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", 3070 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt, 3071 addr_offset_none:$addr, 3072 am3offset:$offset))]> { 3073 bits<10> offset; 3074 bits<4> addr; 3075 let Inst{23} = offset{8}; // U bit 3076 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 3077 let Inst{19-16} = addr; 3078 let Inst{11-8} = offset{7-4}; // imm7_4/zero 3079 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 3080 let DecoderMethod = "DecodeAddrMode3Instruction"; 3081} 3082 3083let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { 3084def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb), 3085 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr), 3086 IndexModePre, StMiscFrm, IIC_iStore_d_ru, 3087 "strd", "\t$Rt, $Rt2, $addr!", 3088 "$addr.base = $Rn_wb", []> { 3089 bits<14> addr; 3090 let Inst{23} = addr{8}; // U bit 3091 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 3092 let Inst{19-16} = addr{12-9}; // Rn 3093 let Inst{11-8} = addr{7-4}; // imm7_4/zero 3094 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 3095 let DecoderMethod = "DecodeAddrMode3Instruction"; 3096} 3097 3098def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb), 3099 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr, 3100 am3offset:$offset), 3101 IndexModePost, StMiscFrm, IIC_iStore_d_ru, 3102 "strd", "\t$Rt, $Rt2, $addr, $offset", 3103 "$addr.base = $Rn_wb", []> { 3104 bits<10> offset; 3105 bits<4> addr; 3106 let Inst{23} = offset{8}; // U bit 3107 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 3108 let Inst{19-16} = addr; 3109 let Inst{11-8} = offset{7-4}; // imm7_4/zero 3110 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 3111 let DecoderMethod = "DecodeAddrMode3Instruction"; 3112} 3113} // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 3114 3115// STRT, STRBT, and STRHT 3116 3117def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 3118 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3119 IndexModePost, StFrm, IIC_iStore_bh_ru, 3120 "strbt", "\t$Rt, $addr, $offset", 3121 "$addr.base = $Rn_wb", []> { 3122 // {12} isAdd 3123 // {11-0} imm12/Rm 3124 bits<14> offset; 3125 bits<4> addr; 3126 let Inst{25} = 1; 3127 let Inst{23} = offset{12}; 3128 let Inst{21} = 1; // overwrite 3129 let Inst{19-16} = addr; 3130 let Inst{11-5} = offset{11-5}; 3131 let Inst{4} = 0; 3132 let Inst{3-0} = offset{3-0}; 3133 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3134} 3135 3136def STRBT_POST_IMM 3137 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 3138 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3139 IndexModePost, StFrm, IIC_iStore_bh_ru, 3140 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3141 // {12} isAdd 3142 // {11-0} imm12/Rm 3143 bits<14> offset; 3144 bits<4> addr; 3145 let Inst{25} = 0; 3146 let Inst{23} = offset{12}; 3147 let Inst{21} = 1; // overwrite 3148 let Inst{19-16} = addr; 3149 let Inst{11-0} = offset{11-0}; 3150 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3151} 3152 3153def STRBT_POST 3154 : ARMAsmPseudo<"strbt${q} $Rt, $addr", 3155 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 3156 3157let mayStore = 1, hasSideEffects = 0 in { 3158def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 3159 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3160 IndexModePost, StFrm, IIC_iStore_ru, 3161 "strt", "\t$Rt, $addr, $offset", 3162 "$addr.base = $Rn_wb", []> { 3163 // {12} isAdd 3164 // {11-0} imm12/Rm 3165 bits<14> offset; 3166 bits<4> addr; 3167 let Inst{25} = 1; 3168 let Inst{23} = offset{12}; 3169 let Inst{21} = 1; // overwrite 3170 let Inst{19-16} = addr; 3171 let Inst{11-5} = offset{11-5}; 3172 let Inst{4} = 0; 3173 let Inst{3-0} = offset{3-0}; 3174 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3175} 3176 3177def STRT_POST_IMM 3178 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 3179 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3180 IndexModePost, StFrm, IIC_iStore_ru, 3181 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3182 // {12} isAdd 3183 // {11-0} imm12/Rm 3184 bits<14> offset; 3185 bits<4> addr; 3186 let Inst{25} = 0; 3187 let Inst{23} = offset{12}; 3188 let Inst{21} = 1; // overwrite 3189 let Inst{19-16} = addr; 3190 let Inst{11-0} = offset{11-0}; 3191 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3192} 3193} 3194 3195def STRT_POST 3196 : ARMAsmPseudo<"strt${q} $Rt, $addr", 3197 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 3198 3199multiclass AI3strT<bits<4> op, string opc> { 3200 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 3201 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset), 3202 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 3203 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 3204 bits<9> offset; 3205 let Inst{23} = offset{8}; 3206 let Inst{22} = 1; 3207 let Inst{11-8} = offset{7-4}; 3208 let Inst{3-0} = offset{3-0}; 3209 } 3210 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 3211 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm), 3212 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 3213 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 3214 bits<5> Rm; 3215 let Inst{23} = Rm{4}; 3216 let Inst{22} = 0; 3217 let Inst{11-8} = 0; 3218 let Inst{3-0} = Rm{3-0}; 3219 } 3220} 3221 3222 3223defm STRHT : AI3strT<0b1011, "strht">; 3224 3225def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3226 NoItinerary, "stl", "\t$Rt, $addr", []>; 3227def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3228 NoItinerary, "stlb", "\t$Rt, $addr", []>; 3229def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3230 NoItinerary, "stlh", "\t$Rt, $addr", []>; 3231 3232//===----------------------------------------------------------------------===// 3233// Load / store multiple Instructions. 3234// 3235 3236multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f, 3237 InstrItinClass itin, InstrItinClass itin_upd> { 3238 // IA is the default, so no need for an explicit suffix on the 3239 // mnemonic here. Without it is the canonical spelling. 3240 def IA : 3241 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3242 IndexModeNone, f, itin, 3243 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> { 3244 let Inst{24-23} = 0b01; // Increment After 3245 let Inst{22} = P_bit; 3246 let Inst{21} = 0; // No writeback 3247 let Inst{20} = L_bit; 3248 } 3249 def IA_UPD : 3250 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3251 IndexModeUpd, f, itin_upd, 3252 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3253 let Inst{24-23} = 0b01; // Increment After 3254 let Inst{22} = P_bit; 3255 let Inst{21} = 1; // Writeback 3256 let Inst{20} = L_bit; 3257 3258 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3259 } 3260 def DA : 3261 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3262 IndexModeNone, f, itin, 3263 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> { 3264 let Inst{24-23} = 0b00; // Decrement After 3265 let Inst{22} = P_bit; 3266 let Inst{21} = 0; // No writeback 3267 let Inst{20} = L_bit; 3268 } 3269 def DA_UPD : 3270 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3271 IndexModeUpd, f, itin_upd, 3272 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3273 let Inst{24-23} = 0b00; // Decrement After 3274 let Inst{22} = P_bit; 3275 let Inst{21} = 1; // Writeback 3276 let Inst{20} = L_bit; 3277 3278 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3279 } 3280 def DB : 3281 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3282 IndexModeNone, f, itin, 3283 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> { 3284 let Inst{24-23} = 0b10; // Decrement Before 3285 let Inst{22} = P_bit; 3286 let Inst{21} = 0; // No writeback 3287 let Inst{20} = L_bit; 3288 } 3289 def DB_UPD : 3290 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3291 IndexModeUpd, f, itin_upd, 3292 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3293 let Inst{24-23} = 0b10; // Decrement Before 3294 let Inst{22} = P_bit; 3295 let Inst{21} = 1; // Writeback 3296 let Inst{20} = L_bit; 3297 3298 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3299 } 3300 def IB : 3301 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3302 IndexModeNone, f, itin, 3303 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> { 3304 let Inst{24-23} = 0b11; // Increment Before 3305 let Inst{22} = P_bit; 3306 let Inst{21} = 0; // No writeback 3307 let Inst{20} = L_bit; 3308 } 3309 def IB_UPD : 3310 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3311 IndexModeUpd, f, itin_upd, 3312 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3313 let Inst{24-23} = 0b11; // Increment Before 3314 let Inst{22} = P_bit; 3315 let Inst{21} = 1; // Writeback 3316 let Inst{20} = L_bit; 3317 3318 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3319 } 3320} 3321 3322let hasSideEffects = 0 in { 3323 3324let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 3325defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m, 3326 IIC_iLoad_mu>, ComplexDeprecationPredicate<"ARMLoad">; 3327 3328let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3329defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m, 3330 IIC_iStore_mu>, 3331 ComplexDeprecationPredicate<"ARMStore">; 3332 3333} // hasSideEffects 3334 3335// FIXME: remove when we have a way to marking a MI with these properties. 3336// FIXME: Should pc be an implicit operand like PICADD, etc? 3337let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 3338 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in 3339def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, 3340 reglist:$regs, variable_ops), 3341 4, IIC_iLoad_mBr, [], 3342 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, 3343 RegConstraint<"$Rn = $wb">; 3344 3345let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 3346defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m, 3347 IIC_iLoad_mu>; 3348 3349let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3350defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m, 3351 IIC_iStore_mu>; 3352 3353 3354 3355//===----------------------------------------------------------------------===// 3356// Move Instructions. 3357// 3358 3359let hasSideEffects = 0, isMoveReg = 1 in 3360def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr, 3361 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3362 bits<4> Rd; 3363 bits<4> Rm; 3364 3365 let Inst{19-16} = 0b0000; 3366 let Inst{11-4} = 0b00000000; 3367 let Inst{25} = 0; 3368 let Inst{3-0} = Rm; 3369 let Inst{15-12} = Rd; 3370} 3371 3372// A version for the smaller set of tail call registers. 3373let hasSideEffects = 0 in 3374def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm, 3375 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3376 bits<4> Rd; 3377 bits<4> Rm; 3378 3379 let Inst{11-4} = 0b00000000; 3380 let Inst{25} = 0; 3381 let Inst{3-0} = Rm; 3382 let Inst{15-12} = Rd; 3383} 3384 3385def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src), 3386 DPSoRegRegFrm, IIC_iMOVsr, 3387 "mov", "\t$Rd, $src", 3388 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP, 3389 Sched<[WriteALU]> { 3390 bits<4> Rd; 3391 bits<12> src; 3392 let Inst{15-12} = Rd; 3393 let Inst{19-16} = 0b0000; 3394 let Inst{11-8} = src{11-8}; 3395 let Inst{7} = 0; 3396 let Inst{6-5} = src{6-5}; 3397 let Inst{4} = 1; 3398 let Inst{3-0} = src{3-0}; 3399 let Inst{25} = 0; 3400} 3401 3402def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src), 3403 DPSoRegImmFrm, IIC_iMOVsr, 3404 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>, 3405 UnaryDP, Sched<[WriteALU]> { 3406 bits<4> Rd; 3407 bits<12> src; 3408 let Inst{15-12} = Rd; 3409 let Inst{19-16} = 0b0000; 3410 let Inst{11-5} = src{11-5}; 3411 let Inst{4} = 0; 3412 let Inst{3-0} = src{3-0}; 3413 let Inst{25} = 0; 3414} 3415 3416let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3417def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi, 3418 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP, 3419 Sched<[WriteALU]> { 3420 bits<4> Rd; 3421 bits<12> imm; 3422 let Inst{25} = 1; 3423 let Inst{15-12} = Rd; 3424 let Inst{19-16} = 0b0000; 3425 let Inst{11-0} = imm; 3426} 3427 3428let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3429def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm), 3430 DPFrm, IIC_iMOVi, 3431 "movw", "\t$Rd, $imm", 3432 [(set GPR:$Rd, imm0_65535:$imm)]>, 3433 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> { 3434 bits<4> Rd; 3435 bits<16> imm; 3436 let Inst{15-12} = Rd; 3437 let Inst{11-0} = imm{11-0}; 3438 let Inst{19-16} = imm{15-12}; 3439 let Inst{20} = 0; 3440 let Inst{25} = 1; 3441 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3442} 3443 3444def : InstAlias<"mov${p} $Rd, $imm", 3445 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p), 0>, 3446 Requires<[IsARM, HasV6T2]>; 3447 3448def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3449 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3450 Sched<[WriteALU]>; 3451 3452let Constraints = "$src = $Rd" in { 3453def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd), 3454 (ins GPR:$src, imm0_65535_expr:$imm), 3455 DPFrm, IIC_iMOVi, 3456 "movt", "\t$Rd, $imm", 3457 [(set GPRnopc:$Rd, 3458 (or (and GPR:$src, 0xffff), 3459 lo16AllZero:$imm))]>, UnaryDP, 3460 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> { 3461 bits<4> Rd; 3462 bits<16> imm; 3463 let Inst{15-12} = Rd; 3464 let Inst{11-0} = imm{11-0}; 3465 let Inst{19-16} = imm{15-12}; 3466 let Inst{20} = 0; 3467 let Inst{25} = 1; 3468 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3469} 3470 3471def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3472 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3473 Sched<[WriteALU]>; 3474 3475} // Constraints 3476 3477def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>, 3478 Requires<[IsARM, HasV6T2]>; 3479 3480let Uses = [CPSR] in 3481def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi, 3482 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP, 3483 Requires<[IsARM]>, Sched<[WriteALU]>; 3484 3485// These aren't really mov instructions, but we have to define them this way 3486// due to flag operands. 3487 3488let Defs = [CPSR] in { 3489def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3490 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP, 3491 Sched<[WriteALU]>, Requires<[IsARM]>; 3492def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3493 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP, 3494 Sched<[WriteALU]>, Requires<[IsARM]>; 3495} 3496 3497//===----------------------------------------------------------------------===// 3498// Extend Instructions. 3499// 3500 3501// Sign extenders 3502 3503def SXTB : AI_ext_rrot<0b01101010, 3504 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 3505def SXTH : AI_ext_rrot<0b01101011, 3506 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 3507 3508def SXTAB : AI_exta_rrot<0b01101010, 3509 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 3510def SXTAH : AI_exta_rrot<0b01101011, 3511 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 3512 3513def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, rot_imm:$rot), i8)), 3514 (SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3515def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, imm8_or_16:$rot), 3516 i16)), 3517 (SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3518 3519def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">; 3520def : ARMV6Pat<(int_arm_sxtb16 GPR:$Src), 3521 (SXTB16 GPR:$Src, 0)>; 3522 3523def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">; 3524def : ARMV6Pat<(int_arm_sxtab16 GPR:$LHS, GPR:$RHS), 3525 (SXTAB16 GPR:$LHS, GPR:$RHS, 0)>; 3526 3527// Zero extenders 3528 3529let AddedComplexity = 16 in { 3530def UXTB : AI_ext_rrot<0b01101110, 3531 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 3532def UXTH : AI_ext_rrot<0b01101111, 3533 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 3534def UXTB16 : AI_ext_rrot<0b01101100, 3535 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 3536 3537// FIXME: This pattern incorrectly assumes the shl operator is a rotate. 3538// The transformation should probably be done as a combiner action 3539// instead so we can include a check for masking back in the upper 3540// eight bits of the source into the lower eight bits of the result. 3541//def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 3542// (UXTB16r_rot GPR:$Src, 3)>; 3543def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 3544 (UXTB16 GPR:$Src, 1)>; 3545def : ARMV6Pat<(int_arm_uxtb16 GPR:$Src), 3546 (UXTB16 GPR:$Src, 0)>; 3547 3548def UXTAB : AI_exta_rrot<0b01101110, "uxtab", 3549 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 3550def UXTAH : AI_exta_rrot<0b01101111, "uxtah", 3551 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 3552 3553def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot), 0xFF)), 3554 (UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3555def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot), 0xFFFF)), 3556 (UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3557} 3558 3559// This isn't safe in general, the add is two 16-bit units, not a 32-bit add. 3560def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">; 3561def : ARMV6Pat<(int_arm_uxtab16 GPR:$LHS, GPR:$RHS), 3562 (UXTAB16 GPR:$LHS, GPR:$RHS, 0)>; 3563 3564 3565def SBFX : I<(outs GPRnopc:$Rd), 3566 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3567 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3568 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3569 Requires<[IsARM, HasV6T2]> { 3570 bits<4> Rd; 3571 bits<4> Rn; 3572 bits<5> lsb; 3573 bits<5> width; 3574 let Inst{27-21} = 0b0111101; 3575 let Inst{6-4} = 0b101; 3576 let Inst{20-16} = width; 3577 let Inst{15-12} = Rd; 3578 let Inst{11-7} = lsb; 3579 let Inst{3-0} = Rn; 3580} 3581 3582def UBFX : I<(outs GPRnopc:$Rd), 3583 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3584 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3585 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3586 Requires<[IsARM, HasV6T2]> { 3587 bits<4> Rd; 3588 bits<4> Rn; 3589 bits<5> lsb; 3590 bits<5> width; 3591 let Inst{27-21} = 0b0111111; 3592 let Inst{6-4} = 0b101; 3593 let Inst{20-16} = width; 3594 let Inst{15-12} = Rd; 3595 let Inst{11-7} = lsb; 3596 let Inst{3-0} = Rn; 3597} 3598 3599//===----------------------------------------------------------------------===// 3600// Arithmetic Instructions. 3601// 3602 3603let isAdd = 1 in 3604defm ADD : AsI1_bin_irs<0b0100, "add", 3605 IIC_iALUi, IIC_iALUr, IIC_iALUsr, add, 1>; 3606defm SUB : AsI1_bin_irs<0b0010, "sub", 3607 IIC_iALUi, IIC_iALUr, IIC_iALUsr, sub>; 3608 3609// ADD and SUB with 's' bit set. 3610// 3611// Currently, ADDS/SUBS are pseudo opcodes that exist only in the 3612// selection DAG. They are "lowered" to real ADD/SUB opcodes by 3613// AdjustInstrPostInstrSelection where we determine whether or not to 3614// set the "s" bit based on CPSR liveness. 3615// 3616// FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen 3617// support for an optional CPSR definition that corresponds to the DAG 3618// node's second value. We can then eliminate the implicit def of CPSR. 3619let isAdd = 1 in 3620defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMaddc, 1>; 3621defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>; 3622 3623let isAdd = 1 in 3624defm ADC : AI1_adde_sube_irs<0b0101, "adc", ARMadde, 1>; 3625defm SBC : AI1_adde_sube_irs<0b0110, "sbc", ARMsube>; 3626 3627defm RSB : AsI1_rbin_irs<0b0011, "rsb", 3628 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3629 sub>; 3630 3631// FIXME: Eliminate them if we can write def : Pat patterns which defines 3632// CPSR and the implicit def of CPSR is not needed. 3633defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>; 3634 3635defm RSC : AI1_rsc_irs<0b0111, "rsc", ARMsube>; 3636 3637// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 3638// The assume-no-carry-in form uses the negation of the input since add/sub 3639// assume opposite meanings of the carry flag (i.e., carry == !borrow). 3640// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory 3641// details. 3642def : ARMPat<(add GPR:$src, mod_imm_neg:$imm), 3643 (SUBri GPR:$src, mod_imm_neg:$imm)>; 3644def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm), 3645 (SUBSri GPR:$src, mod_imm_neg:$imm)>; 3646 3647def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm), 3648 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3649 Requires<[IsARM, HasV6T2]>; 3650def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm), 3651 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3652 Requires<[IsARM, HasV6T2]>; 3653 3654// The with-carry-in form matches bitwise not instead of the negation. 3655// Effectively, the inverse interpretation of the carry flag already accounts 3656// for part of the negation. 3657def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR), 3658 (SBCri GPR:$src, mod_imm_not:$imm)>; 3659def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR), 3660 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>, 3661 Requires<[IsARM, HasV6T2]>; 3662 3663// Note: These are implemented in C++ code, because they have to generate 3664// ADD/SUBrs instructions, which use a complex pattern that a xform function 3665// cannot produce. 3666// (mul X, 2^n+1) -> (add (X << n), X) 3667// (mul X, 2^n-1) -> (rsb X, (X << n)) 3668 3669// ARM Arithmetic Instruction 3670// GPR:$dst = GPR:$a op GPR:$b 3671class AAI<bits<8> op27_20, bits<8> op11_4, string opc, 3672 list<dag> pattern = [], 3673 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm), 3674 string asm = "\t$Rd, $Rn, $Rm"> 3675 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>, 3676 Sched<[WriteALU, ReadALU, ReadALU]> { 3677 bits<4> Rn; 3678 bits<4> Rd; 3679 bits<4> Rm; 3680 let Inst{27-20} = op27_20; 3681 let Inst{11-4} = op11_4; 3682 let Inst{19-16} = Rn; 3683 let Inst{15-12} = Rd; 3684 let Inst{3-0} = Rm; 3685 3686 let Unpredictable{11-8} = 0b1111; 3687} 3688 3689// Wrappers around the AAI class 3690class AAIRevOpr<bits<8> op27_20, bits<8> op11_4, string opc, 3691 list<dag> pattern = []> 3692 : AAI<op27_20, op11_4, opc, 3693 pattern, 3694 (ins GPRnopc:$Rm, GPRnopc:$Rn), 3695 "\t$Rd, $Rm, $Rn">; 3696 3697class AAIIntrinsic<bits<8> op27_20, bits<8> op11_4, string opc, 3698 Intrinsic intrinsic> 3699 : AAI<op27_20, op11_4, opc, 3700 [(set GPRnopc:$Rd, (intrinsic GPRnopc:$Rn, GPRnopc:$Rm))]>; 3701 3702// Saturating add/subtract 3703let hasSideEffects = 1 in { 3704def QADD8 : AAIIntrinsic<0b01100010, 0b11111001, "qadd8", int_arm_qadd8>; 3705def QADD16 : AAIIntrinsic<0b01100010, 0b11110001, "qadd16", int_arm_qadd16>; 3706def QSUB16 : AAIIntrinsic<0b01100010, 0b11110111, "qsub16", int_arm_qsub16>; 3707def QSUB8 : AAIIntrinsic<0b01100010, 0b11111111, "qsub8", int_arm_qsub8>; 3708 3709def QDADD : AAIRevOpr<0b00010100, 0b00000101, "qdadd", 3710 [(set GPRnopc:$Rd, (int_arm_qadd (int_arm_qadd GPRnopc:$Rm, 3711 GPRnopc:$Rm), 3712 GPRnopc:$Rn))]>; 3713def QDSUB : AAIRevOpr<0b00010110, 0b00000101, "qdsub", 3714 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, 3715 (int_arm_qadd GPRnopc:$Rn, GPRnopc:$Rn)))]>; 3716def QSUB : AAIRevOpr<0b00010010, 0b00000101, "qsub", 3717 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))]>; 3718let DecoderMethod = "DecodeQADDInstruction" in 3719 def QADD : AAIRevOpr<0b00010000, 0b00000101, "qadd", 3720 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))]>; 3721} 3722 3723def UQADD16 : AAIIntrinsic<0b01100110, 0b11110001, "uqadd16", int_arm_uqadd16>; 3724def UQADD8 : AAIIntrinsic<0b01100110, 0b11111001, "uqadd8", int_arm_uqadd8>; 3725def UQSUB16 : AAIIntrinsic<0b01100110, 0b11110111, "uqsub16", int_arm_uqsub16>; 3726def UQSUB8 : AAIIntrinsic<0b01100110, 0b11111111, "uqsub8", int_arm_uqsub8>; 3727def QASX : AAIIntrinsic<0b01100010, 0b11110011, "qasx", int_arm_qasx>; 3728def QSAX : AAIIntrinsic<0b01100010, 0b11110101, "qsax", int_arm_qsax>; 3729def UQASX : AAIIntrinsic<0b01100110, 0b11110011, "uqasx", int_arm_uqasx>; 3730def UQSAX : AAIIntrinsic<0b01100110, 0b11110101, "uqsax", int_arm_uqsax>; 3731 3732// Signed/Unsigned add/subtract 3733 3734def SASX : AAIIntrinsic<0b01100001, 0b11110011, "sasx", int_arm_sasx>; 3735def SADD16 : AAIIntrinsic<0b01100001, 0b11110001, "sadd16", int_arm_sadd16>; 3736def SADD8 : AAIIntrinsic<0b01100001, 0b11111001, "sadd8", int_arm_sadd8>; 3737def SSAX : AAIIntrinsic<0b01100001, 0b11110101, "ssax", int_arm_ssax>; 3738def SSUB16 : AAIIntrinsic<0b01100001, 0b11110111, "ssub16", int_arm_ssub16>; 3739def SSUB8 : AAIIntrinsic<0b01100001, 0b11111111, "ssub8", int_arm_ssub8>; 3740def UASX : AAIIntrinsic<0b01100101, 0b11110011, "uasx", int_arm_uasx>; 3741def UADD16 : AAIIntrinsic<0b01100101, 0b11110001, "uadd16", int_arm_uadd16>; 3742def UADD8 : AAIIntrinsic<0b01100101, 0b11111001, "uadd8", int_arm_uadd8>; 3743def USAX : AAIIntrinsic<0b01100101, 0b11110101, "usax", int_arm_usax>; 3744def USUB16 : AAIIntrinsic<0b01100101, 0b11110111, "usub16", int_arm_usub16>; 3745def USUB8 : AAIIntrinsic<0b01100101, 0b11111111, "usub8", int_arm_usub8>; 3746 3747// Signed/Unsigned halving add/subtract 3748 3749def SHASX : AAIIntrinsic<0b01100011, 0b11110011, "shasx", int_arm_shasx>; 3750def SHADD16 : AAIIntrinsic<0b01100011, 0b11110001, "shadd16", int_arm_shadd16>; 3751def SHADD8 : AAIIntrinsic<0b01100011, 0b11111001, "shadd8", int_arm_shadd8>; 3752def SHSAX : AAIIntrinsic<0b01100011, 0b11110101, "shsax", int_arm_shsax>; 3753def SHSUB16 : AAIIntrinsic<0b01100011, 0b11110111, "shsub16", int_arm_shsub16>; 3754def SHSUB8 : AAIIntrinsic<0b01100011, 0b11111111, "shsub8", int_arm_shsub8>; 3755def UHASX : AAIIntrinsic<0b01100111, 0b11110011, "uhasx", int_arm_uhasx>; 3756def UHADD16 : AAIIntrinsic<0b01100111, 0b11110001, "uhadd16", int_arm_uhadd16>; 3757def UHADD8 : AAIIntrinsic<0b01100111, 0b11111001, "uhadd8", int_arm_uhadd8>; 3758def UHSAX : AAIIntrinsic<0b01100111, 0b11110101, "uhsax", int_arm_uhsax>; 3759def UHSUB16 : AAIIntrinsic<0b01100111, 0b11110111, "uhsub16", int_arm_uhsub16>; 3760def UHSUB8 : AAIIntrinsic<0b01100111, 0b11111111, "uhsub8", int_arm_uhsub8>; 3761 3762// Unsigned Sum of Absolute Differences [and Accumulate]. 3763 3764def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3765 MulFrm /* for convenience */, NoItinerary, "usad8", 3766 "\t$Rd, $Rn, $Rm", 3767 [(set GPR:$Rd, (int_arm_usad8 GPR:$Rn, GPR:$Rm))]>, 3768 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> { 3769 bits<4> Rd; 3770 bits<4> Rn; 3771 bits<4> Rm; 3772 let Inst{27-20} = 0b01111000; 3773 let Inst{15-12} = 0b1111; 3774 let Inst{7-4} = 0b0001; 3775 let Inst{19-16} = Rd; 3776 let Inst{11-8} = Rm; 3777 let Inst{3-0} = Rn; 3778} 3779def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3780 MulFrm /* for convenience */, NoItinerary, "usada8", 3781 "\t$Rd, $Rn, $Rm, $Ra", 3782 [(set GPR:$Rd, (int_arm_usada8 GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, 3783 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{ 3784 bits<4> Rd; 3785 bits<4> Rn; 3786 bits<4> Rm; 3787 bits<4> Ra; 3788 let Inst{27-20} = 0b01111000; 3789 let Inst{7-4} = 0b0001; 3790 let Inst{19-16} = Rd; 3791 let Inst{15-12} = Ra; 3792 let Inst{11-8} = Rm; 3793 let Inst{3-0} = Rn; 3794} 3795 3796// Signed/Unsigned saturate 3797def SSAT : AI<(outs GPRnopc:$Rd), 3798 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3799 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []>, 3800 Requires<[IsARM,HasV6]>{ 3801 bits<4> Rd; 3802 bits<5> sat_imm; 3803 bits<4> Rn; 3804 bits<8> sh; 3805 let Inst{27-21} = 0b0110101; 3806 let Inst{5-4} = 0b01; 3807 let Inst{20-16} = sat_imm; 3808 let Inst{15-12} = Rd; 3809 let Inst{11-7} = sh{4-0}; 3810 let Inst{6} = sh{5}; 3811 let Inst{3-0} = Rn; 3812} 3813 3814def SSAT16 : AI<(outs GPRnopc:$Rd), 3815 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm, 3816 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []>, 3817 Requires<[IsARM,HasV6]>{ 3818 bits<4> Rd; 3819 bits<4> sat_imm; 3820 bits<4> Rn; 3821 let Inst{27-20} = 0b01101010; 3822 let Inst{11-4} = 0b11110011; 3823 let Inst{15-12} = Rd; 3824 let Inst{19-16} = sat_imm; 3825 let Inst{3-0} = Rn; 3826} 3827 3828def USAT : AI<(outs GPRnopc:$Rd), 3829 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3830 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []>, 3831 Requires<[IsARM,HasV6]> { 3832 bits<4> Rd; 3833 bits<5> sat_imm; 3834 bits<4> Rn; 3835 bits<8> sh; 3836 let Inst{27-21} = 0b0110111; 3837 let Inst{5-4} = 0b01; 3838 let Inst{15-12} = Rd; 3839 let Inst{11-7} = sh{4-0}; 3840 let Inst{6} = sh{5}; 3841 let Inst{20-16} = sat_imm; 3842 let Inst{3-0} = Rn; 3843} 3844 3845def USAT16 : AI<(outs GPRnopc:$Rd), 3846 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm, 3847 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []>, 3848 Requires<[IsARM,HasV6]>{ 3849 bits<4> Rd; 3850 bits<4> sat_imm; 3851 bits<4> Rn; 3852 let Inst{27-20} = 0b01101110; 3853 let Inst{11-4} = 0b11110011; 3854 let Inst{15-12} = Rd; 3855 let Inst{19-16} = sat_imm; 3856 let Inst{3-0} = Rn; 3857} 3858 3859def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm1_32:$pos), 3860 (SSAT imm1_32:$pos, GPRnopc:$a, 0)>; 3861def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm0_31:$pos), 3862 (USAT imm0_31:$pos, GPRnopc:$a, 0)>; 3863def : ARMPat<(ARMssatnoshift GPRnopc:$Rn, imm0_31:$imm), 3864 (SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>; 3865def : ARMPat<(ARMusatnoshift GPRnopc:$Rn, imm0_31:$imm), 3866 (USAT imm0_31:$imm, GPRnopc:$Rn, 0)>; 3867def : ARMV6Pat<(int_arm_ssat16 GPRnopc:$a, imm1_16:$pos), 3868 (SSAT16 imm1_16:$pos, GPRnopc:$a)>; 3869def : ARMV6Pat<(int_arm_usat16 GPRnopc:$a, imm0_15:$pos), 3870 (USAT16 imm0_15:$pos, GPRnopc:$a)>; 3871 3872//===----------------------------------------------------------------------===// 3873// Bitwise Instructions. 3874// 3875 3876defm AND : AsI1_bin_irs<0b0000, "and", 3877 IIC_iBITi, IIC_iBITr, IIC_iBITsr, and, 1>; 3878defm ORR : AsI1_bin_irs<0b1100, "orr", 3879 IIC_iBITi, IIC_iBITr, IIC_iBITsr, or, 1>; 3880defm EOR : AsI1_bin_irs<0b0001, "eor", 3881 IIC_iBITi, IIC_iBITr, IIC_iBITsr, xor, 1>; 3882defm BIC : AsI1_bin_irs<0b1110, "bic", 3883 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3884 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 3885 3886// FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just 3887// like in the actual instruction encoding. The complexity of mapping the mask 3888// to the lsb/msb pair should be handled by ISel, not encapsulated in the 3889// instruction description. 3890def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm), 3891 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3892 "bfc", "\t$Rd, $imm", "$src = $Rd", 3893 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>, 3894 Requires<[IsARM, HasV6T2]> { 3895 bits<4> Rd; 3896 bits<10> imm; 3897 let Inst{27-21} = 0b0111110; 3898 let Inst{6-0} = 0b0011111; 3899 let Inst{15-12} = Rd; 3900 let Inst{11-7} = imm{4-0}; // lsb 3901 let Inst{20-16} = imm{9-5}; // msb 3902} 3903 3904// A8.6.18 BFI - Bitfield insert (Encoding A1) 3905def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm), 3906 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3907 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd", 3908 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn, 3909 bf_inv_mask_imm:$imm))]>, 3910 Requires<[IsARM, HasV6T2]> { 3911 bits<4> Rd; 3912 bits<4> Rn; 3913 bits<10> imm; 3914 let Inst{27-21} = 0b0111110; 3915 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15 3916 let Inst{15-12} = Rd; 3917 let Inst{11-7} = imm{4-0}; // lsb 3918 let Inst{20-16} = imm{9-5}; // width 3919 let Inst{3-0} = Rn; 3920} 3921 3922def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr, 3923 "mvn", "\t$Rd, $Rm", 3924 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> { 3925 bits<4> Rd; 3926 bits<4> Rm; 3927 let Inst{25} = 0; 3928 let Inst{19-16} = 0b0000; 3929 let Inst{11-4} = 0b00000000; 3930 let Inst{15-12} = Rd; 3931 let Inst{3-0} = Rm; 3932 3933 let Unpredictable{19-16} = 0b1111; 3934} 3935def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift), 3936 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3937 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP, 3938 Sched<[WriteALU]> { 3939 bits<4> Rd; 3940 bits<12> shift; 3941 let Inst{25} = 0; 3942 let Inst{19-16} = 0b0000; 3943 let Inst{15-12} = Rd; 3944 let Inst{11-5} = shift{11-5}; 3945 let Inst{4} = 0; 3946 let Inst{3-0} = shift{3-0}; 3947 3948 let Unpredictable{19-16} = 0b1111; 3949} 3950def MVNsr : AsI1<0b1111, (outs GPRnopc:$Rd), (ins so_reg_reg:$shift), 3951 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3952 [(set GPRnopc:$Rd, (not so_reg_reg:$shift))]>, UnaryDP, 3953 Sched<[WriteALU]> { 3954 bits<4> Rd; 3955 bits<12> shift; 3956 let Inst{25} = 0; 3957 let Inst{19-16} = 0b0000; 3958 let Inst{15-12} = Rd; 3959 let Inst{11-8} = shift{11-8}; 3960 let Inst{7} = 0; 3961 let Inst{6-5} = shift{6-5}; 3962 let Inst{4} = 1; 3963 let Inst{3-0} = shift{3-0}; 3964 3965 let Unpredictable{19-16} = 0b1111; 3966} 3967let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3968def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, 3969 IIC_iMVNi, "mvn", "\t$Rd, $imm", 3970 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> { 3971 bits<4> Rd; 3972 bits<12> imm; 3973 let Inst{25} = 1; 3974 let Inst{19-16} = 0b0000; 3975 let Inst{15-12} = Rd; 3976 let Inst{11-0} = imm; 3977} 3978 3979let AddedComplexity = 1 in 3980def : ARMPat<(and GPR:$src, mod_imm_not:$imm), 3981 (BICri GPR:$src, mod_imm_not:$imm)>; 3982 3983//===----------------------------------------------------------------------===// 3984// Multiply Instructions. 3985// 3986class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3987 string opc, string asm, list<dag> pattern> 3988 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3989 bits<4> Rd; 3990 bits<4> Rm; 3991 bits<4> Rn; 3992 let Inst{19-16} = Rd; 3993 let Inst{11-8} = Rm; 3994 let Inst{3-0} = Rn; 3995} 3996class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3997 string opc, string asm, list<dag> pattern> 3998 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3999 bits<4> RdLo; 4000 bits<4> RdHi; 4001 bits<4> Rm; 4002 bits<4> Rn; 4003 let Inst{19-16} = RdHi; 4004 let Inst{15-12} = RdLo; 4005 let Inst{11-8} = Rm; 4006 let Inst{3-0} = Rn; 4007} 4008class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 4009 string opc, string asm, list<dag> pattern> 4010 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 4011 bits<4> RdLo; 4012 bits<4> RdHi; 4013 bits<4> Rm; 4014 bits<4> Rn; 4015 let Inst{19-16} = RdHi; 4016 let Inst{15-12} = RdLo; 4017 let Inst{11-8} = Rm; 4018 let Inst{3-0} = Rn; 4019} 4020 4021// FIXME: The v5 pseudos are only necessary for the additional Constraint 4022// property. Remove them when it's possible to add those properties 4023// on an individual MachineInstr, not just an instruction description. 4024let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in { 4025def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd), 4026 (ins GPRnopc:$Rn, GPRnopc:$Rm), 4027 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", 4028 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>, 4029 Requires<[IsARM, HasV6]>, 4030 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 4031 let Inst{15-12} = 0b0000; 4032 let Unpredictable{15-12} = 0b1111; 4033} 4034 4035let Constraints = "@earlyclobber $Rd" in 4036def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, 4037 pred:$p, cc_out:$s), 4038 4, IIC_iMUL32, 4039 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))], 4040 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>, 4041 Requires<[IsARM, NoV6, UseMulOps]>, 4042 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4043} 4044 4045def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd), 4046 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra), 4047 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra", 4048 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>, 4049 Requires<[IsARM, HasV6, UseMulOps]>, 4050 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> { 4051 bits<4> Ra; 4052 let Inst{15-12} = Ra; 4053} 4054 4055let Constraints = "@earlyclobber $Rd" in 4056def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd), 4057 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 4058 pred:$p, cc_out:$s), 4, IIC_iMAC32, 4059 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))], 4060 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>, 4061 Requires<[IsARM, NoV6]>, 4062 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4063 4064def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4065 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra", 4066 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>, 4067 Requires<[IsARM, HasV6T2, UseMulOps]>, 4068 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> { 4069 bits<4> Rd; 4070 bits<4> Rm; 4071 bits<4> Rn; 4072 bits<4> Ra; 4073 let Inst{19-16} = Rd; 4074 let Inst{15-12} = Ra; 4075 let Inst{11-8} = Rm; 4076 let Inst{3-0} = Rn; 4077} 4078 4079// Extra precision multiplies with low / high results 4080let hasSideEffects = 0 in { 4081let isCommutable = 1 in { 4082def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi), 4083 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 4084 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", 4085 [(set GPR:$RdLo, GPR:$RdHi, 4086 (smullohi GPR:$Rn, GPR:$Rm))]>, 4087 Requires<[IsARM, HasV6]>, 4088 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4089 4090def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi), 4091 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 4092 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", 4093 [(set GPR:$RdLo, GPR:$RdHi, 4094 (umullohi GPR:$Rn, GPR:$Rm))]>, 4095 Requires<[IsARM, HasV6]>, 4096 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL]>; 4097 4098let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in { 4099def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4100 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 4101 4, IIC_iMUL64, 4102 [(set GPR:$RdLo, GPR:$RdHi, 4103 (smullohi GPR:$Rn, GPR:$Rm))], 4104 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 4105 Requires<[IsARM, NoV6]>, 4106 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4107 4108def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4109 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 4110 4, IIC_iMUL64, 4111 [(set GPR:$RdLo, GPR:$RdHi, 4112 (umullohi GPR:$Rn, GPR:$Rm))], 4113 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 4114 Requires<[IsARM, NoV6]>, 4115 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4116} 4117} 4118 4119// Multiply + accumulate 4120def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi), 4121 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 4122 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4123 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4124 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4125def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi), 4126 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 4127 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4128 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4129 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4130 4131def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi), 4132 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4133 IIC_iMAC64, 4134 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4135 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4136 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]> { 4137 bits<4> RdLo; 4138 bits<4> RdHi; 4139 bits<4> Rm; 4140 bits<4> Rn; 4141 let Inst{19-16} = RdHi; 4142 let Inst{15-12} = RdLo; 4143 let Inst{11-8} = Rm; 4144 let Inst{3-0} = Rn; 4145} 4146 4147let Constraints = 4148 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in { 4149def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4150 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 4151 4, IIC_iMAC64, [], 4152 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 4153 pred:$p, cc_out:$s)>, 4154 Requires<[IsARM, NoV6]>, 4155 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4156def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4157 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 4158 4, IIC_iMAC64, [], 4159 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 4160 pred:$p, cc_out:$s)>, 4161 Requires<[IsARM, NoV6]>, 4162 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4163} 4164 4165} // hasSideEffects 4166 4167// Most significant word multiply 4168def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4169 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm", 4170 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>, 4171 Requires<[IsARM, HasV6]>, 4172 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 4173 let Inst{15-12} = 0b1111; 4174} 4175 4176def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4177 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", 4178 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, (i32 0)))]>, 4179 Requires<[IsARM, HasV6]>, 4180 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 4181 let Inst{15-12} = 0b1111; 4182} 4183 4184def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd), 4185 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4186 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra", 4187 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>, 4188 Requires<[IsARM, HasV6, UseMulOps]>, 4189 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4190 4191def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd), 4192 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4193 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", 4194 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, 4195 Requires<[IsARM, HasV6]>, 4196 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4197 4198def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd), 4199 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4200 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>, 4201 Requires<[IsARM, HasV6, UseMulOps]>, 4202 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4203 4204def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd), 4205 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4206 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", 4207 [(set GPR:$Rd, (ARMsmmlsr GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, 4208 Requires<[IsARM, HasV6]>, 4209 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4210 4211multiclass AI_smul<string opc> { 4212 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4213 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm", 4214 [(set GPR:$Rd, (mul (sext_inreg GPR:$Rn, i16), 4215 (sext_inreg GPR:$Rm, i16)))]>, 4216 Requires<[IsARM, HasV5TE]>, 4217 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4218 4219 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4220 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm", 4221 [(set GPR:$Rd, (mul (sext_inreg GPR:$Rn, i16), 4222 (sra GPR:$Rm, (i32 16))))]>, 4223 Requires<[IsARM, HasV5TE]>, 4224 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4225 4226 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4227 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm", 4228 [(set GPR:$Rd, (mul (sra GPR:$Rn, (i32 16)), 4229 (sext_inreg GPR:$Rm, i16)))]>, 4230 Requires<[IsARM, HasV5TE]>, 4231 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4232 4233 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4234 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm", 4235 [(set GPR:$Rd, (mul (sra GPR:$Rn, (i32 16)), 4236 (sra GPR:$Rm, (i32 16))))]>, 4237 Requires<[IsARM, HasV5TE]>, 4238 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4239 4240 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4241 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm", 4242 [(set GPR:$Rd, (ARMsmulwb GPR:$Rn, GPR:$Rm))]>, 4243 Requires<[IsARM, HasV5TE]>, 4244 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4245 4246 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4247 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm", 4248 [(set GPR:$Rd, (ARMsmulwt GPR:$Rn, GPR:$Rm))]>, 4249 Requires<[IsARM, HasV5TE]>, 4250 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4251} 4252 4253 4254multiclass AI_smla<string opc> { 4255 let DecoderMethod = "DecodeSMLAInstruction" in { 4256 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd), 4257 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4258 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", 4259 [(set GPRnopc:$Rd, (add GPR:$Ra, 4260 (mul (sext_inreg GPRnopc:$Rn, i16), 4261 (sext_inreg GPRnopc:$Rm, i16))))]>, 4262 Requires<[IsARM, HasV5TE, UseMulOps]>, 4263 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4264 4265 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd), 4266 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4267 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", 4268 [(set GPRnopc:$Rd, 4269 (add GPR:$Ra, (mul (sext_inreg GPRnopc:$Rn, i16), 4270 (sra GPRnopc:$Rm, (i32 16)))))]>, 4271 Requires<[IsARM, HasV5TE, UseMulOps]>, 4272 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4273 4274 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd), 4275 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4276 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", 4277 [(set GPRnopc:$Rd, 4278 (add GPR:$Ra, (mul (sra GPRnopc:$Rn, (i32 16)), 4279 (sext_inreg GPRnopc:$Rm, i16))))]>, 4280 Requires<[IsARM, HasV5TE, UseMulOps]>, 4281 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4282 4283 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd), 4284 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4285 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra", 4286 [(set GPRnopc:$Rd, 4287 (add GPR:$Ra, (mul (sra GPRnopc:$Rn, (i32 16)), 4288 (sra GPRnopc:$Rm, (i32 16)))))]>, 4289 Requires<[IsARM, HasV5TE, UseMulOps]>, 4290 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4291 4292 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd), 4293 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4294 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra", 4295 [(set GPRnopc:$Rd, 4296 (add GPR:$Ra, (ARMsmulwb GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4297 Requires<[IsARM, HasV5TE, UseMulOps]>, 4298 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4299 4300 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd), 4301 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4302 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra", 4303 [(set GPRnopc:$Rd, 4304 (add GPR:$Ra, (ARMsmulwt GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4305 Requires<[IsARM, HasV5TE, UseMulOps]>, 4306 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4307 } 4308} 4309 4310defm SMUL : AI_smul<"smul">; 4311defm SMLA : AI_smla<"smla">; 4312 4313// Halfword multiply accumulate long: SMLAL<x><y>. 4314class SMLAL<bits<2> opc1, string asm> 4315 : AMulxyI64<0b0001010, opc1, 4316 (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4317 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4318 IIC_iMAC64, asm, "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4319 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4320 Requires<[IsARM, HasV5TE]>, 4321 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4322 4323def SMLALBB : SMLAL<0b00, "smlalbb">; 4324def SMLALBT : SMLAL<0b10, "smlalbt">; 4325def SMLALTB : SMLAL<0b01, "smlaltb">; 4326def SMLALTT : SMLAL<0b11, "smlaltt">; 4327 4328def : ARMV5TEPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4329 (SMLALBB $Rn, $Rm, $RLo, $RHi)>; 4330def : ARMV5TEPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4331 (SMLALBT $Rn, $Rm, $RLo, $RHi)>; 4332def : ARMV5TEPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4333 (SMLALTB $Rn, $Rm, $RLo, $RHi)>; 4334def : ARMV5TEPat<(ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4335 (SMLALTT $Rn, $Rm, $RLo, $RHi)>; 4336 4337// Helper class for AI_smld. 4338class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops, 4339 InstrItinClass itin, string opc, string asm> 4340 : AI<oops, iops, MulFrm, itin, opc, asm, []>, 4341 Requires<[IsARM, HasV6]> { 4342 bits<4> Rn; 4343 bits<4> Rm; 4344 let Inst{27-23} = 0b01110; 4345 let Inst{22} = long; 4346 let Inst{21-20} = 0b00; 4347 let Inst{11-8} = Rm; 4348 let Inst{7} = 0; 4349 let Inst{6} = sub; 4350 let Inst{5} = swap; 4351 let Inst{4} = 1; 4352 let Inst{3-0} = Rn; 4353} 4354class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops, 4355 InstrItinClass itin, string opc, string asm> 4356 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4357 bits<4> Rd; 4358 let Inst{15-12} = 0b1111; 4359 let Inst{19-16} = Rd; 4360} 4361class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops, 4362 InstrItinClass itin, string opc, string asm> 4363 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4364 bits<4> Ra; 4365 bits<4> Rd; 4366 let Inst{19-16} = Rd; 4367 let Inst{15-12} = Ra; 4368} 4369class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops, 4370 InstrItinClass itin, string opc, string asm> 4371 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4372 bits<4> RdLo; 4373 bits<4> RdHi; 4374 let Inst{19-16} = RdHi; 4375 let Inst{15-12} = RdLo; 4376} 4377 4378multiclass AI_smld<bit sub, string opc> { 4379 4380 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd), 4381 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4382 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">, 4383 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4384 4385 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd), 4386 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4387 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">, 4388 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4389 4390 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4391 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4392 NoItinerary, 4393 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">, 4394 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4395 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4396 4397 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4398 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4399 NoItinerary, 4400 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">, 4401 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4402 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4403} 4404 4405defm SMLA : AI_smld<0, "smla">; 4406defm SMLS : AI_smld<1, "smls">; 4407 4408def : ARMV6Pat<(int_arm_smlad GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4409 (SMLAD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4410def : ARMV6Pat<(int_arm_smladx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4411 (SMLADX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4412def : ARMV6Pat<(int_arm_smlsd GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4413 (SMLSD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4414def : ARMV6Pat<(int_arm_smlsdx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4415 (SMLSDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4416def : ARMV6Pat<(ARMSmlald GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4417 (SMLALD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4418def : ARMV6Pat<(ARMSmlaldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4419 (SMLALDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4420def : ARMV6Pat<(ARMSmlsld GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4421 (SMLSLD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4422def : ARMV6Pat<(ARMSmlsldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4423 (SMLSLDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4424 4425multiclass AI_sdml<bit sub, string opc> { 4426 4427 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), 4428 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">, 4429 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4430 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm), 4431 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">, 4432 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4433} 4434 4435defm SMUA : AI_sdml<0, "smua">; 4436defm SMUS : AI_sdml<1, "smus">; 4437 4438def : ARMV6Pat<(int_arm_smuad GPRnopc:$Rn, GPRnopc:$Rm), 4439 (SMUAD GPRnopc:$Rn, GPRnopc:$Rm)>; 4440def : ARMV6Pat<(int_arm_smuadx GPRnopc:$Rn, GPRnopc:$Rm), 4441 (SMUADX GPRnopc:$Rn, GPRnopc:$Rm)>; 4442def : ARMV6Pat<(int_arm_smusd GPRnopc:$Rn, GPRnopc:$Rm), 4443 (SMUSD GPRnopc:$Rn, GPRnopc:$Rm)>; 4444def : ARMV6Pat<(int_arm_smusdx GPRnopc:$Rn, GPRnopc:$Rm), 4445 (SMUSDX GPRnopc:$Rn, GPRnopc:$Rm)>; 4446 4447//===----------------------------------------------------------------------===// 4448// Division Instructions (ARMv7-A with virtualization extension) 4449// 4450def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4451 "sdiv", "\t$Rd, $Rn, $Rm", 4452 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>, 4453 Requires<[IsARM, HasDivideInARM]>, 4454 Sched<[WriteDIV]>; 4455 4456def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4457 "udiv", "\t$Rd, $Rn, $Rm", 4458 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>, 4459 Requires<[IsARM, HasDivideInARM]>, 4460 Sched<[WriteDIV]>; 4461 4462//===----------------------------------------------------------------------===// 4463// Misc. Arithmetic Instructions. 4464// 4465 4466def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm), 4467 IIC_iUNAr, "clz", "\t$Rd, $Rm", 4468 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>, 4469 Sched<[WriteALU]>; 4470 4471def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4472 IIC_iUNAr, "rbit", "\t$Rd, $Rm", 4473 [(set GPR:$Rd, (bitreverse GPR:$Rm))]>, 4474 Requires<[IsARM, HasV6T2]>, 4475 Sched<[WriteALU]>; 4476 4477def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4478 IIC_iUNAr, "rev", "\t$Rd, $Rm", 4479 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>, 4480 Sched<[WriteALU]>; 4481 4482let AddedComplexity = 5 in 4483def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4484 IIC_iUNAr, "rev16", "\t$Rd, $Rm", 4485 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>, 4486 Requires<[IsARM, HasV6]>, 4487 Sched<[WriteALU]>; 4488 4489def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)), 4490 (REV16 (LDRH addrmode3:$addr))>; 4491def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr), 4492 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>; 4493 4494let AddedComplexity = 5 in 4495def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4496 IIC_iUNAr, "revsh", "\t$Rd, $Rm", 4497 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>, 4498 Requires<[IsARM, HasV6]>, 4499 Sched<[WriteALU]>; 4500 4501def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)), 4502 (and (srl GPR:$Rm, (i32 8)), 0xFF)), 4503 (REVSH GPR:$Rm)>; 4504 4505def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd), 4506 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh), 4507 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh", 4508 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF), 4509 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh), 4510 0xFFFF0000)))]>, 4511 Requires<[IsARM, HasV6]>, 4512 Sched<[WriteALUsi, ReadALU]>; 4513 4514// Alternate cases for PKHBT where identities eliminate some nodes. 4515def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)), 4516 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>; 4517def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)), 4518 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>; 4519 4520// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and 4521// will match the pattern below. 4522def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd), 4523 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh), 4524 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh", 4525 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000), 4526 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh), 4527 0xFFFF)))]>, 4528 Requires<[IsARM, HasV6]>, 4529 Sched<[WriteALUsi, ReadALU]>; 4530 4531// Alternate cases for PKHTB where identities eliminate some nodes. Note that 4532// a shift amount of 0 is *not legal* here, it is PKHBT instead. 4533// We also can not replace a srl (17..31) by an arithmetic shift we would use in 4534// pkhtb src1, src2, asr (17..31). 4535def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4536 (srl GPRnopc:$src2, imm16:$sh)), 4537 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>; 4538def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4539 (sra GPRnopc:$src2, imm16_31:$sh)), 4540 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>; 4541def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4542 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)), 4543 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>; 4544 4545//===----------------------------------------------------------------------===// 4546// CRC Instructions 4547// 4548// Polynomials: 4549// + CRC32{B,H,W} 0x04C11DB7 4550// + CRC32C{B,H,W} 0x1EDC6F41 4551// 4552 4553class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin> 4554 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary, 4555 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm", 4556 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>, 4557 Requires<[IsARM, HasV8, HasCRC]> { 4558 bits<4> Rd; 4559 bits<4> Rn; 4560 bits<4> Rm; 4561 4562 let Inst{31-28} = 0b1110; 4563 let Inst{27-23} = 0b00010; 4564 let Inst{22-21} = sz; 4565 let Inst{20} = 0; 4566 let Inst{19-16} = Rn; 4567 let Inst{15-12} = Rd; 4568 let Inst{11-10} = 0b00; 4569 let Inst{9} = C; 4570 let Inst{8} = 0; 4571 let Inst{7-4} = 0b0100; 4572 let Inst{3-0} = Rm; 4573 4574 let Unpredictable{11-8} = 0b1101; 4575} 4576 4577def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>; 4578def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>; 4579def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>; 4580def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>; 4581def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>; 4582def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>; 4583 4584//===----------------------------------------------------------------------===// 4585// ARMv8.1a Privilege Access Never extension 4586// 4587// SETPAN #imm1 4588 4589def SETPAN : AInoP<(outs), (ins imm0_1:$imm), MiscFrm, NoItinerary, "setpan", 4590 "\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> { 4591 bits<1> imm; 4592 4593 let Inst{31-28} = 0b1111; 4594 let Inst{27-20} = 0b00010001; 4595 let Inst{19-16} = 0b0000; 4596 let Inst{15-10} = 0b000000; 4597 let Inst{9} = imm; 4598 let Inst{8} = 0b0; 4599 let Inst{7-4} = 0b0000; 4600 let Inst{3-0} = 0b0000; 4601 4602 let Unpredictable{19-16} = 0b1111; 4603 let Unpredictable{15-10} = 0b111111; 4604 let Unpredictable{8} = 0b1; 4605 let Unpredictable{3-0} = 0b1111; 4606} 4607 4608//===----------------------------------------------------------------------===// 4609// Comparison Instructions... 4610// 4611 4612defm CMP : AI1_cmp_irs<0b1010, "cmp", 4613 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, ARMcmp>; 4614 4615// ARMcmpZ can re-use the above instruction definitions. 4616def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm), 4617 (CMPri GPR:$src, mod_imm:$imm)>; 4618def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs), 4619 (CMPrr GPR:$src, GPR:$rhs)>; 4620def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs), 4621 (CMPrsi GPR:$src, so_reg_imm:$rhs)>; 4622def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs), 4623 (CMPrsr GPR:$src, so_reg_reg:$rhs)>; 4624 4625// CMN register-integer 4626let isCompare = 1, Defs = [CPSR] in { 4627def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi, 4628 "cmn", "\t$Rn, $imm", 4629 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>, 4630 Sched<[WriteCMP, ReadALU]> { 4631 bits<4> Rn; 4632 bits<12> imm; 4633 let Inst{25} = 1; 4634 let Inst{20} = 1; 4635 let Inst{19-16} = Rn; 4636 let Inst{15-12} = 0b0000; 4637 let Inst{11-0} = imm; 4638 4639 let Unpredictable{15-12} = 0b1111; 4640} 4641 4642// CMN register-register/shift 4643def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr, 4644 "cmn", "\t$Rn, $Rm", 4645 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4646 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> { 4647 bits<4> Rn; 4648 bits<4> Rm; 4649 let isCommutable = 1; 4650 let Inst{25} = 0; 4651 let Inst{20} = 1; 4652 let Inst{19-16} = Rn; 4653 let Inst{15-12} = 0b0000; 4654 let Inst{11-4} = 0b00000000; 4655 let Inst{3-0} = Rm; 4656 4657 let Unpredictable{15-12} = 0b1111; 4658} 4659 4660def CMNzrsi : AI1<0b1011, (outs), 4661 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr, 4662 "cmn", "\t$Rn, $shift", 4663 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4664 GPR:$Rn, so_reg_imm:$shift)]>, 4665 Sched<[WriteCMPsi, ReadALU]> { 4666 bits<4> Rn; 4667 bits<12> shift; 4668 let Inst{25} = 0; 4669 let Inst{20} = 1; 4670 let Inst{19-16} = Rn; 4671 let Inst{15-12} = 0b0000; 4672 let Inst{11-5} = shift{11-5}; 4673 let Inst{4} = 0; 4674 let Inst{3-0} = shift{3-0}; 4675 4676 let Unpredictable{15-12} = 0b1111; 4677} 4678 4679def CMNzrsr : AI1<0b1011, (outs), 4680 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr, 4681 "cmn", "\t$Rn, $shift", 4682 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4683 GPRnopc:$Rn, so_reg_reg:$shift)]>, 4684 Sched<[WriteCMPsr, ReadALU]> { 4685 bits<4> Rn; 4686 bits<12> shift; 4687 let Inst{25} = 0; 4688 let Inst{20} = 1; 4689 let Inst{19-16} = Rn; 4690 let Inst{15-12} = 0b0000; 4691 let Inst{11-8} = shift{11-8}; 4692 let Inst{7} = 0; 4693 let Inst{6-5} = shift{6-5}; 4694 let Inst{4} = 1; 4695 let Inst{3-0} = shift{3-0}; 4696 4697 let Unpredictable{15-12} = 0b1111; 4698} 4699 4700} 4701 4702def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm), 4703 (CMNri GPR:$src, mod_imm_neg:$imm)>; 4704 4705def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm), 4706 (CMNri GPR:$src, mod_imm_neg:$imm)>; 4707 4708// Note that TST/TEQ don't set all the same flags that CMP does! 4709defm TST : AI1_cmp_irs<0b1000, "tst", 4710 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4711 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1, 4712 "DecodeTSTInstruction">; 4713defm TEQ : AI1_cmp_irs<0b1001, "teq", 4714 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4715 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>; 4716 4717// Pseudo i64 compares for some floating point compares. 4718let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, 4719 Defs = [CPSR] in { 4720def BCCi64 : PseudoInst<(outs), 4721 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst), 4722 IIC_Br, 4723 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>, 4724 Sched<[WriteBr]>; 4725 4726def BCCZi64 : PseudoInst<(outs), 4727 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, 4728 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>, 4729 Sched<[WriteBr]>; 4730} // usesCustomInserter 4731 4732 4733// Conditional moves 4734let hasSideEffects = 0 in { 4735 4736let isCommutable = 1, isSelect = 1 in 4737def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), 4738 (ins GPR:$false, GPR:$Rm, cmovpred:$p), 4739 4, IIC_iCMOVr, 4740 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, 4741 cmovpred:$p))]>, 4742 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4743 4744def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd), 4745 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p), 4746 4, IIC_iCMOVsr, 4747 [(set GPR:$Rd, 4748 (ARMcmov GPR:$false, so_reg_imm:$shift, 4749 cmovpred:$p))]>, 4750 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4751def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd), 4752 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p), 4753 4, IIC_iCMOVsr, 4754 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift, 4755 cmovpred:$p))]>, 4756 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4757 4758 4759let isMoveImm = 1 in 4760def MOVCCi16 4761 : ARMPseudoInst<(outs GPR:$Rd), 4762 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p), 4763 4, IIC_iMOVi, 4764 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm, 4765 cmovpred:$p))]>, 4766 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>, 4767 Sched<[WriteALU]>; 4768 4769let isMoveImm = 1 in 4770def MOVCCi : ARMPseudoInst<(outs GPR:$Rd), 4771 (ins GPR:$false, mod_imm:$imm, cmovpred:$p), 4772 4, IIC_iCMOVi, 4773 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm, 4774 cmovpred:$p))]>, 4775 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4776 4777// Two instruction predicate mov immediate. 4778let isMoveImm = 1 in 4779def MOVCCi32imm 4780 : ARMPseudoInst<(outs GPR:$Rd), 4781 (ins GPR:$false, i32imm:$src, cmovpred:$p), 4782 8, IIC_iCMOVix2, 4783 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src, 4784 cmovpred:$p))]>, 4785 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>; 4786 4787let isMoveImm = 1 in 4788def MVNCCi : ARMPseudoInst<(outs GPR:$Rd), 4789 (ins GPR:$false, mod_imm:$imm, cmovpred:$p), 4790 4, IIC_iCMOVi, 4791 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm, 4792 cmovpred:$p))]>, 4793 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4794 4795} // hasSideEffects 4796 4797 4798//===----------------------------------------------------------------------===// 4799// Atomic operations intrinsics 4800// 4801 4802def MemBarrierOptOperand : AsmOperandClass { 4803 let Name = "MemBarrierOpt"; 4804 let ParserMethod = "parseMemBarrierOptOperand"; 4805} 4806def memb_opt : Operand<i32> { 4807 let PrintMethod = "printMemBOption"; 4808 let ParserMatchClass = MemBarrierOptOperand; 4809 let DecoderMethod = "DecodeMemBarrierOption"; 4810} 4811 4812def InstSyncBarrierOptOperand : AsmOperandClass { 4813 let Name = "InstSyncBarrierOpt"; 4814 let ParserMethod = "parseInstSyncBarrierOptOperand"; 4815} 4816def instsyncb_opt : Operand<i32> { 4817 let PrintMethod = "printInstSyncBOption"; 4818 let ParserMatchClass = InstSyncBarrierOptOperand; 4819 let DecoderMethod = "DecodeInstSyncBarrierOption"; 4820} 4821 4822def TraceSyncBarrierOptOperand : AsmOperandClass { 4823 let Name = "TraceSyncBarrierOpt"; 4824 let ParserMethod = "parseTraceSyncBarrierOptOperand"; 4825} 4826def tsb_opt : Operand<i32> { 4827 let PrintMethod = "printTraceSyncBOption"; 4828 let ParserMatchClass = TraceSyncBarrierOptOperand; 4829} 4830 4831// Memory barriers protect the atomic sequences 4832let hasSideEffects = 1 in { 4833def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4834 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>, 4835 Requires<[IsARM, HasDB]> { 4836 bits<4> opt; 4837 let Inst{31-4} = 0xf57ff05; 4838 let Inst{3-0} = opt; 4839} 4840 4841def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4842 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>, 4843 Requires<[IsARM, HasDB]> { 4844 bits<4> opt; 4845 let Inst{31-4} = 0xf57ff04; 4846 let Inst{3-0} = opt; 4847} 4848 4849// ISB has only full system option 4850def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary, 4851 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>, 4852 Requires<[IsARM, HasDB]> { 4853 bits<4> opt; 4854 let Inst{31-4} = 0xf57ff06; 4855 let Inst{3-0} = opt; 4856} 4857 4858let hasNoSchedulingInfo = 1 in 4859def TSB : AInoP<(outs), (ins tsb_opt:$opt), MiscFrm, NoItinerary, 4860 "tsb", "\t$opt", []>, Requires<[IsARM, HasV8_4a]> { 4861 let Inst{31-0} = 0xe320f012; 4862} 4863 4864} 4865 4866let usesCustomInserter = 1, Defs = [CPSR] in { 4867 4868// Pseudo instruction that combines movs + predicated rsbmi 4869// to implement integer ABS 4870 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>; 4871} 4872 4873let usesCustomInserter = 1 in { 4874 def COPY_STRUCT_BYVAL_I32 : PseudoInst< 4875 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment), 4876 NoItinerary, 4877 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>; 4878} 4879 4880let hasPostISelHook = 1, Constraints = "$newdst = $dst, $newsrc = $src" in { 4881 // %newsrc, %newdst = MEMCPY %dst, %src, N, ...N scratch regs... 4882 // Copies N registers worth of memory from address %src to address %dst 4883 // and returns the incremented addresses. N scratch register will 4884 // be attached for the copy to use. 4885 def MEMCPY : PseudoInst< 4886 (outs GPR:$newdst, GPR:$newsrc), 4887 (ins GPR:$dst, GPR:$src, i32imm:$nreg, variable_ops), 4888 NoItinerary, 4889 [(set GPR:$newdst, GPR:$newsrc, 4890 (ARMmemcopy GPR:$dst, GPR:$src, imm:$nreg))]>; 4891} 4892 4893def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4894 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4895}]>; 4896 4897def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4898 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4899}]>; 4900 4901def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4902 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4903}]>; 4904 4905def strex_1 : PatFrag<(ops node:$val, node:$ptr), 4906 (int_arm_strex node:$val, node:$ptr), [{ 4907 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4908}]>; 4909 4910def strex_2 : PatFrag<(ops node:$val, node:$ptr), 4911 (int_arm_strex node:$val, node:$ptr), [{ 4912 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4913}]>; 4914 4915def strex_4 : PatFrag<(ops node:$val, node:$ptr), 4916 (int_arm_strex node:$val, node:$ptr), [{ 4917 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4918}]>; 4919 4920def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4921 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4922}]>; 4923 4924def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4925 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4926}]>; 4927 4928def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4929 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4930}]>; 4931 4932def stlex_1 : PatFrag<(ops node:$val, node:$ptr), 4933 (int_arm_stlex node:$val, node:$ptr), [{ 4934 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4935}]>; 4936 4937def stlex_2 : PatFrag<(ops node:$val, node:$ptr), 4938 (int_arm_stlex node:$val, node:$ptr), [{ 4939 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4940}]>; 4941 4942def stlex_4 : PatFrag<(ops node:$val, node:$ptr), 4943 (int_arm_stlex node:$val, node:$ptr), [{ 4944 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4945}]>; 4946 4947let mayLoad = 1 in { 4948def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4949 NoItinerary, "ldrexb", "\t$Rt, $addr", 4950 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>; 4951def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4952 NoItinerary, "ldrexh", "\t$Rt, $addr", 4953 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>; 4954def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4955 NoItinerary, "ldrex", "\t$Rt, $addr", 4956 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>; 4957let hasExtraDefRegAllocReq = 1 in 4958def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 4959 NoItinerary, "ldrexd", "\t$Rt, $addr", []> { 4960 let DecoderMethod = "DecodeDoubleRegLoad"; 4961} 4962 4963def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4964 NoItinerary, "ldaexb", "\t$Rt, $addr", 4965 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>; 4966def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4967 NoItinerary, "ldaexh", "\t$Rt, $addr", 4968 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>; 4969def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4970 NoItinerary, "ldaex", "\t$Rt, $addr", 4971 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>; 4972let hasExtraDefRegAllocReq = 1 in 4973def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 4974 NoItinerary, "ldaexd", "\t$Rt, $addr", []> { 4975 let DecoderMethod = "DecodeDoubleRegLoad"; 4976} 4977} 4978 4979let mayStore = 1, Constraints = "@earlyclobber $Rd" in { 4980def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4981 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", 4982 [(set GPR:$Rd, (strex_1 GPR:$Rt, 4983 addr_offset_none:$addr))]>; 4984def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4985 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", 4986 [(set GPR:$Rd, (strex_2 GPR:$Rt, 4987 addr_offset_none:$addr))]>; 4988def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4989 NoItinerary, "strex", "\t$Rd, $Rt, $addr", 4990 [(set GPR:$Rd, (strex_4 GPR:$Rt, 4991 addr_offset_none:$addr))]>; 4992let hasExtraSrcRegAllocReq = 1 in 4993def STREXD : AIstrex<0b01, (outs GPR:$Rd), 4994 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 4995 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> { 4996 let DecoderMethod = "DecodeDoubleRegStore"; 4997} 4998def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4999 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr", 5000 [(set GPR:$Rd, 5001 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>; 5002def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5003 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr", 5004 [(set GPR:$Rd, 5005 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>; 5006def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5007 NoItinerary, "stlex", "\t$Rd, $Rt, $addr", 5008 [(set GPR:$Rd, 5009 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>; 5010let hasExtraSrcRegAllocReq = 1 in 5011def STLEXD : AIstlex<0b01, (outs GPR:$Rd), 5012 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 5013 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> { 5014 let DecoderMethod = "DecodeDoubleRegStore"; 5015} 5016} 5017 5018def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", 5019 [(int_arm_clrex)]>, 5020 Requires<[IsARM, HasV6K]> { 5021 let Inst{31-0} = 0b11110101011111111111000000011111; 5022} 5023 5024def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 5025 (STREXB GPR:$Rt, addr_offset_none:$addr)>; 5026def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 5027 (STREXH GPR:$Rt, addr_offset_none:$addr)>; 5028 5029def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 5030 (STLEXB GPR:$Rt, addr_offset_none:$addr)>; 5031def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 5032 (STLEXH GPR:$Rt, addr_offset_none:$addr)>; 5033 5034class acquiring_load<PatFrag base> 5035 : PatFrag<(ops node:$ptr), (base node:$ptr), [{ 5036 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 5037 return isAcquireOrStronger(Ordering); 5038}]>; 5039 5040def atomic_load_acquire_8 : acquiring_load<atomic_load_8>; 5041def atomic_load_acquire_16 : acquiring_load<atomic_load_16>; 5042def atomic_load_acquire_32 : acquiring_load<atomic_load_32>; 5043 5044class releasing_store<PatFrag base> 5045 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{ 5046 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 5047 return isReleaseOrStronger(Ordering); 5048}]>; 5049 5050def atomic_store_release_8 : releasing_store<atomic_store_8>; 5051def atomic_store_release_16 : releasing_store<atomic_store_16>; 5052def atomic_store_release_32 : releasing_store<atomic_store_32>; 5053 5054let AddedComplexity = 8 in { 5055 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>; 5056 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>; 5057 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>; 5058 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>; 5059 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>; 5060 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>; 5061} 5062 5063// SWP/SWPB are deprecated in V6/V7 and optional in v7VE. 5064// FIXME Use InstAlias to generate LDREX/STREX pairs instead. 5065let mayLoad = 1, mayStore = 1 in { 5066def SWP : AIswp<0, (outs GPRnopc:$Rt), 5067 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>, 5068 Requires<[IsARM,PreV8]>; 5069def SWPB: AIswp<1, (outs GPRnopc:$Rt), 5070 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>, 5071 Requires<[IsARM,PreV8]>; 5072} 5073 5074//===----------------------------------------------------------------------===// 5075// Coprocessor Instructions. 5076// 5077 5078def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5079 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 5080 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 5081 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 5082 imm:$CRm, imm:$opc2)]>, 5083 Requires<[IsARM,PreV8]> { 5084 bits<4> opc1; 5085 bits<4> CRn; 5086 bits<4> CRd; 5087 bits<4> cop; 5088 bits<3> opc2; 5089 bits<4> CRm; 5090 5091 let Inst{3-0} = CRm; 5092 let Inst{4} = 0; 5093 let Inst{7-5} = opc2; 5094 let Inst{11-8} = cop; 5095 let Inst{15-12} = CRd; 5096 let Inst{19-16} = CRn; 5097 let Inst{23-20} = opc1; 5098 5099 let DecoderNamespace = "CoProc"; 5100} 5101 5102def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5103 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 5104 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 5105 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 5106 imm:$CRm, imm:$opc2)]>, 5107 Requires<[IsARM,PreV8]> { 5108 let Inst{31-28} = 0b1111; 5109 bits<4> opc1; 5110 bits<4> CRn; 5111 bits<4> CRd; 5112 bits<4> cop; 5113 bits<3> opc2; 5114 bits<4> CRm; 5115 5116 let Inst{3-0} = CRm; 5117 let Inst{4} = 0; 5118 let Inst{7-5} = opc2; 5119 let Inst{11-8} = cop; 5120 let Inst{15-12} = CRd; 5121 let Inst{19-16} = CRn; 5122 let Inst{23-20} = opc1; 5123 5124 let DecoderNamespace = "CoProc"; 5125} 5126 5127class ACI<dag oops, dag iops, string opc, string asm, 5128 list<dag> pattern, IndexMode im = IndexModeNone> 5129 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 5130 opc, asm, "", pattern> { 5131 let Inst{27-25} = 0b110; 5132} 5133class ACInoP<dag oops, dag iops, string opc, string asm, 5134 list<dag> pattern, IndexMode im = IndexModeNone> 5135 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 5136 opc, asm, "", pattern> { 5137 let Inst{31-28} = 0b1111; 5138 let Inst{27-25} = 0b110; 5139} 5140 5141let DecoderNamespace = "CoProc" in { 5142multiclass LdStCop<bit load, bit Dbit, string asm, list<dag> pattern> { 5143 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 5144 asm, "\t$cop, $CRd, $addr", pattern> { 5145 bits<13> addr; 5146 bits<4> cop; 5147 bits<4> CRd; 5148 let Inst{24} = 1; // P = 1 5149 let Inst{23} = addr{8}; 5150 let Inst{22} = Dbit; 5151 let Inst{21} = 0; // W = 0 5152 let Inst{20} = load; 5153 let Inst{19-16} = addr{12-9}; 5154 let Inst{15-12} = CRd; 5155 let Inst{11-8} = cop; 5156 let Inst{7-0} = addr{7-0}; 5157 let DecoderMethod = "DecodeCopMemInstruction"; 5158 } 5159 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 5160 asm, "\t$cop, $CRd, $addr!", [], IndexModePre> { 5161 bits<13> addr; 5162 bits<4> cop; 5163 bits<4> CRd; 5164 let Inst{24} = 1; // P = 1 5165 let Inst{23} = addr{8}; 5166 let Inst{22} = Dbit; 5167 let Inst{21} = 1; // W = 1 5168 let Inst{20} = load; 5169 let Inst{19-16} = addr{12-9}; 5170 let Inst{15-12} = CRd; 5171 let Inst{11-8} = cop; 5172 let Inst{7-0} = addr{7-0}; 5173 let DecoderMethod = "DecodeCopMemInstruction"; 5174 } 5175 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5176 postidx_imm8s4:$offset), 5177 asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> { 5178 bits<9> offset; 5179 bits<4> addr; 5180 bits<4> cop; 5181 bits<4> CRd; 5182 let Inst{24} = 0; // P = 0 5183 let Inst{23} = offset{8}; 5184 let Inst{22} = Dbit; 5185 let Inst{21} = 1; // W = 1 5186 let Inst{20} = load; 5187 let Inst{19-16} = addr; 5188 let Inst{15-12} = CRd; 5189 let Inst{11-8} = cop; 5190 let Inst{7-0} = offset{7-0}; 5191 let DecoderMethod = "DecodeCopMemInstruction"; 5192 } 5193 def _OPTION : ACI<(outs), 5194 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5195 coproc_option_imm:$option), 5196 asm, "\t$cop, $CRd, $addr, $option", []> { 5197 bits<8> option; 5198 bits<4> addr; 5199 bits<4> cop; 5200 bits<4> CRd; 5201 let Inst{24} = 0; // P = 0 5202 let Inst{23} = 1; // U = 1 5203 let Inst{22} = Dbit; 5204 let Inst{21} = 0; // W = 0 5205 let Inst{20} = load; 5206 let Inst{19-16} = addr; 5207 let Inst{15-12} = CRd; 5208 let Inst{11-8} = cop; 5209 let Inst{7-0} = option; 5210 let DecoderMethod = "DecodeCopMemInstruction"; 5211 } 5212} 5213multiclass LdSt2Cop<bit load, bit Dbit, string asm, list<dag> pattern> { 5214 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 5215 asm, "\t$cop, $CRd, $addr", pattern> { 5216 bits<13> addr; 5217 bits<4> cop; 5218 bits<4> CRd; 5219 let Inst{24} = 1; // P = 1 5220 let Inst{23} = addr{8}; 5221 let Inst{22} = Dbit; 5222 let Inst{21} = 0; // W = 0 5223 let Inst{20} = load; 5224 let Inst{19-16} = addr{12-9}; 5225 let Inst{15-12} = CRd; 5226 let Inst{11-8} = cop; 5227 let Inst{7-0} = addr{7-0}; 5228 let DecoderMethod = "DecodeCopMemInstruction"; 5229 } 5230 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 5231 asm, "\t$cop, $CRd, $addr!", [], IndexModePre> { 5232 bits<13> addr; 5233 bits<4> cop; 5234 bits<4> CRd; 5235 let Inst{24} = 1; // P = 1 5236 let Inst{23} = addr{8}; 5237 let Inst{22} = Dbit; 5238 let Inst{21} = 1; // W = 1 5239 let Inst{20} = load; 5240 let Inst{19-16} = addr{12-9}; 5241 let Inst{15-12} = CRd; 5242 let Inst{11-8} = cop; 5243 let Inst{7-0} = addr{7-0}; 5244 let DecoderMethod = "DecodeCopMemInstruction"; 5245 } 5246 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5247 postidx_imm8s4:$offset), 5248 asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> { 5249 bits<9> offset; 5250 bits<4> addr; 5251 bits<4> cop; 5252 bits<4> CRd; 5253 let Inst{24} = 0; // P = 0 5254 let Inst{23} = offset{8}; 5255 let Inst{22} = Dbit; 5256 let Inst{21} = 1; // W = 1 5257 let Inst{20} = load; 5258 let Inst{19-16} = addr; 5259 let Inst{15-12} = CRd; 5260 let Inst{11-8} = cop; 5261 let Inst{7-0} = offset{7-0}; 5262 let DecoderMethod = "DecodeCopMemInstruction"; 5263 } 5264 def _OPTION : ACInoP<(outs), 5265 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5266 coproc_option_imm:$option), 5267 asm, "\t$cop, $CRd, $addr, $option", []> { 5268 bits<8> option; 5269 bits<4> addr; 5270 bits<4> cop; 5271 bits<4> CRd; 5272 let Inst{24} = 0; // P = 0 5273 let Inst{23} = 1; // U = 1 5274 let Inst{22} = Dbit; 5275 let Inst{21} = 0; // W = 0 5276 let Inst{20} = load; 5277 let Inst{19-16} = addr; 5278 let Inst{15-12} = CRd; 5279 let Inst{11-8} = cop; 5280 let Inst{7-0} = option; 5281 let DecoderMethod = "DecodeCopMemInstruction"; 5282 } 5283} 5284 5285defm LDC : LdStCop <1, 0, "ldc", [(int_arm_ldc imm:$cop, imm:$CRd, addrmode5:$addr)]>; 5286defm LDCL : LdStCop <1, 1, "ldcl", [(int_arm_ldcl imm:$cop, imm:$CRd, addrmode5:$addr)]>; 5287defm LDC2 : LdSt2Cop<1, 0, "ldc2", [(int_arm_ldc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5288defm LDC2L : LdSt2Cop<1, 1, "ldc2l", [(int_arm_ldc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5289 5290defm STC : LdStCop <0, 0, "stc", [(int_arm_stc imm:$cop, imm:$CRd, addrmode5:$addr)]>; 5291defm STCL : LdStCop <0, 1, "stcl", [(int_arm_stcl imm:$cop, imm:$CRd, addrmode5:$addr)]>; 5292defm STC2 : LdSt2Cop<0, 0, "stc2", [(int_arm_stc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5293defm STC2L : LdSt2Cop<0, 1, "stc2l", [(int_arm_stc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5294 5295} // DecoderNamespace = "CoProc" 5296 5297//===----------------------------------------------------------------------===// 5298// Move between coprocessor and ARM core register. 5299// 5300 5301class MovRCopro<string opc, bit direction, dag oops, dag iops, 5302 list<dag> pattern> 5303 : ABI<0b1110, oops, iops, NoItinerary, opc, 5304 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> { 5305 let Inst{20} = direction; 5306 let Inst{4} = 1; 5307 5308 bits<4> Rt; 5309 bits<4> cop; 5310 bits<3> opc1; 5311 bits<3> opc2; 5312 bits<4> CRm; 5313 bits<4> CRn; 5314 5315 let Inst{15-12} = Rt; 5316 let Inst{11-8} = cop; 5317 let Inst{23-21} = opc1; 5318 let Inst{7-5} = opc2; 5319 let Inst{3-0} = CRm; 5320 let Inst{19-16} = CRn; 5321 5322 let DecoderNamespace = "CoProc"; 5323} 5324 5325def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */, 5326 (outs), 5327 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5328 c_imm:$CRm, imm0_7:$opc2), 5329 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 5330 imm:$CRm, imm:$opc2)]>, 5331 ComplexDeprecationPredicate<"MCR">; 5332def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm", 5333 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5334 c_imm:$CRm, 0, pred:$p)>; 5335def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */, 5336 (outs GPRwithAPSR:$Rt), 5337 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 5338 imm0_7:$opc2), []>; 5339def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm", 5340 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 5341 c_imm:$CRm, 0, pred:$p)>; 5342 5343def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), 5344 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 5345 5346class MovRCopro2<string opc, bit direction, dag oops, dag iops, 5347 list<dag> pattern> 5348 : ABXI<0b1110, oops, iops, NoItinerary, 5349 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> { 5350 let Inst{31-24} = 0b11111110; 5351 let Inst{20} = direction; 5352 let Inst{4} = 1; 5353 5354 bits<4> Rt; 5355 bits<4> cop; 5356 bits<3> opc1; 5357 bits<3> opc2; 5358 bits<4> CRm; 5359 bits<4> CRn; 5360 5361 let Inst{15-12} = Rt; 5362 let Inst{11-8} = cop; 5363 let Inst{23-21} = opc1; 5364 let Inst{7-5} = opc2; 5365 let Inst{3-0} = CRm; 5366 let Inst{19-16} = CRn; 5367 5368 let DecoderNamespace = "CoProc"; 5369} 5370 5371def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */, 5372 (outs), 5373 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5374 c_imm:$CRm, imm0_7:$opc2), 5375 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 5376 imm:$CRm, imm:$opc2)]>, 5377 Requires<[IsARM,PreV8]>; 5378def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm", 5379 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5380 c_imm:$CRm, 0)>; 5381def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */, 5382 (outs GPRwithAPSR:$Rt), 5383 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 5384 imm0_7:$opc2), []>, 5385 Requires<[IsARM,PreV8]>; 5386def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm", 5387 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 5388 c_imm:$CRm, 0)>; 5389 5390def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, 5391 imm:$CRm, imm:$opc2), 5392 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 5393 5394class MovRRCopro<string opc, bit direction, dag oops, dag iops, list<dag> 5395 pattern = []> 5396 : ABI<0b1100, oops, iops, NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", 5397 pattern> { 5398 5399 let Inst{23-21} = 0b010; 5400 let Inst{20} = direction; 5401 5402 bits<4> Rt; 5403 bits<4> Rt2; 5404 bits<4> cop; 5405 bits<4> opc1; 5406 bits<4> CRm; 5407 5408 let Inst{15-12} = Rt; 5409 let Inst{19-16} = Rt2; 5410 let Inst{11-8} = cop; 5411 let Inst{7-4} = opc1; 5412 let Inst{3-0} = CRm; 5413} 5414 5415def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */, 5416 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt, 5417 GPRnopc:$Rt2, c_imm:$CRm), 5418 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt, 5419 GPRnopc:$Rt2, imm:$CRm)]>; 5420def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */, 5421 (outs GPRnopc:$Rt, GPRnopc:$Rt2), 5422 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>; 5423 5424class MovRRCopro2<string opc, bit direction, dag oops, dag iops, 5425 list<dag> pattern = []> 5426 : ABXI<0b1100, oops, iops, NoItinerary, 5427 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>, 5428 Requires<[IsARM,PreV8]> { 5429 let Inst{31-28} = 0b1111; 5430 let Inst{23-21} = 0b010; 5431 let Inst{20} = direction; 5432 5433 bits<4> Rt; 5434 bits<4> Rt2; 5435 bits<4> cop; 5436 bits<4> opc1; 5437 bits<4> CRm; 5438 5439 let Inst{15-12} = Rt; 5440 let Inst{19-16} = Rt2; 5441 let Inst{11-8} = cop; 5442 let Inst{7-4} = opc1; 5443 let Inst{3-0} = CRm; 5444 5445 let DecoderMethod = "DecoderForMRRC2AndMCRR2"; 5446} 5447 5448def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */, 5449 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt, 5450 GPRnopc:$Rt2, c_imm:$CRm), 5451 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt, 5452 GPRnopc:$Rt2, imm:$CRm)]>; 5453 5454def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */, 5455 (outs GPRnopc:$Rt, GPRnopc:$Rt2), 5456 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>; 5457 5458//===----------------------------------------------------------------------===// 5459// Move between special register and ARM core register 5460// 5461 5462// Move to ARM core register from Special Register 5463def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5464 "mrs", "\t$Rd, apsr", []> { 5465 bits<4> Rd; 5466 let Inst{23-16} = 0b00001111; 5467 let Unpredictable{19-17} = 0b111; 5468 5469 let Inst{15-12} = Rd; 5470 5471 let Inst{11-0} = 0b000000000000; 5472 let Unpredictable{11-0} = 0b110100001111; 5473} 5474 5475def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p), 0>, 5476 Requires<[IsARM]>; 5477 5478// The MRSsys instruction is the MRS instruction from the ARM ARM, 5479// section B9.3.9, with the R bit set to 1. 5480def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5481 "mrs", "\t$Rd, spsr", []> { 5482 bits<4> Rd; 5483 let Inst{23-16} = 0b01001111; 5484 let Unpredictable{19-16} = 0b1111; 5485 5486 let Inst{15-12} = Rd; 5487 5488 let Inst{11-0} = 0b000000000000; 5489 let Unpredictable{11-0} = 0b110100001111; 5490} 5491 5492// However, the MRS (banked register) system instruction (ARMv7VE) *does* have a 5493// separate encoding (distinguished by bit 5. 5494def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked), 5495 NoItinerary, "mrs", "\t$Rd, $banked", []>, 5496 Requires<[IsARM, HasVirtualization]> { 5497 bits<6> banked; 5498 bits<4> Rd; 5499 5500 let Inst{23} = 0; 5501 let Inst{22} = banked{5}; // R bit 5502 let Inst{21-20} = 0b00; 5503 let Inst{19-16} = banked{3-0}; 5504 let Inst{15-12} = Rd; 5505 let Inst{11-9} = 0b001; 5506 let Inst{8} = banked{4}; 5507 let Inst{7-0} = 0b00000000; 5508} 5509 5510// Move from ARM core register to Special Register 5511// 5512// No need to have both system and application versions of MSR (immediate) or 5513// MSR (register), the encodings are the same and the assembly parser has no way 5514// to distinguish between them. The mask operand contains the special register 5515// (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be 5516// accessed in the special register. 5517let Defs = [CPSR] in 5518def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary, 5519 "msr", "\t$mask, $Rn", []> { 5520 bits<5> mask; 5521 bits<4> Rn; 5522 5523 let Inst{23} = 0; 5524 let Inst{22} = mask{4}; // R bit 5525 let Inst{21-20} = 0b10; 5526 let Inst{19-16} = mask{3-0}; 5527 let Inst{15-12} = 0b1111; 5528 let Inst{11-4} = 0b00000000; 5529 let Inst{3-0} = Rn; 5530} 5531 5532let Defs = [CPSR] in 5533def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary, 5534 "msr", "\t$mask, $imm", []> { 5535 bits<5> mask; 5536 bits<12> imm; 5537 5538 let Inst{23} = 0; 5539 let Inst{22} = mask{4}; // R bit 5540 let Inst{21-20} = 0b10; 5541 let Inst{19-16} = mask{3-0}; 5542 let Inst{15-12} = 0b1111; 5543 let Inst{11-0} = imm; 5544} 5545 5546// However, the MSR (banked register) system instruction (ARMv7VE) *does* have a 5547// separate encoding (distinguished by bit 5. 5548def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn), 5549 NoItinerary, "msr", "\t$banked, $Rn", []>, 5550 Requires<[IsARM, HasVirtualization]> { 5551 bits<6> banked; 5552 bits<4> Rn; 5553 5554 let Inst{23} = 0; 5555 let Inst{22} = banked{5}; // R bit 5556 let Inst{21-20} = 0b10; 5557 let Inst{19-16} = banked{3-0}; 5558 let Inst{15-12} = 0b1111; 5559 let Inst{11-9} = 0b001; 5560 let Inst{8} = banked{4}; 5561 let Inst{7-4} = 0b0000; 5562 let Inst{3-0} = Rn; 5563} 5564 5565// Dynamic stack allocation yields a _chkstk for Windows targets. These calls 5566// are needed to probe the stack when allocating more than 5567// 4k bytes in one go. Touching the stack at 4K increments is necessary to 5568// ensure that the guard pages used by the OS virtual memory manager are 5569// allocated in correct sequence. 5570// The main point of having separate instruction are extra unmodelled effects 5571// (compared to ordinary calls) like stack pointer change. 5572 5573def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone, 5574 [SDNPHasChain, SDNPSideEffect]>; 5575let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in 5576 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>; 5577 5578def win__dbzchk : SDNode<"ARMISD::WIN__DBZCHK", SDT_WIN__DBZCHK, 5579 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 5580let usesCustomInserter = 1, Defs = [CPSR] in 5581 def WIN__DBZCHK : PseudoInst<(outs), (ins tGPR:$divisor), NoItinerary, 5582 [(win__dbzchk tGPR:$divisor)]>; 5583 5584//===----------------------------------------------------------------------===// 5585// TLS Instructions 5586// 5587 5588// __aeabi_read_tp preserves the registers r1-r3. 5589// This is a pseudo inst so that we can get the encoding right, 5590// complete with fixup for the aeabi_read_tp function. 5591// TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern 5592// is defined in "ARMInstrThumb.td". 5593let isCall = 1, 5594 Defs = [R0, R12, LR, CPSR], Uses = [SP] in { 5595 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br, 5596 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>, 5597 Requires<[IsARM, IsReadTPSoft]>; 5598} 5599 5600// Reading thread pointer from coprocessor register 5601def : ARMPat<(ARMthread_pointer), (MRC 15, 0, 13, 0, 3)>, 5602 Requires<[IsARM, IsReadTPHard]>; 5603 5604//===----------------------------------------------------------------------===// 5605// SJLJ Exception handling intrinsics 5606// eh_sjlj_setjmp() is an instruction sequence to store the return 5607// address and save #0 in R0 for the non-longjmp case. 5608// Since by its nature we may be coming from some other function to get 5609// here, and we're using the stack frame for the containing function to 5610// save/restore registers, we can't keep anything live in regs across 5611// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 5612// when we get here from a longjmp(). We force everything out of registers 5613// except for our own input by listing the relevant registers in Defs. By 5614// doing so, we also cause the prologue/epilogue code to actively preserve 5615// all of the callee-saved resgisters, which is exactly what we want. 5616// A constant value is passed in $val, and we use the location as a scratch. 5617// 5618// These are pseudo-instructions and are lowered to individual MC-insts, so 5619// no encoding information is necessary. 5620let Defs = 5621 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, 5622 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ], 5623 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5624 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5625 NoItinerary, 5626 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5627 Requires<[IsARM, HasVFP2]>; 5628} 5629 5630let Defs = 5631 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], 5632 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5633 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5634 NoItinerary, 5635 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5636 Requires<[IsARM, NoVFP]>; 5637} 5638 5639// FIXME: Non-IOS version(s) 5640let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, 5641 Defs = [ R7, LR, SP ] in { 5642def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch), 5643 NoItinerary, 5644 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 5645 Requires<[IsARM]>; 5646} 5647 5648let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1 in 5649def Int_eh_sjlj_setup_dispatch : PseudoInst<(outs), (ins), NoItinerary, 5650 [(ARMeh_sjlj_setup_dispatch)]>; 5651 5652// eh.sjlj.dispatchsetup pseudo-instruction. 5653// This pseudo is used for both ARM and Thumb. Any differences are handled when 5654// the pseudo is expanded (which happens before any passes that need the 5655// instruction size). 5656let isBarrier = 1 in 5657def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>; 5658 5659 5660//===----------------------------------------------------------------------===// 5661// Non-Instruction Patterns 5662// 5663 5664// ARMv4 indirect branch using (MOVr PC, dst) 5665let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in 5666 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst), 5667 4, IIC_Br, [(brind GPR:$dst)], 5668 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, 5669 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 5670 5671let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in 5672 def TAILJMPr4 : ARMPseudoExpand<(outs), (ins GPR:$dst), 5673 4, IIC_Br, [], 5674 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, 5675 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 5676 5677// Large immediate handling. 5678 5679// 32-bit immediate using two piece mod_imms or movw + movt. 5680// This is a single pseudo instruction, the benefit is that it can be remat'd 5681// as a single unit instead of having to handle reg inputs. 5682// FIXME: Remove this when we can do generalized remat. 5683let isReMaterializable = 1, isMoveImm = 1 in 5684def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, 5685 [(set GPR:$dst, (arm_i32imm:$src))]>, 5686 Requires<[IsARM]>; 5687 5688def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i, 5689 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>, 5690 Requires<[IsARM, DontUseMovt]>; 5691 5692// Pseudo instruction that combines movw + movt + add pc (if PIC). 5693// It also makes it possible to rematerialize the instructions. 5694// FIXME: Remove this when we can do generalized remat and when machine licm 5695// can properly the instructions. 5696let isReMaterializable = 1 in { 5697def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5698 IIC_iMOVix2addpc, 5699 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>, 5700 Requires<[IsARM, UseMovtInPic]>; 5701 5702def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5703 IIC_iLoadiALU, 5704 [(set GPR:$dst, 5705 (ARMWrapperPIC tglobaladdr:$addr))]>, 5706 Requires<[IsARM, DontUseMovtInPic]>; 5707 5708let AddedComplexity = 10 in 5709def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5710 NoItinerary, 5711 [(set GPR:$dst, 5712 (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5713 Requires<[IsARM, DontUseMovtInPic]>; 5714 5715let AddedComplexity = 10 in 5716def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5717 IIC_iMOVix2ld, 5718 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5719 Requires<[IsARM, UseMovtInPic]>; 5720} // isReMaterializable 5721 5722// The many different faces of TLS access. 5723def : ARMPat<(ARMWrapper tglobaltlsaddr :$dst), 5724 (MOVi32imm tglobaltlsaddr :$dst)>, 5725 Requires<[IsARM, UseMovt]>; 5726 5727def : Pat<(ARMWrapper tglobaltlsaddr:$src), 5728 (LDRLIT_ga_abs tglobaltlsaddr:$src)>, 5729 Requires<[IsARM, DontUseMovt]>; 5730 5731def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 5732 (MOV_ga_pcrel tglobaltlsaddr:$addr)>, Requires<[IsARM, UseMovtInPic]>; 5733 5734def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 5735 (LDRLIT_ga_pcrel tglobaltlsaddr:$addr)>, 5736 Requires<[IsARM, DontUseMovtInPic]>; 5737let AddedComplexity = 10 in 5738def : Pat<(load (ARMWrapperPIC tglobaltlsaddr:$addr)), 5739 (MOV_ga_pcrel_ldr tglobaltlsaddr:$addr)>, 5740 Requires<[IsARM, UseMovtInPic]>; 5741 5742 5743// ConstantPool, GlobalAddress, and JumpTable 5744def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>; 5745def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>, 5746 Requires<[IsARM, UseMovt]>; 5747def : ARMPat<(ARMWrapper texternalsym :$dst), (MOVi32imm texternalsym :$dst)>, 5748 Requires<[IsARM, UseMovt]>; 5749def : ARMPat<(ARMWrapperJT tjumptable:$dst), 5750 (LEApcrelJT tjumptable:$dst)>; 5751 5752// TODO: add,sub,and, 3-instr forms? 5753 5754// Tail calls. These patterns also apply to Thumb mode. 5755def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>; 5756def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>; 5757def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>; 5758 5759// Direct calls 5760def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>; 5761def : ARMPat<(ARMcall_nolink texternalsym:$func), 5762 (BMOVPCB_CALL texternalsym:$func)>; 5763 5764// zextload i1 -> zextload i8 5765def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5766def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5767 5768// extload -> zextload 5769def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5770def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5771def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5772def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5773 5774def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; 5775 5776def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>; 5777def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>; 5778 5779// smul* and smla* 5780def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b), 5781 (SMULBB GPR:$a, GPR:$b)>, 5782 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 5783def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))), 5784 (SMULBT GPR:$a, GPR:$b)>, 5785 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 5786def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b), 5787 (SMULTB GPR:$a, GPR:$b)>, 5788 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 5789def : ARMV5MOPat<(add GPR:$acc, 5790 (mul sext_16_node:$a, sext_16_node:$b)), 5791 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>, 5792 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 5793def : ARMV5MOPat<(add GPR:$acc, 5794 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))), 5795 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>, 5796 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 5797def : ARMV5MOPat<(add GPR:$acc, 5798 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)), 5799 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>, 5800 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 5801 5802def : ARMV5TEPat<(int_arm_smulbb GPR:$a, GPR:$b), 5803 (SMULBB GPR:$a, GPR:$b)>; 5804def : ARMV5TEPat<(int_arm_smulbt GPR:$a, GPR:$b), 5805 (SMULBT GPR:$a, GPR:$b)>; 5806def : ARMV5TEPat<(int_arm_smultb GPR:$a, GPR:$b), 5807 (SMULTB GPR:$a, GPR:$b)>; 5808def : ARMV5TEPat<(int_arm_smultt GPR:$a, GPR:$b), 5809 (SMULTT GPR:$a, GPR:$b)>; 5810def : ARMV5TEPat<(int_arm_smulwb GPR:$a, GPR:$b), 5811 (SMULWB GPR:$a, GPR:$b)>; 5812def : ARMV5TEPat<(int_arm_smulwt GPR:$a, GPR:$b), 5813 (SMULWT GPR:$a, GPR:$b)>; 5814 5815def : ARMV5TEPat<(int_arm_smlabb GPR:$a, GPR:$b, GPR:$acc), 5816 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 5817def : ARMV5TEPat<(int_arm_smlabt GPR:$a, GPR:$b, GPR:$acc), 5818 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 5819def : ARMV5TEPat<(int_arm_smlatb GPR:$a, GPR:$b, GPR:$acc), 5820 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 5821def : ARMV5TEPat<(int_arm_smlatt GPR:$a, GPR:$b, GPR:$acc), 5822 (SMLATT GPR:$a, GPR:$b, GPR:$acc)>; 5823def : ARMV5TEPat<(int_arm_smlawb GPR:$a, GPR:$b, GPR:$acc), 5824 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 5825def : ARMV5TEPat<(int_arm_smlawt GPR:$a, GPR:$b, GPR:$acc), 5826 (SMLAWT GPR:$a, GPR:$b, GPR:$acc)>; 5827 5828// Pre-v7 uses MCR for synchronization barriers. 5829def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>, 5830 Requires<[IsARM, HasV6]>; 5831 5832// SXT/UXT with no rotate 5833let AddedComplexity = 16 in { 5834def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>; 5835def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>; 5836def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>; 5837def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)), 5838 (UXTAB GPR:$Rn, GPR:$Rm, 0)>; 5839def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)), 5840 (UXTAH GPR:$Rn, GPR:$Rm, 0)>; 5841} 5842 5843def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>; 5844def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>; 5845 5846def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)), 5847 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>; 5848def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)), 5849 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>; 5850 5851// Atomic load/store patterns 5852def : ARMPat<(atomic_load_8 ldst_so_reg:$src), 5853 (LDRBrs ldst_so_reg:$src)>; 5854def : ARMPat<(atomic_load_8 addrmode_imm12:$src), 5855 (LDRBi12 addrmode_imm12:$src)>; 5856def : ARMPat<(atomic_load_16 addrmode3:$src), 5857 (LDRH addrmode3:$src)>; 5858def : ARMPat<(atomic_load_32 ldst_so_reg:$src), 5859 (LDRrs ldst_so_reg:$src)>; 5860def : ARMPat<(atomic_load_32 addrmode_imm12:$src), 5861 (LDRi12 addrmode_imm12:$src)>; 5862def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val), 5863 (STRBrs GPR:$val, ldst_so_reg:$ptr)>; 5864def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val), 5865 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>; 5866def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val), 5867 (STRH GPR:$val, addrmode3:$ptr)>; 5868def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val), 5869 (STRrs GPR:$val, ldst_so_reg:$ptr)>; 5870def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val), 5871 (STRi12 GPR:$val, addrmode_imm12:$ptr)>; 5872 5873 5874//===----------------------------------------------------------------------===// 5875// Thumb Support 5876// 5877 5878include "ARMInstrThumb.td" 5879 5880//===----------------------------------------------------------------------===// 5881// Thumb2 Support 5882// 5883 5884include "ARMInstrThumb2.td" 5885 5886//===----------------------------------------------------------------------===// 5887// Floating Point Support 5888// 5889 5890include "ARMInstrVFP.td" 5891 5892//===----------------------------------------------------------------------===// 5893// Advanced SIMD (NEON) Support 5894// 5895 5896include "ARMInstrNEON.td" 5897 5898//===----------------------------------------------------------------------===// 5899// Assembler aliases 5900// 5901 5902// Memory barriers 5903def : InstAlias<"dmb", (DMB 0xf), 0>, Requires<[IsARM, HasDB]>; 5904def : InstAlias<"dsb", (DSB 0xf), 0>, Requires<[IsARM, HasDB]>; 5905def : InstAlias<"isb", (ISB 0xf), 0>, Requires<[IsARM, HasDB]>; 5906// Armv8-R 'Data Full Barrier' 5907def : InstAlias<"dfb", (DSB 0xc), 1>, Requires<[IsARM, HasDFB]>; 5908 5909// System instructions 5910def : MnemonicAlias<"swi", "svc">; 5911 5912// Load / Store Multiple 5913def : MnemonicAlias<"ldmfd", "ldm">; 5914def : MnemonicAlias<"ldmia", "ldm">; 5915def : MnemonicAlias<"ldmea", "ldmdb">; 5916def : MnemonicAlias<"stmfd", "stmdb">; 5917def : MnemonicAlias<"stmia", "stm">; 5918def : MnemonicAlias<"stmea", "stm">; 5919 5920// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT with the 5921// input operands swapped when the shift amount is zero (i.e., unspecified). 5922def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm", 5923 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p), 0>, 5924 Requires<[IsARM, HasV6]>; 5925def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm", 5926 (PKHBT GPRnopc:$Rd, GPRnopc:$Rm, GPRnopc:$Rn, 0, pred:$p), 0>, 5927 Requires<[IsARM, HasV6]>; 5928 5929// PUSH/POP aliases for STM/LDM 5930def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>; 5931def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>; 5932 5933// SSAT/USAT optional shift operand. 5934def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn", 5935 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 5936def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn", 5937 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 5938 5939 5940// Extend instruction optional rotate operand. 5941def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm", 5942 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5943def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm", 5944 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5945def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm", 5946 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5947def : ARMInstAlias<"sxtb${p} $Rd, $Rm", 5948 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5949def : ARMInstAlias<"sxtb16${p} $Rd, $Rm", 5950 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5951def : ARMInstAlias<"sxth${p} $Rd, $Rm", 5952 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5953 5954def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm", 5955 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5956def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm", 5957 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5958def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm", 5959 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5960def : ARMInstAlias<"uxtb${p} $Rd, $Rm", 5961 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5962def : ARMInstAlias<"uxtb16${p} $Rd, $Rm", 5963 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5964def : ARMInstAlias<"uxth${p} $Rd, $Rm", 5965 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5966 5967 5968// RFE aliases 5969def : MnemonicAlias<"rfefa", "rfeda">; 5970def : MnemonicAlias<"rfeea", "rfedb">; 5971def : MnemonicAlias<"rfefd", "rfeia">; 5972def : MnemonicAlias<"rfeed", "rfeib">; 5973def : MnemonicAlias<"rfe", "rfeia">; 5974 5975// SRS aliases 5976def : MnemonicAlias<"srsfa", "srsib">; 5977def : MnemonicAlias<"srsea", "srsia">; 5978def : MnemonicAlias<"srsfd", "srsdb">; 5979def : MnemonicAlias<"srsed", "srsda">; 5980def : MnemonicAlias<"srs", "srsia">; 5981 5982// QSAX == QSUBADDX 5983def : MnemonicAlias<"qsubaddx", "qsax">; 5984// SASX == SADDSUBX 5985def : MnemonicAlias<"saddsubx", "sasx">; 5986// SHASX == SHADDSUBX 5987def : MnemonicAlias<"shaddsubx", "shasx">; 5988// SHSAX == SHSUBADDX 5989def : MnemonicAlias<"shsubaddx", "shsax">; 5990// SSAX == SSUBADDX 5991def : MnemonicAlias<"ssubaddx", "ssax">; 5992// UASX == UADDSUBX 5993def : MnemonicAlias<"uaddsubx", "uasx">; 5994// UHASX == UHADDSUBX 5995def : MnemonicAlias<"uhaddsubx", "uhasx">; 5996// UHSAX == UHSUBADDX 5997def : MnemonicAlias<"uhsubaddx", "uhsax">; 5998// UQASX == UQADDSUBX 5999def : MnemonicAlias<"uqaddsubx", "uqasx">; 6000// UQSAX == UQSUBADDX 6001def : MnemonicAlias<"uqsubaddx", "uqsax">; 6002// USAX == USUBADDX 6003def : MnemonicAlias<"usubaddx", "usax">; 6004 6005// "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like 6006// for isel. 6007def : ARMInstSubst<"mov${s}${p} $Rd, $imm", 6008 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6009def : ARMInstSubst<"mvn${s}${p} $Rd, $imm", 6010 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6011// Same for AND <--> BIC 6012def : ARMInstSubst<"bic${s}${p} $Rd, $Rn, $imm", 6013 (ANDri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, 6014 pred:$p, cc_out:$s)>; 6015def : ARMInstSubst<"bic${s}${p} $Rdn, $imm", 6016 (ANDri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, 6017 pred:$p, cc_out:$s)>; 6018def : ARMInstSubst<"and${s}${p} $Rd, $Rn, $imm", 6019 (BICri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, 6020 pred:$p, cc_out:$s)>; 6021def : ARMInstSubst<"and${s}${p} $Rdn, $imm", 6022 (BICri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, 6023 pred:$p, cc_out:$s)>; 6024 6025// Likewise, "add Rd, mod_imm_neg" -> sub 6026def : ARMInstSubst<"add${s}${p} $Rd, $Rn, $imm", 6027 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6028def : ARMInstSubst<"add${s}${p} $Rd, $imm", 6029 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6030// Likewise, "sub Rd, mod_imm_neg" -> add 6031def : ARMInstSubst<"sub${s}${p} $Rd, $Rn, $imm", 6032 (ADDri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6033def : ARMInstSubst<"sub${s}${p} $Rd, $imm", 6034 (ADDri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6035 6036 6037def : ARMInstSubst<"adc${s}${p} $Rd, $Rn, $imm", 6038 (SBCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6039def : ARMInstSubst<"adc${s}${p} $Rdn, $imm", 6040 (SBCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6041def : ARMInstSubst<"sbc${s}${p} $Rd, $Rn, $imm", 6042 (ADCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6043def : ARMInstSubst<"sbc${s}${p} $Rdn, $imm", 6044 (ADCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6045 6046// Same for CMP <--> CMN via mod_imm_neg 6047def : ARMInstSubst<"cmp${p} $Rd, $imm", 6048 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>; 6049def : ARMInstSubst<"cmn${p} $Rd, $imm", 6050 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>; 6051 6052// The shifter forms of the MOV instruction are aliased to the ASR, LSL, 6053// LSR, ROR, and RRX instructions. 6054// FIXME: We need C++ parser hooks to map the alias to the MOV 6055// encoding. It seems we should be able to do that sort of thing 6056// in tblgen, but it could get ugly. 6057let TwoOperandAliasConstraint = "$Rm = $Rd" in { 6058def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm", 6059 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 6060 cc_out:$s)>; 6061def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm", 6062 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 6063 cc_out:$s)>; 6064def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm", 6065 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 6066 cc_out:$s)>; 6067def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm", 6068 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 6069 cc_out:$s)>; 6070} 6071def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm", 6072 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>; 6073let TwoOperandAliasConstraint = "$Rn = $Rd" in { 6074def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm", 6075 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6076 cc_out:$s)>; 6077def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm", 6078 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6079 cc_out:$s)>; 6080def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm", 6081 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6082 cc_out:$s)>; 6083def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm", 6084 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6085 cc_out:$s)>; 6086} 6087 6088// "neg" is and alias for "rsb rd, rn, #0" 6089def : ARMInstAlias<"neg${s}${p} $Rd, $Rm", 6090 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>; 6091 6092// Pre-v6, 'mov r0, r0' was used as a NOP encoding. 6093def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>, 6094 Requires<[IsARM, NoV6]>; 6095 6096// MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but 6097// the instruction definitions need difference constraints pre-v6. 6098// Use these aliases for the assembly parsing on pre-v6. 6099def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm", 6100 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s), 0>, 6101 Requires<[IsARM, NoV6]>; 6102def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra", 6103 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 6104 pred:$p, cc_out:$s), 0>, 6105 Requires<[IsARM, NoV6]>; 6106def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6107 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6108 Requires<[IsARM, NoV6]>; 6109def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6110 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6111 Requires<[IsARM, NoV6]>; 6112def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6113 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6114 Requires<[IsARM, NoV6]>; 6115def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6116 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6117 Requires<[IsARM, NoV6]>; 6118 6119// 'it' blocks in ARM mode just validate the predicates. The IT itself 6120// is discarded. 6121def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>, 6122 ComplexDeprecationPredicate<"IT">; 6123 6124let mayLoad = 1, mayStore =1, hasSideEffects = 1 in 6125def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn), 6126 NoItinerary, 6127 [(set GPR:$Rd, (int_arm_space imm:$size, GPR:$Rn))]>; 6128 6129//===---------------------------------- 6130// Atomic cmpxchg for -O0 6131//===---------------------------------- 6132 6133// The fast register allocator used during -O0 inserts spills to cover any VRegs 6134// live across basic block boundaries. When this happens between an LDXR and an 6135// STXR it can clear the exclusive monitor, causing all cmpxchg attempts to 6136// fail. 6137 6138// Unfortunately, this means we have to have an alternative (expanded 6139// post-regalloc) path for -O0 compilations. Fortunately this path can be 6140// significantly more naive than the standard expansion: we conservatively 6141// assume seq_cst, strong cmpxchg and omit clrex on failure. 6142 6143let Constraints = "@earlyclobber $Rd,@earlyclobber $temp", 6144 mayLoad = 1, mayStore = 1 in { 6145def CMP_SWAP_8 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6146 (ins GPR:$addr, GPR:$desired, GPR:$new), 6147 NoItinerary, []>, Sched<[]>; 6148 6149def CMP_SWAP_16 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6150 (ins GPR:$addr, GPR:$desired, GPR:$new), 6151 NoItinerary, []>, Sched<[]>; 6152 6153def CMP_SWAP_32 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6154 (ins GPR:$addr, GPR:$desired, GPR:$new), 6155 NoItinerary, []>, Sched<[]>; 6156 6157def CMP_SWAP_64 : PseudoInst<(outs GPRPair:$Rd, GPR:$temp), 6158 (ins GPR:$addr, GPRPair:$desired, GPRPair:$new), 6159 NoItinerary, []>, Sched<[]>; 6160} 6161 6162def CompilerBarrier : PseudoInst<(outs), (ins i32imm:$ordering), NoItinerary, 6163 [(atomic_fence imm:$ordering, 0)]> { 6164 let hasSideEffects = 1; 6165 let Size = 0; 6166 let AsmString = "@ COMPILER BARRIER"; 6167} 6168