1; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
2
3; optnone disables AMDGPUAnnotateUniformValues, so no branch is known
4; to be uniform during instruction selection. The custom selection for
5; brcond was not checking if the branch was uniform, relying on the
6; selection pattern to check that. That would fail, so then the branch
7; would fail to select.
8
9; GCN-LABEL: {{^}}copytoreg_divergent_brcond:
10; GCN: s_branch
11
12; GCN-DAG: v_cmp_lt_i32
13; GCN-DAG: v_cmp_gt_i32
14; GCN: s_and_b64
15; GCN: s_mov_b64 exec
16
17; GCN: s_or_b64 exec, exec
18; GCN: v_cmp_eq_u32
19; GCN: s_cbranch_vccnz
20; GCN-NEXT: s_branch
21define amdgpu_kernel void @copytoreg_divergent_brcond(i32 %arg, i32 %arg1, i32 %arg2) #0 {
22bb:
23  %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
24  %tmp3 = zext i32 %tmp to i64
25  %tmp5 = add i64 %tmp3, undef
26  %tmp6 = trunc i64 %tmp5 to i32
27  %tmp7 = mul nsw i32 %tmp6, %arg2
28  br label %bb8
29
30bb8.loopexit:                                     ; preds = %bb14
31  br label %bb8
32
33bb8:                                              ; preds = %bb8.loopexit, %bb
34  br label %bb9
35
36bb9:                                              ; preds = %bb14, %bb8
37  %tmp10 = icmp slt i32 %tmp7, %arg1
38  %tmp11 = icmp sgt i32 %arg, 0
39  %tmp12 = and i1 %tmp10, %tmp11
40  br i1 %tmp12, label %bb13, label %bb14
41
42bb13:                                             ; preds = %bb9
43  store volatile i32 0, i32 addrspace(1)* undef, align 4
44  br label %bb14
45
46bb14:                                             ; preds = %bb13, %bb9
47  %tmp15 = icmp eq i32 %arg2, 1
48  br i1 %tmp15, label %bb8.loopexit, label %bb9
49}
50
51declare i32 @llvm.amdgcn.workitem.id.x() #1
52
53attributes #0 = { nounwind optnone noinline }
54attributes #1 = { nounwind readnone speculatable }
55