1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-SAFE -check-prefix=GCN %s 2; RUN: llc -enable-no-nans-fp-math -enable-unsafe-fp-math -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-NONAN -check-prefix=GCN %s 3 4; FIXME: Should replace unsafe-fp-math with no signed zeros. 5 6; GCN-LABEL: {{^}}min_fneg_select_regression_0: 7; GCN-SAFE: v_max_legacy_f32_e64 [[MIN:v[0-9]+]], -1.0, -v0 8; GCN-NONAN: v_max_f32_e64 v{{[0-9]+}}, -v0, -1.0 9define amdgpu_ps float @min_fneg_select_regression_0(float %a, float %b) #0 { 10 %fneg.a = fsub float -0.0, %a 11 %cmp.a = fcmp ult float %a, 1.0 12 %min.a = select i1 %cmp.a, float %fneg.a, float -1.0 13 ret float %min.a 14} 15 16; GCN-LABEL: {{^}}min_fneg_select_regression_posk_0: 17; GCN-SAFE: v_max_legacy_f32_e64 [[MIN:v[0-9]+]], 1.0, -v0 18; GCN-NONAN: v_max_f32_e64 v{{[0-9]+}}, -v0, 1.0 19define amdgpu_ps float @min_fneg_select_regression_posk_0(float %a, float %b) #0 { 20 %fneg.a = fsub float -0.0, %a 21 %cmp.a = fcmp ult float %a, -1.0 22 %min.a = select i1 %cmp.a, float %fneg.a, float 1.0 23 ret float %min.a 24} 25 26; GCN-LABEL: {{^}}max_fneg_select_regression_0: 27; GCN-SAFE: v_min_legacy_f32_e64 [[MIN:v[0-9]+]], -1.0, -v0 28; GCN-NONAN: v_min_f32_e64 [[MIN:v[0-9]+]], -v0, -1.0 29define amdgpu_ps float @max_fneg_select_regression_0(float %a, float %b) #0 { 30 %fneg.a = fsub float -0.0, %a 31 %cmp.a = fcmp ugt float %a, 1.0 32 %min.a = select i1 %cmp.a, float %fneg.a, float -1.0 33 ret float %min.a 34} 35 36; GCN-LABEL: {{^}}max_fneg_select_regression_posk_0: 37; GCN-SAFE: v_min_legacy_f32_e64 [[MIN:v[0-9]+]], 1.0, -v0 38; GCN-NONAN: v_min_f32_e64 [[MIN:v[0-9]+]], -v0, 1.0 39define amdgpu_ps float @max_fneg_select_regression_posk_0(float %a, float %b) #0 { 40 %fneg.a = fsub float -0.0, %a 41 %cmp.a = fcmp ugt float %a, -1.0 42 %min.a = select i1 %cmp.a, float %fneg.a, float 1.0 43 ret float %min.a 44} 45 46attributes #0 = { nounwind } 47attributes #1 = { nounwind readnone } 48