1; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s 2; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s 3 4; XXX - Why the packing? 5; GCN-LABEL: {{^}}scalar_to_vector_v2i32: 6; GCN: buffer_load_dword [[VAL:v[0-9]+]], 7; GCN: v_lshrrev_b32_e32 [[SHR:v[0-9]+]], 16, [[VAL]] 8; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 16, [[SHR]] 9; GCN: v_or_b32_e32 v[[OR:[0-9]+]], [[SHR]], [[SHL]] 10; GCN: v_mov_b32_e32 v[[COPY:[0-9]+]], v[[OR]] 11; GCN: buffer_store_dwordx2 v{{\[}}[[OR]]:[[COPY]]{{\]}} 12define amdgpu_kernel void @scalar_to_vector_v2i32(<4 x i16> addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { 13 %tmp1 = load i32, i32 addrspace(1)* %in, align 4 14 %bc = bitcast i32 %tmp1 to <2 x i16> 15 %tmp2 = shufflevector <2 x i16> %bc, <2 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> 16 store <4 x i16> %tmp2, <4 x i16> addrspace(1)* %out, align 8 17 ret void 18} 19 20; GCN-LABEL: {{^}}scalar_to_vector_v2f32: 21; GCN: buffer_load_dword [[VAL:v[0-9]+]], 22; GCN: v_lshrrev_b32_e32 [[RESULT:v[0-9]+]], 16, [[VAL]] 23; GCN: buffer_store_dwordx2 24define amdgpu_kernel void @scalar_to_vector_v2f32(<4 x i16> addrspace(1)* %out, float addrspace(1)* %in) nounwind { 25 %tmp1 = load float, float addrspace(1)* %in, align 4 26 %bc = bitcast float %tmp1 to <2 x i16> 27 %tmp2 = shufflevector <2 x i16> %bc, <2 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> 28 store <4 x i16> %tmp2, <4 x i16> addrspace(1)* %out, align 8 29 ret void 30} 31 32; GCN-LABEL: {{^}}scalar_to_vector_v4i16: 33; VI: v_lshlrev_b16_e32 34; VI: v_lshlrev_b16_e32 35; VI: v_or_b32_e32 36; VI: v_lshlrev_b32 37; VI: v_or_b32_sdwa 38; VI: v_or_b32_sdwa 39define amdgpu_kernel void @scalar_to_vector_v4i16() { 40bb: 41 %tmp = load <2 x i8>, <2 x i8> addrspace(1)* undef, align 1 42 %tmp1 = shufflevector <2 x i8> %tmp, <2 x i8> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> 43 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 0, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9> 44 store <8 x i8> %tmp2, <8 x i8> addrspace(1)* undef, align 8 45 ret void 46} 47 48; GCN-LABEL: {{^}}scalar_to_vector_v4f16: 49; VI: v_lshlrev_b16_e32 50; VI: v_lshlrev_b16_e32 51; VI: v_or_b32_e32 52; VI: v_lshlrev_b32 53; VI: v_or_b32_sdwa 54; VI: v_or_b32_sdwa 55define amdgpu_kernel void @scalar_to_vector_v4f16() { 56bb: 57 %load = load half, half addrspace(1)* undef, align 1 58 %tmp = bitcast half %load to <2 x i8> 59 %tmp1 = shufflevector <2 x i8> %tmp, <2 x i8> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> 60 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 0, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9> 61 store <8 x i8> %tmp2, <8 x i8> addrspace(1)* undef, align 8 62 ret void 63} 64 65; Getting a SCALAR_TO_VECTOR seems to be tricky. These cases managed 66; to produce one, but for some reason never made it to selection. 67 68 69; define amdgpu_kernel void @scalar_to_vector_test2(<8 x i8> addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { 70; %tmp1 = load i32, i32 addrspace(1)* %in, align 4 71; %bc = bitcast i32 %tmp1 to <4 x i8> 72 73; %tmp2 = shufflevector <4 x i8> %bc, <4 x i8> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> 74; store <8 x i8> %tmp2, <8 x i8> addrspace(1)* %out, align 4 75; ret void 76; } 77 78; define amdgpu_kernel void @scalar_to_vector_test3(<4 x i32> addrspace(1)* %out) nounwind { 79; %newvec0 = insertelement <2 x i64> undef, i64 12345, i32 0 80; %newvec1 = insertelement <2 x i64> %newvec0, i64 undef, i32 1 81; %bc = bitcast <2 x i64> %newvec1 to <4 x i32> 82; %add = add <4 x i32> %bc, <i32 1, i32 2, i32 3, i32 4> 83; store <4 x i32> %add, <4 x i32> addrspace(1)* %out, align 16 84; ret void 85; } 86 87; define amdgpu_kernel void @scalar_to_vector_test4(<8 x i16> addrspace(1)* %out) nounwind { 88; %newvec0 = insertelement <4 x i32> undef, i32 12345, i32 0 89; %bc = bitcast <4 x i32> %newvec0 to <8 x i16> 90; %add = add <8 x i16> %bc, <i16 1, i16 2, i16 3, i16 4, i16 1, i16 2, i16 3, i16 4> 91; store <8 x i16> %add, <8 x i16> addrspace(1)* %out, align 16 92; ret void 93; } 94 95; define amdgpu_kernel void @scalar_to_vector_test5(<4 x i16> addrspace(1)* %out) nounwind { 96; %newvec0 = insertelement <2 x i32> undef, i32 12345, i32 0 97; %bc = bitcast <2 x i32> %newvec0 to <4 x i16> 98; %add = add <4 x i16> %bc, <i16 1, i16 2, i16 3, i16 4> 99; store <4 x i16> %add, <4 x i16> addrspace(1)* %out, align 16 100; ret void 101; } 102 103define amdgpu_kernel void @scalar_to_vector_test6(<2 x half> addrspace(1)* %out, i8 zeroext %val) nounwind { 104 %newvec0 = insertelement <4 x i8> undef, i8 %val, i32 0 105 %bc = bitcast <4 x i8> %newvec0 to <2 x half> 106 store <2 x half> %bc, <2 x half> addrspace(1)* %out 107 ret void 108} 109