1;RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s
2;RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=VI --check-prefix=FUNC %s
3;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG --check-prefix=FUNC %s
4
5; FUNC-LABEL: {{^}}test_select_v2i32:
6
7; EG-DAG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW]}}, KC0[3].Z
8; EG-DAG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW]}}, KC0[3].Y
9
10; SI: v_cmp_gt_i32_e32 vcc
11; SI: v_cndmask_b32_e32
12; SI: v_cmp_gt_i32_e32 vcc
13; SI: v_cndmask_b32_e32
14
15define amdgpu_kernel void @test_select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in0, <2 x i32> addrspace(1)* %in1, <2 x i32> %val) {
16entry:
17  %load0 = load <2 x i32>, <2 x i32> addrspace(1)* %in0
18  %load1 = load <2 x i32>, <2 x i32> addrspace(1)* %in1
19  %cmp = icmp sgt <2 x i32> %load0, %load1
20  %result = select <2 x i1> %cmp, <2 x i32> %val, <2 x i32> %load0
21  store <2 x i32> %result, <2 x i32> addrspace(1)* %out
22  ret void
23}
24
25; FUNC-LABEL: {{^}}test_select_v2f32:
26
27; EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
28; EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
29
30
31; SI: v_cmp_neq_f32_e32 vcc
32; SI: v_cndmask_b32_e32
33; SI: v_cmp_neq_f32_e32 vcc
34; SI: v_cndmask_b32_e32
35
36define amdgpu_kernel void @test_select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in0, <2 x float> addrspace(1)* %in1) {
37entry:
38  %0 = load <2 x float>, <2 x float> addrspace(1)* %in0
39  %1 = load <2 x float>, <2 x float> addrspace(1)* %in1
40  %cmp = fcmp une <2 x float> %0, %1
41  %result = select <2 x i1> %cmp, <2 x float> %0, <2 x float> %1
42  store <2 x float> %result, <2 x float> addrspace(1)* %out
43  ret void
44}
45
46;FUNC-LABEL: {{^}}test_select_v4i32:
47
48; EG-DAG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW]}}, KC0[4].X
49; EG-DAG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, KC0[3].W
50; EG-DAG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW]}}, KC0[3].Z
51; EG-DAG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW]}}, KC0[3].Y
52
53; SI: v_cndmask_b32_e32
54; SI: v_cndmask_b32_e32
55; SI: v_cndmask_b32_e32
56; SI: v_cndmask_b32_e32
57
58define amdgpu_kernel void @test_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1, <4 x i32> %val) {
59entry:
60  %load0 = load <4 x i32>, <4 x i32> addrspace(1)* %in0
61  %load1 = load <4 x i32>, <4 x i32> addrspace(1)* %in1
62  %cmp = icmp sgt <4 x i32> %load0, %load1
63  %result = select <4 x i1> %cmp, <4 x i32> %val, <4 x i32> %load0
64  store <4 x i32> %result, <4 x i32> addrspace(1)* %out
65  ret void
66}
67
68;FUNC-LABEL: {{^}}test_select_v4f32:
69;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
70;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
71;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
72;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
73
74; SI: v_cndmask_b32_e32
75; SI: v_cndmask_b32_e32
76; SI: v_cndmask_b32_e32
77; SI: v_cndmask_b32_e32
78define amdgpu_kernel void @test_select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in0, <4 x float> addrspace(1)* %in1) {
79entry:
80  %0 = load <4 x float>, <4 x float> addrspace(1)* %in0
81  %1 = load <4 x float>, <4 x float> addrspace(1)* %in1
82  %cmp = fcmp une <4 x float> %0, %1
83  %result = select <4 x i1> %cmp, <4 x float> %0, <4 x float> %1
84  store <4 x float> %result, <4 x float> addrspace(1)* %out
85  ret void
86}
87